include/configs/MPC8315ERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
   4  *
   5  * Dave Liu <daveliu@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  12 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  13 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  14 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  15 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 /*
  22  * High Level Configuration Options
  23  */
  24 #define CONFIG_E300             1 /* E300 family */
  25
  26 /*
  27  * System IO Config
  28  */
  29 #define CONFIG_SYS_SICRH                0x00000000
  30 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  31
  32 #define CONFIG_HWCONFIG
  33
  34 /*
  35  * IMMR new address
  36  */
  37 #define CONFIG_SYS_IMMR         0xE0000000
  38
  39 /*
  40  * Arbiter Setup
  41  */
  42 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  43 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  44 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  45
  46 /*
  47  * DDR Setup
  48  */
  49 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  50 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  51 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  52 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  53 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  54                                 | DDRCDR_PZ_LOZ \
  55                                 | DDRCDR_NZ_LOZ \
  56                                 | DDRCDR_ODT \
  57                                 | DDRCDR_Q_DRN)
  58                                 /* 0x7b880001 */
  59 /*
  60  * Manually set up DDR parameters
  61  * consist of two chips HY5PS12621BFP-C4 from HYNIX
  62  */
  63 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  64 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  65 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  66                                 | CSCONFIG_ODT_RD_NEVER \
  67                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  68                                 | CSCONFIG_ROW_BIT_13 \
  69                                 | CSCONFIG_COL_BIT_10)
  70                                 /* 0x80010102 */
  71 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  72 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  73                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  74                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  75                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  76                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  77                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  78                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  79                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  80                                 /* 0x00220802 */
  81 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  82                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  83                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  84                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  85                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
  86                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  87                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  88                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  89                                 /* 0x27256222 */
  90 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  91                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
  92                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  93                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  94                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  95                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  96                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  97                                 /* 0x121048c5 */
  98 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
  99                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 100                                 /* 0x03600100 */
 101 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 102                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 103                                 | SDRAM_CFG_DBW_32)
 104                                 /* 0x43080000 */
 105 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 106 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 107                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 108                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 109 #define CONFIG_SYS_DDR_MODE2    0x00000000
 110
 111 /*
 112  * Memory test
 113  */
 114 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 115 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 116 #define CONFIG_SYS_MEMTEST_END          0x00140000
 117
 118 /*
 119  * The reserved memory
 120  */
 121 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 122 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 123
 124 /*
 125  * Initial RAM Base Address Setup
 126  */
 127 #define CONFIG_SYS_INIT_RAM_LOCK        1
 128 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 129 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 130 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 131                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 132
 133 /*
 134  * Local Bus Configuration & Clock Setup
 135  */
 136 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 137 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 138 #define CONFIG_SYS_LBC_LBCR             0x00040000
 139 #define CONFIG_FSL_ELBC         1
 140
 141 /*
 142  * FLASH on the Local Bus
 143  */
 144 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 145
 146 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 147 #define CONFIG_SYS_FLASH_SIZE           8       /* FLASH size is 8M */
 148
 149                                         /* Window base at flash base */
 150 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 151 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 152
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 154 /* 127 64KB sectors and 8 8KB top sectors per device */
 155 #define CONFIG_SYS_MAX_FLASH_SECT       135
 156
 157 #undef CONFIG_SYS_FLASH_CHECKSUM
 158 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 159 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 160
 161 /*
 162  * NAND Flash on the Local Bus
 163  */
 164
 165 #ifdef CONFIG_NAND_SPL
 166 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 167 #else
 168 #define CONFIG_SYS_NAND_BASE            0xE0600000
 169 #endif
 170
 171 #define CONFIG_MTD_PARTITION
 172
 173 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 174 #define CONFIG_NAND_FSL_ELBC            1
 175 #define CONFIG_SYS_NAND_BLOCK_SIZE      16384
 176 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 177
 178 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 179 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 180 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 181 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 182 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 183
 184 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
 185                                         | BR_PS_16      /* 16 bit port */ \
 186                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 187                                         | BR_V)         /* valid */
 188 #define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
 189                                         | OR_UPM_XAM \
 190                                         | OR_GPCM_CSNT \
 191                                         | OR_GPCM_ACS_DIV2 \
 192                                         | OR_GPCM_XACS \
 193                                         | OR_GPCM_SCY_15 \
 194                                         | OR_GPCM_TRLX_SET \
 195                                         | OR_GPCM_EHTR_SET \
 196                                         | OR_GPCM_EAD)
 197 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
 198                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 199                                 | BR_PS_8               /* 8 bit port */ \
 200                                 | BR_MS_FCM             /* MSEL = FCM */ \
 201                                 | BR_V)                 /* valid */
 202 #define CONFIG_SYS_OR1_PRELIM \
 203                                 (OR_AM_32KB \
 204                                 | OR_FCM_CSCT \
 205                                 | OR_FCM_CST \
 206                                 | OR_FCM_CHT \
 207                                 | OR_FCM_SCY_1 \
 208                                 | OR_FCM_TRLX \
 209                                 | OR_FCM_EHTR)
 210                                 /* 0xFFFF8396 */
 211
 212 /* Still needed for spl_minimal.c */
 213 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 214 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 215
 216 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 217 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 218
 219 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 220 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 221
 222 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 223         !defined(CONFIG_NAND_SPL)
 224 #define CONFIG_SYS_RAMBOOT
 225 #else
 226 #undef CONFIG_SYS_RAMBOOT
 227 #endif
 228
 229 /*
 230  * Serial Port
 231  */
 232 #define CONFIG_SYS_NS16550_SERIAL
 233 #define CONFIG_SYS_NS16550_REG_SIZE     1
 234 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0))
 235
 236 #define CONFIG_SYS_BAUDRATE_TABLE  \
 237                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 238
 239 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 240 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 241
 242 /* I2C */
 243 #define CONFIG_SYS_I2C
 244 #define CONFIG_SYS_I2C_FSL
 245 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 246 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 247 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 248 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 249
 250 /*
 251  * Board info - revision and where boot from
 252  */
 253 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 254
 255 /*
 256  * Config on-board RTC
 257  */
 258 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 259 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 260
 261 /*
 262  * General PCI
 263  * Addresses are mapped 1-1.
 264  */
 265 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 266 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 267 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 268 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 269 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 270 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 271 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 272 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 273 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 274
 275 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 276 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 277 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 278
 279 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 280 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 281 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 282 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 283 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 284 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 285 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 286 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 287 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 288
 289 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 290 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 291 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 292 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 293 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 294 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 295 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 296 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 297 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 298
 299 #define CONFIG_PCI_INDIRECT_BRIDGE
 300 #define CONFIG_PCIE
 301
 302 #define CONFIG_EEPRO100
 303 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 304 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 305
 306 #define CONFIG_HAS_FSL_DR_USB
 307 #define CONFIG_SYS_SCCR_USBDRCM         3
 308
 309 #define CONFIG_USB_EHCI_FSL
 310 #define CONFIG_USB_PHY_TYPE     "utmi"
 311 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 312
 313 /*
 314  * TSEC
 315  */
 316 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 317 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 318 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 319 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 320
 321 /*
 322  * TSEC ethernet configuration
 323  */
 324 #define CONFIG_TSEC1            1
 325 #define CONFIG_TSEC1_NAME       "eTSEC0"
 326 #define CONFIG_TSEC2            1
 327 #define CONFIG_TSEC2_NAME       "eTSEC1"
 328 #define TSEC1_PHY_ADDR          0
 329 #define TSEC2_PHY_ADDR          1
 330 #define TSEC1_PHYIDX            0
 331 #define TSEC2_PHYIDX            0
 332 #define TSEC1_FLAGS             TSEC_GIGABIT
 333 #define TSEC2_FLAGS             TSEC_GIGABIT
 334
 335 /* Options are: eTSEC[0-1] */
 336 #define CONFIG_ETHPRIME         "eTSEC1"
 337
 338 /*
 339  * SATA
 340  */
 341 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 342 #define CONFIG_SATA1
 343 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 344 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 345 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 346 #define CONFIG_SATA2
 347 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 348 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 349 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 350
 351 #ifdef CONFIG_FSL_SATA
 352 #define CONFIG_LBA48
 353 #endif
 354
 355 /*
 356  * Environment
 357  */
 358 #if !defined(CONFIG_SYS_RAMBOOT)
 359         #define CONFIG_ENV_ADDR         \
 360                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 361         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 362         #define CONFIG_ENV_SIZE         0x2000
 363 #else
 364         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 365         #define CONFIG_ENV_SIZE         0x2000
 366 #endif
 367
 368 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 369 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 370
 371 /*
 372  * BOOTP options
 373  */
 374 #define CONFIG_BOOTP_BOOTFILESIZE
 375
 376 /*
 377  * Command line configuration.
 378  */
 379
 380 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 381
 382 /*
 383  * Miscellaneous configurable options
 384  */
 385 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 386
 387 /*
 388  * For booting Linux, the board info and command line data
 389  * have to be in the first 256 MB of memory, since this is
 390  * the maximum mapped by the Linux kernel during initialization.
 391  */
 392 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 393 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 394
 395 /*
 396  * Core HID Setup
 397  */
 398 #define CONFIG_SYS_HID0_INIT    0x000000000
 399 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 400                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 401                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 402 #define CONFIG_SYS_HID2         HID2_HBE
 403
 404 /*
 405  * MMU Setup
 406  */
 407 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 408
 409 /* DDR: cache cacheable */
 410 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 411                                 | BATL_PP_RW \
 412                                 | BATL_MEMCOHERENCE)
 413 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 414                                 | BATU_BL_128M \
 415                                 | BATU_VS \
 416                                 | BATU_VP)
 417 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 418 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 419
 420 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 421 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 422                                 | BATL_PP_RW \
 423                                 | BATL_CACHEINHIBIT \
 424                                 | BATL_GUARDEDSTORAGE)
 425 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 426                                 | BATU_BL_8M \
 427                                 | BATU_VS \
 428                                 | BATU_VP)
 429 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 430 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 431
 432 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 433 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 434                                 | BATL_PP_RW \
 435                                 | BATL_MEMCOHERENCE)
 436 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 437                                 | BATU_BL_32M \
 438                                 | BATU_VS \
 439                                 | BATU_VP)
 440 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 441                                 | BATL_PP_RW \
 442                                 | BATL_CACHEINHIBIT \
 443                                 | BATL_GUARDEDSTORAGE)
 444 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 445
 446 /* Stack in dcache: cacheable, no memory coherence */
 447 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 448 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR \
 449                                 | BATU_BL_128K \
 450                                 | BATU_VS \
 451                                 | BATU_VP)
 452 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 453 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 454
 455 /* PCI MEM space: cacheable */
 456 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI_MEM_PHYS \
 457                                 | BATL_PP_RW \
 458                                 | BATL_MEMCOHERENCE)
 459 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI_MEM_PHYS \
 460                                 | BATU_BL_256M \
 461                                 | BATU_VS \
 462                                 | BATU_VP)
 463 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 464 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 465
 466 /* PCI MMIO space: cache-inhibit and guarded */
 467 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI_MMIO_PHYS \
 468                                 | BATL_PP_RW \
 469                                 | BATL_CACHEINHIBIT \
 470                                 | BATL_GUARDEDSTORAGE)
 471 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI_MMIO_PHYS \
 472                                 | BATU_BL_256M \
 473                                 | BATU_VS \
 474                                 | BATU_VP)
 475 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 476 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 477
 478 #define CONFIG_SYS_IBAT6L       0
 479 #define CONFIG_SYS_IBAT6U       0
 480 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 481 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 482
 483 #define CONFIG_SYS_IBAT7L       0
 484 #define CONFIG_SYS_IBAT7U       0
 485 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 486 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 487
 488 #if defined(CONFIG_CMD_KGDB)
 489 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 490 #endif
 491
 492 /*
 493  * Environment Configuration
 494  */
 495
 496 #define CONFIG_ENV_OVERWRITE
 497
 498 #if defined(CONFIG_TSEC_ENET)
 499 #define CONFIG_HAS_ETH0
 500 #define CONFIG_HAS_ETH1
 501 #endif
 502
 503 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 504
 505 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 506         "netdev=eth0\0"                                                 \
 507         "consoledev=ttyS0\0"                                            \
 508         "ramdiskaddr=1000000\0"                                         \
 509         "ramdiskfile=ramfs.83xx\0"                                      \
 510         "fdtaddr=780000\0"                                              \
 511         "fdtfile=mpc8315erdb.dtb\0"                                     \
 512         "usb_phy_type=utmi\0"                                           \
 513         ""
 514
 515 #define CONFIG_NFSBOOTCOMMAND                                           \
 516         "setenv bootargs root=/dev/nfs rw "                             \
 517                 "nfsroot=$serverip:$rootpath "                          \
 518                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 519                                                         "$netdev:off "  \
 520                 "console=$consoledev,$baudrate $othbootargs;"           \
 521         "tftp $loadaddr $bootfile;"                                     \
 522         "tftp $fdtaddr $fdtfile;"                                       \
 523         "bootm $loadaddr - $fdtaddr"
 524
 525 #define CONFIG_RAMBOOTCOMMAND                                           \
 526         "setenv bootargs root=/dev/ram rw "                             \
 527                 "console=$consoledev,$baudrate $othbootargs;"           \
 528         "tftp $ramdiskaddr $ramdiskfile;"                               \
 529         "tftp $loadaddr $bootfile;"                                     \
 530         "tftp $fdtaddr $fdtfile;"                                       \
 531         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 532
 533 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 534
 535 #endif  /* __CONFIG_H */