include/configs/MPC8315ERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
   4  *
   5  * Dave Liu <daveliu@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  12 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  13 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  14 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  15 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 /*
  22  * High Level Configuration Options
  23  */
  24 #define CONFIG_E300             1 /* E300 family */
  25 #define CONFIG_MPC831x          1 /* MPC831x CPU family */
  26 #define CONFIG_MPC8315          1 /* MPC8315 CPU specific */
  27 #define CONFIG_MPC8315ERDB      1 /* MPC8315ERDB board specific */
  28
  29 /*
  30  * System Clock Setup
  31  */
  32 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  33 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  34
  35 /*
  36  * Hardware Reset Configuration Word
  37  * if CLKIN is 66.66MHz, then
  38  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
  39  */
  40 #define CONFIG_SYS_HRCW_LOW (\
  41         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  42         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  43         HRCWL_SVCOD_DIV_2 |\
  44         HRCWL_CSB_TO_CLKIN_2X1 |\
  45         HRCWL_CORE_TO_CSB_3X1)
  46 #define CONFIG_SYS_HRCW_HIGH_BASE (\
  47         HRCWH_PCI_HOST |\
  48         HRCWH_PCI1_ARBITER_ENABLE |\
  49         HRCWH_CORE_ENABLE |\
  50         HRCWH_BOOTSEQ_DISABLE |\
  51         HRCWH_SW_WATCHDOG_DISABLE |\
  52         HRCWH_TSEC1M_IN_RGMII |\
  53         HRCWH_TSEC2M_IN_RGMII |\
  54         HRCWH_BIG_ENDIAN |\
  55         HRCWH_LALE_NORMAL)
  56
  57 #ifdef CONFIG_NAND_SPL
  58 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  59                        HRCWH_FROM_0XFFF00100 |\
  60                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
  61                        HRCWH_RL_EXT_NAND)
  62 #else
  63 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  64                        HRCWH_FROM_0X00000100 |\
  65                        HRCWH_ROM_LOC_LOCAL_16BIT |\
  66                        HRCWH_RL_EXT_LEGACY)
  67 #endif
  68
  69 /*
  70  * System IO Config
  71  */
  72 #define CONFIG_SYS_SICRH                0x00000000
  73 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  74
  75 #define CONFIG_HWCONFIG
  76
  77 /*
  78  * IMMR new address
  79  */
  80 #define CONFIG_SYS_IMMR         0xE0000000
  81
  82 /*
  83  * Arbiter Setup
  84  */
  85 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  86 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  87 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  88
  89 /*
  90  * DDR Setup
  91  */
  92 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  96 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  97                                 | DDRCDR_PZ_LOZ \
  98                                 | DDRCDR_NZ_LOZ \
  99                                 | DDRCDR_ODT \
 100                                 | DDRCDR_Q_DRN)
 101                                 /* 0x7b880001 */
 102 /*
 103  * Manually set up DDR parameters
 104  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 105  */
 106 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 107 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 108 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 109                                 | CSCONFIG_ODT_RD_NEVER \
 110                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 111                                 | CSCONFIG_ROW_BIT_13 \
 112                                 | CSCONFIG_COL_BIT_10)
 113                                 /* 0x80010102 */
 114 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 115 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 116                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 117                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 118                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 119                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 120                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 121                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 122                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 123                                 /* 0x00220802 */
 124 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 125                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 126                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 127                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 128                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 129                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 130                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 131                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 132                                 /* 0x27256222 */
 133 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 134                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 135                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 136                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 137                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 138                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 139                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 140                                 /* 0x121048c5 */
 141 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 142                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 143                                 /* 0x03600100 */
 144 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 145                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 146                                 | SDRAM_CFG_DBW_32)
 147                                 /* 0x43080000 */
 148 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 149 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 150                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 151                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 152 #define CONFIG_SYS_DDR_MODE2    0x00000000
 153
 154 /*
 155  * Memory test
 156  */
 157 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 158 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 159 #define CONFIG_SYS_MEMTEST_END          0x00140000
 160
 161 /*
 162  * The reserved memory
 163  */
 164 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 165 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 166
 167 /*
 168  * Initial RAM Base Address Setup
 169  */
 170 #define CONFIG_SYS_INIT_RAM_LOCK        1
 171 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 172 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 173 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 174                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 175
 176 /*
 177  * Local Bus Configuration & Clock Setup
 178  */
 179 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 180 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 181 #define CONFIG_SYS_LBC_LBCR             0x00040000
 182 #define CONFIG_FSL_ELBC         1
 183
 184 /*
 185  * FLASH on the Local Bus
 186  */
 187 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 188 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 189 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 190
 191 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 192 #define CONFIG_SYS_FLASH_SIZE           8       /* FLASH size is 8M */
 193 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 194
 195                                         /* Window base at flash base */
 196 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 197 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 198
 199 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 200                                         | BR_PS_16      /* 16 bit port */ \
 201                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 202                                         | BR_V)         /* valid */
 203 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 204                                         | OR_UPM_XAM \
 205                                         | OR_GPCM_CSNT \
 206                                         | OR_GPCM_ACS_DIV2 \
 207                                         | OR_GPCM_XACS \
 208                                         | OR_GPCM_SCY_15 \
 209                                         | OR_GPCM_TRLX_SET \
 210                                         | OR_GPCM_EHTR_SET \
 211                                         | OR_GPCM_EAD)
 212
 213 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 214 /* 127 64KB sectors and 8 8KB top sectors per device */
 215 #define CONFIG_SYS_MAX_FLASH_SECT       135
 216
 217 #undef CONFIG_SYS_FLASH_CHECKSUM
 218 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 219 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 220
 221 /*
 222  * NAND Flash on the Local Bus
 223  */
 224
 225 #ifdef CONFIG_NAND_SPL
 226 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 227 #else
 228 #define CONFIG_SYS_NAND_BASE            0xE0600000
 229 #endif
 230
 231 #define CONFIG_MTD_PARTITION
 232
 233 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 234 #define CONFIG_NAND_FSL_ELBC            1
 235 #define CONFIG_SYS_NAND_BLOCK_SIZE      16384
 236 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 237
 238 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 239 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 240 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 241 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 242 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 243
 244 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 245                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 246                                 | BR_PS_8               /* 8 bit port */ \
 247                                 | BR_MS_FCM             /* MSEL = FCM */ \
 248                                 | BR_V)                 /* valid */
 249 #define CONFIG_SYS_NAND_OR_PRELIM       \
 250                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 251                                 | OR_FCM_CSCT \
 252                                 | OR_FCM_CST \
 253                                 | OR_FCM_CHT \
 254                                 | OR_FCM_SCY_1 \
 255                                 | OR_FCM_TRLX \
 256                                 | OR_FCM_EHTR)
 257                                 /* 0xFFFF8396 */
 258
 259 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 260 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 261 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 262 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 263
 264 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 265 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 266
 267 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 268 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 269
 270 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 271         !defined(CONFIG_NAND_SPL)
 272 #define CONFIG_SYS_RAMBOOT
 273 #else
 274 #undef CONFIG_SYS_RAMBOOT
 275 #endif
 276
 277 /*
 278  * Serial Port
 279  */
 280 #define CONFIG_SYS_NS16550_SERIAL
 281 #define CONFIG_SYS_NS16550_REG_SIZE     1
 282 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 2)
 283
 284 #define CONFIG_SYS_BAUDRATE_TABLE  \
 285                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 286
 287 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 288 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 289
 290 /* I2C */
 291 #define CONFIG_SYS_I2C
 292 #define CONFIG_SYS_I2C_FSL
 293 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 294 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 295 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 296 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 297
 298 /*
 299  * Board info - revision and where boot from
 300  */
 301 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 302
 303 /*
 304  * Config on-board RTC
 305  */
 306 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 307 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 308
 309 /*
 310  * General PCI
 311  * Addresses are mapped 1-1.
 312  */
 313 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 314 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 315 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 316 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 317 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 318 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 319 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 320 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 321 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 322
 323 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 324 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 325 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 326
 327 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 328 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 329 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 330 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 331 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 332 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 333 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 334 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 335 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 336
 337 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 338 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 339 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 340 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 341 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 342 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 343 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 344 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 345 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 346
 347 #define CONFIG_PCI_INDIRECT_BRIDGE
 348 #define CONFIG_PCIE
 349
 350 #define CONFIG_EEPRO100
 351 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 352 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 353
 354 #define CONFIG_HAS_FSL_DR_USB
 355 #define CONFIG_SYS_SCCR_USBDRCM         3
 356
 357 #define CONFIG_USB_EHCI_FSL
 358 #define CONFIG_USB_PHY_TYPE     "utmi"
 359 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 360
 361 /*
 362  * TSEC
 363  */
 364 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 365 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 366 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 367 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 368
 369 /*
 370  * TSEC ethernet configuration
 371  */
 372 #define CONFIG_MII              1 /* MII PHY management */
 373 #define CONFIG_TSEC1            1
 374 #define CONFIG_TSEC1_NAME       "eTSEC0"
 375 #define CONFIG_TSEC2            1
 376 #define CONFIG_TSEC2_NAME       "eTSEC1"
 377 #define TSEC1_PHY_ADDR          0
 378 #define TSEC2_PHY_ADDR          1
 379 #define TSEC1_PHYIDX            0
 380 #define TSEC2_PHYIDX            0
 381 #define TSEC1_FLAGS             TSEC_GIGABIT
 382 #define TSEC2_FLAGS             TSEC_GIGABIT
 383
 384 /* Options are: eTSEC[0-1] */
 385 #define CONFIG_ETHPRIME         "eTSEC1"
 386
 387 /*
 388  * SATA
 389  */
 390 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 391 #define CONFIG_SATA1
 392 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 393 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 394 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 395 #define CONFIG_SATA2
 396 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 397 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 398 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 399
 400 #ifdef CONFIG_FSL_SATA
 401 #define CONFIG_LBA48
 402 #endif
 403
 404 /*
 405  * Environment
 406  */
 407 #if !defined(CONFIG_SYS_RAMBOOT)
 408         #define CONFIG_ENV_ADDR         \
 409                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 410         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 411         #define CONFIG_ENV_SIZE         0x2000
 412 #else
 413         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 414         #define CONFIG_ENV_SIZE         0x2000
 415 #endif
 416
 417 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 418 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 419
 420 /*
 421  * BOOTP options
 422  */
 423 #define CONFIG_BOOTP_BOOTFILESIZE
 424
 425 /*
 426  * Command line configuration.
 427  */
 428
 429 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 430
 431 /*
 432  * Miscellaneous configurable options
 433  */
 434 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 435
 436 /*
 437  * For booting Linux, the board info and command line data
 438  * have to be in the first 256 MB of memory, since this is
 439  * the maximum mapped by the Linux kernel during initialization.
 440  */
 441 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 442 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 443
 444 /*
 445  * Core HID Setup
 446  */
 447 #define CONFIG_SYS_HID0_INIT    0x000000000
 448 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 449                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 450                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 451 #define CONFIG_SYS_HID2         HID2_HBE
 452
 453 /*
 454  * MMU Setup
 455  */
 456 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 457
 458 /* DDR: cache cacheable */
 459 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 460                                 | BATL_PP_RW \
 461                                 | BATL_MEMCOHERENCE)
 462 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 463                                 | BATU_BL_128M \
 464                                 | BATU_VS \
 465                                 | BATU_VP)
 466 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 467 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 468
 469 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 470 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 471                                 | BATL_PP_RW \
 472                                 | BATL_CACHEINHIBIT \
 473                                 | BATL_GUARDEDSTORAGE)
 474 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 475                                 | BATU_BL_8M \
 476                                 | BATU_VS \
 477                                 | BATU_VP)
 478 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 479 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 480
 481 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 482 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 483                                 | BATL_PP_RW \
 484                                 | BATL_MEMCOHERENCE)
 485 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 486                                 | BATU_BL_32M \
 487                                 | BATU_VS \
 488                                 | BATU_VP)
 489 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 490                                 | BATL_PP_RW \
 491                                 | BATL_CACHEINHIBIT \
 492                                 | BATL_GUARDEDSTORAGE)
 493 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 494
 495 /* Stack in dcache: cacheable, no memory coherence */
 496 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 497 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR \
 498                                 | BATU_BL_128K \
 499                                 | BATU_VS \
 500                                 | BATU_VP)
 501 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 502 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 503
 504 /* PCI MEM space: cacheable */
 505 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI_MEM_PHYS \
 506                                 | BATL_PP_RW \
 507                                 | BATL_MEMCOHERENCE)
 508 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI_MEM_PHYS \
 509                                 | BATU_BL_256M \
 510                                 | BATU_VS \
 511                                 | BATU_VP)
 512 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 513 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 514
 515 /* PCI MMIO space: cache-inhibit and guarded */
 516 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI_MMIO_PHYS \
 517                                 | BATL_PP_RW \
 518                                 | BATL_CACHEINHIBIT \
 519                                 | BATL_GUARDEDSTORAGE)
 520 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI_MMIO_PHYS \
 521                                 | BATU_BL_256M \
 522                                 | BATU_VS \
 523                                 | BATU_VP)
 524 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 525 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 526
 527 #define CONFIG_SYS_IBAT6L       0
 528 #define CONFIG_SYS_IBAT6U       0
 529 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 530 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 531
 532 #define CONFIG_SYS_IBAT7L       0
 533 #define CONFIG_SYS_IBAT7U       0
 534 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 535 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 536
 537 #if defined(CONFIG_CMD_KGDB)
 538 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 539 #endif
 540
 541 /*
 542  * Environment Configuration
 543  */
 544
 545 #define CONFIG_ENV_OVERWRITE
 546
 547 #if defined(CONFIG_TSEC_ENET)
 548 #define CONFIG_HAS_ETH0
 549 #define CONFIG_HAS_ETH1
 550 #endif
 551
 552 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 553
 554 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 555         "netdev=eth0\0"                                                 \
 556         "consoledev=ttyS0\0"                                            \
 557         "ramdiskaddr=1000000\0"                                         \
 558         "ramdiskfile=ramfs.83xx\0"                                      \
 559         "fdtaddr=780000\0"                                              \
 560         "fdtfile=mpc8315erdb.dtb\0"                                     \
 561         "usb_phy_type=utmi\0"                                           \
 562         ""
 563
 564 #define CONFIG_NFSBOOTCOMMAND                                           \
 565         "setenv bootargs root=/dev/nfs rw "                             \
 566                 "nfsroot=$serverip:$rootpath "                          \
 567                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 568                                                         "$netdev:off "  \
 569                 "console=$consoledev,$baudrate $othbootargs;"           \
 570         "tftp $loadaddr $bootfile;"                                     \
 571         "tftp $fdtaddr $fdtfile;"                                       \
 572         "bootm $loadaddr - $fdtaddr"
 573
 574 #define CONFIG_RAMBOOTCOMMAND                                           \
 575         "setenv bootargs root=/dev/ram rw "                             \
 576                 "console=$consoledev,$baudrate $othbootargs;"           \
 577         "tftp $ramdiskaddr $ramdiskfile;"                               \
 578         "tftp $loadaddr $bootfile;"                                     \
 579         "tftp $fdtaddr $fdtfile;"                                       \
 580         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 581
 582 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 583
 584 #endif  /* __CONFIG_H */