include/configs/MPC8315ERDB.h

   1 /*
   2  * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /*
  29  * High Level Configuration Options
  30  */
  31 #define CONFIG_E300             1 /* E300 family */
  32 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  33 #define CONFIG_MPC831x          1 /* MPC831x CPU family */
  34 #define CONFIG_MPC8315          1 /* MPC8315 CPU specific */
  35 #define CONFIG_MPC8315ERDB      1 /* MPC8315ERDB board specific */
  36
  37 /*
  38  * System Clock Setup
  39  */
  40 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  41 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  42
  43 /*
  44  * Hardware Reset Configuration Word
  45  * if CLKIN is 66.66MHz, then
  46  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
  47  */
  48 #define CONFIG_SYS_HRCW_LOW (\
  49         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  50         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  51         HRCWL_SVCOD_DIV_2 |\
  52         HRCWL_CSB_TO_CLKIN_2X1 |\
  53         HRCWL_CORE_TO_CSB_3X1)
  54 #define CONFIG_SYS_HRCW_HIGH (\
  55         HRCWH_PCI_HOST |\
  56         HRCWH_PCI1_ARBITER_ENABLE |\
  57         HRCWH_CORE_ENABLE |\
  58         HRCWH_FROM_0X00000100 |\
  59         HRCWH_BOOTSEQ_DISABLE |\
  60         HRCWH_SW_WATCHDOG_DISABLE |\
  61         HRCWH_ROM_LOC_LOCAL_16BIT |\
  62         HRCWH_RL_EXT_LEGACY |\
  63         HRCWH_TSEC1M_IN_RGMII |\
  64         HRCWH_TSEC2M_IN_RGMII |\
  65         HRCWH_BIG_ENDIAN |\
  66         HRCWH_LALE_NORMAL)
  67
  68 /*
  69  * System IO Config
  70  */
  71 #define CONFIG_SYS_SICRH                0x00000000
  72 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  73
  74 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  75
  76 /*
  77  * IMMR new address
  78  */
  79 #define CONFIG_SYS_IMMR         0xE0000000
  80
  81 /*
  82  * Arbiter Setup
  83  */
  84 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  85 #define CONFIG_SYS_ACR_RPTCNT           3 /* Arbiter repeat count is 4 */
  86 #define CONFIG_SYS_SPCR_TSECEP          3 /* eTSEC emergency priority is highest */
  87
  88 /*
  89  * DDR Setup
  90  */
  91 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  92 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  93 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  94 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  95 #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
  96                                 | DDRCDR_PZ_LOZ \
  97                                 | DDRCDR_NZ_LOZ \
  98                                 | DDRCDR_ODT \
  99                                 | DDRCDR_Q_DRN )
 100                                 /* 0x7b880001 */
 101 /*
 102  * Manually set up DDR parameters
 103  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 104  */
 105 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 106 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 107 #define CONFIG_SYS_DDR_CS0_CONFIG       ( CSCONFIG_EN \
 108                                 | 0x00010000  /* ODT_WR to CSn */ \
 109                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
 110                                 /* 0x80010102 */
 111 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 112 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 113                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 114                                 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 115                                 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
 116                                 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
 117                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
 118                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 119                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 120                                 /* 0x00220802 */
 121 #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
 122                                 | ( 7 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 123                                 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
 124                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
 125                                 | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
 126                                 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
 127                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 128                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 129                                 /* 0x27256222 */
 130 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 131                                 | ( 4 << TIMING_CFG2_CPO_SHIFT ) \
 132                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 133                                 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 134                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 135                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 136                                 | ( 5 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 137                                 /* 0x121048c5 */
 138 #define CONFIG_SYS_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 139                                 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 140                                 /* 0x03600100 */
 141 #define CONFIG_SYS_DDR_SDRAM_CFG        ( SDRAM_CFG_SREN \
 142                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 143                                 | SDRAM_CFG_32_BE )
 144                                 /* 0x43080000 */
 145 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 146 #define CONFIG_SYS_DDR_MODE             ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
 147                                 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
 148                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 149 #define CONFIG_SYS_DDR_MODE2            0x00000000
 150
 151 /*
 152  * Memory test
 153  */
 154 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 155 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 156 #define CONFIG_SYS_MEMTEST_END          0x00140000
 157
 158 /*
 159  * The reserved memory
 160  */
 161 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 162
 163 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 164 #define CONFIG_SYS_RAMBOOT
 165 #else
 166 #undef CONFIG_SYS_RAMBOOT
 167 #endif
 168
 169 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kB for Mon */
 170 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024) /* Reserved for malloc */
 171
 172 /*
 173  * Initial RAM Base Address Setup
 174  */
 175 #define CONFIG_SYS_INIT_RAM_LOCK        1
 176 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 177 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 178 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 179 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 180
 181 /*
 182  * Local Bus Configuration & Clock Setup
 183  */
 184 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_CLKDIV_2)
 185 #define CONFIG_SYS_LBC_LBCR             0x00040000
 186
 187 /*
 188  * FLASH on the Local Bus
 189  */
 190 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 191 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 192 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 193
 194 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 195 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is 8M */
 196 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 197
 198 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 199 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016 /* 8MB window size */
 200
 201 #define CONFIG_SYS_BR0_PRELIM           ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
 202                                 | (2 << BR_PS_SHIFT)    /* 16 bit port size */ \
 203                                 | BR_V )                /* valid */
 204 #define CONFIG_SYS_OR0_PRELIM           ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 205                                 | OR_UPM_XAM \
 206                                 | OR_GPCM_CSNT \
 207                                 | OR_GPCM_ACS_DIV2 \
 208                                 | OR_GPCM_XACS \
 209                                 | OR_GPCM_SCY_15 \
 210                                 | OR_GPCM_TRLX \
 211                                 | OR_GPCM_EHTR \
 212                                 | OR_GPCM_EAD )
 213
 214 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 215 #define CONFIG_SYS_MAX_FLASH_SECT       135 /* 127 64KB sectors and 8 8KB top sectors per device */
 216
 217 #undef CONFIG_SYS_FLASH_CHECKSUM
 218 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 219 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 220
 221 /*
 222  * NAND Flash on the Local Bus
 223  */
 224 #define CONFIG_SYS_NAND_BASE            0xE0600000      /* 0xE0600000 */
 225 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 226 #define CONFIG_MTD_NAND_VERIFY_WRITE    1
 227 #define CONFIG_CMD_NAND                 1
 228 #define CONFIG_NAND_FSL_ELBC            1
 229
 230 #define CONFIG_SYS_BR1_PRELIM   ( CONFIG_SYS_NAND_BASE \
 231                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 232                                 | BR_PS_8               /* Port Size = 8 bit */ \
 233                                 | BR_MS_FCM             /* MSEL = FCM */ \
 234                                 | BR_V )                /* valid */
 235 #define CONFIG_SYS_OR1_PRELIM   ( 0xFFFF8000            /* length 32K */ \
 236                                 | OR_FCM_CSCT \
 237                                 | OR_FCM_CST \
 238                                 | OR_FCM_CHT \
 239                                 | OR_FCM_SCY_1 \
 240                                 | OR_FCM_TRLX \
 241                                 | OR_FCM_EHTR )
 242                                 /* 0xFFFF8396 */
 243
 244 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 245 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E      /* 32KB  */
 246
 247 /*
 248  * Serial Port
 249  */
 250 #define CONFIG_CONS_INDEX       1
 251 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 252 #define CONFIG_SYS_NS16550
 253 #define CONFIG_SYS_NS16550_SERIAL
 254 #define CONFIG_SYS_NS16550_REG_SIZE     1
 255 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 256
 257 #define CONFIG_SYS_BAUDRATE_TABLE  \
 258         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 259
 260 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 261 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 262
 263 /* Use the HUSH parser */
 264 #define CONFIG_SYS_HUSH_PARSER
 265 #ifdef CONFIG_SYS_HUSH_PARSER
 266 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 267 #endif
 268
 269 /* Pass open firmware flat tree */
 270 #define CONFIG_OF_LIBFDT        1
 271 #define CONFIG_OF_BOARD_SETUP   1
 272 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 273
 274 /* I2C */
 275 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 276 #define CONFIG_FSL_I2C
 277 #define CONFIG_SYS_I2C_SPEED            400000 /* I2C speed and slave address */
 278 #define CONFIG_SYS_I2C_SLAVE            0x7F
 279 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
 280 #define CONFIG_SYS_I2C_OFFSET           0x3000
 281 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 282
 283 /*
 284  * Board info - revision and where boot from
 285  */
 286 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 287
 288 /*
 289  * Config on-board RTC
 290  */
 291 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 292 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 293
 294 /*
 295  * General PCI
 296  * Addresses are mapped 1-1.
 297  */
 298 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
 299 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 300 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
 301 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 302 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 303 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 304 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 305 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 306 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 307
 308 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 309 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 310 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 311
 312 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 313 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 314 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 315 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 316 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 317 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 318 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 319 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 320 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 321
 322 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 323 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 324 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 325 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 326 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 327 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 328 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 329 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 330 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 331
 332 #define CONFIG_PCI
 333 #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
 334 #define CONFIG_83XX_GENERIC_PCIE        1
 335
 336 #define CONFIG_NET_MULTI
 337 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 338
 339 #define CONFIG_EEPRO100
 340 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 341 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 342
 343 #ifndef CONFIG_NET_MULTI
 344 #define CONFIG_NET_MULTI        1
 345 #endif
 346
 347 #define CONFIG_HAS_FSL_DR_USB
 348 #define CONFIG_SYS_SCCR_USBDRCM         3
 349
 350 #define CONFIG_CMD_USB
 351 #define CONFIG_USB_STORAGE
 352 #define CONFIG_USB_EHCI
 353 #define CONFIG_USB_EHCI_FSL
 354 #define CONFIG_USB_PHY_TYPE     "utmi"
 355 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 356
 357 /*
 358  * TSEC
 359  */
 360 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 361 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 362 #define CONFIG_SYS_TSEC1                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 363 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 364 #define CONFIG_SYS_TSEC2                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 365
 366 /*
 367  * TSEC ethernet configuration
 368  */
 369 #define CONFIG_MII              1 /* MII PHY management */
 370 #define CONFIG_TSEC1            1
 371 #define CONFIG_TSEC1_NAME       "eTSEC0"
 372 #define CONFIG_TSEC2            1
 373 #define CONFIG_TSEC2_NAME       "eTSEC1"
 374 #define TSEC1_PHY_ADDR          0
 375 #define TSEC2_PHY_ADDR          1
 376 #define TSEC1_PHYIDX            0
 377 #define TSEC2_PHYIDX            0
 378 #define TSEC1_FLAGS             TSEC_GIGABIT
 379 #define TSEC2_FLAGS             TSEC_GIGABIT
 380
 381 /* Options are: eTSEC[0-1] */
 382 #define CONFIG_ETHPRIME         "eTSEC1"
 383
 384 /*
 385  * SATA
 386  */
 387 #define CONFIG_LIBATA
 388 #define CONFIG_FSL_SATA
 389
 390 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 391 #define CONFIG_SATA1
 392 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 393 #define CONFIG_SYS_SATA1                (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 394 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 395 #define CONFIG_SATA2
 396 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 397 #define CONFIG_SYS_SATA2                (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 398 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 399
 400 #ifdef CONFIG_FSL_SATA
 401 #define CONFIG_LBA48
 402 #define CONFIG_CMD_SATA
 403 #define CONFIG_DOS_PARTITION
 404 #define CONFIG_CMD_EXT2
 405 #endif
 406
 407 /*
 408  * Environment
 409  */
 410 #ifndef CONFIG_SYS_RAMBOOT
 411         #define CONFIG_ENV_IS_IN_FLASH  1
 412         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 413         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 414         #define CONFIG_ENV_SIZE         0x2000
 415 #else
 416         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 417         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 418         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 419         #define CONFIG_ENV_SIZE         0x2000
 420 #endif
 421
 422 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 423 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 424
 425 /*
 426  * BOOTP options
 427  */
 428 #define CONFIG_BOOTP_BOOTFILESIZE
 429 #define CONFIG_BOOTP_BOOTPATH
 430 #define CONFIG_BOOTP_GATEWAY
 431 #define CONFIG_BOOTP_HOSTNAME
 432
 433 /*
 434  * Command line configuration.
 435  */
 436 #include <config_cmd_default.h>
 437
 438 #define CONFIG_CMD_PING
 439 #define CONFIG_CMD_I2C
 440 #define CONFIG_CMD_MII
 441 #define CONFIG_CMD_DATE
 442 #define CONFIG_CMD_PCI
 443
 444 #if defined(CONFIG_SYS_RAMBOOT)
 445     #undef CONFIG_CMD_SAVEENV
 446     #undef CONFIG_CMD_LOADS
 447 #endif
 448
 449 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 450
 451 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 452
 453 /*
 454  * Miscellaneous configurable options
 455  */
 456 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 457 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 458 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 459
 460 #if defined(CONFIG_CMD_KGDB)
 461         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 462 #else
 463         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 464 #endif
 465
 466 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 467 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 468 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 469 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 470
 471 /*
 472  * For booting Linux, the board info and command line data
 473  * have to be in the first 8 MB of memory, since this is
 474  * the maximum mapped by the Linux kernel during initialization.
 475  */
 476 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 477
 478 /*
 479  * Core HID Setup
 480  */
 481 #define CONFIG_SYS_HID0_INIT            0x000000000
 482 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 483                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 484 #define CONFIG_SYS_HID2         HID2_HBE
 485
 486 /*
 487  * MMU Setup
 488  */
 489 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 490
 491 /* DDR: cache cacheable */
 492 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 493 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 494 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 495 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 496
 497 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 498 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 499                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 500 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
 501 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 502 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 503
 504 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 505 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 506 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
 507 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 508                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 509 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 510
 511 /* Stack in dcache: cacheable, no memory coherence */
 512 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 513 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 514 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 515 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 516
 517 /* PCI MEM space: cacheable */
 518 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 519 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 520 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 521 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 522
 523 /* PCI MMIO space: cache-inhibit and guarded */
 524 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
 525                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 526 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 527 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 528 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 529
 530 #define CONFIG_SYS_IBAT6L       0
 531 #define CONFIG_SYS_IBAT6U       0
 532 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 533 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 534
 535 #define CONFIG_SYS_IBAT7L       0
 536 #define CONFIG_SYS_IBAT7U       0
 537 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 538 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 539
 540 /*
 541  * Internal Definitions
 542  *
 543  * Boot Flags
 544  */
 545 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 546 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 547
 548 #if defined(CONFIG_CMD_KGDB)
 549 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 550 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 551 #endif
 552
 553 /*
 554  * Environment Configuration
 555  */
 556
 557 #define CONFIG_ENV_OVERWRITE
 558
 559 #if defined(CONFIG_TSEC_ENET)
 560 #define CONFIG_HAS_ETH0
 561 #define CONFIG_ETHADDR          04:00:00:00:00:0A
 562 #define CONFIG_HAS_ETH1
 563 #define CONFIG_ETH1ADDR         04:00:00:00:00:0B
 564 #endif
 565
 566 #define CONFIG_BAUDRATE 115200
 567
 568 #define CONFIG_LOADADDR 500000  /* default location for tftp and bootm */
 569
 570 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 571 #undef CONFIG_BOOTARGS          /* the boot command will set bootargs */
 572
 573 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 574    "netdev=eth0\0"                                                      \
 575    "consoledev=ttyS0\0"                                                 \
 576    "ramdiskaddr=1000000\0"                                              \
 577    "ramdiskfile=ramfs.83xx\0"                                           \
 578    "fdtaddr=400000\0"                                                   \
 579    "fdtfile=mpc8315erdb.dtb\0"                                          \
 580    "usb_phy_type=utmi\0"                                                \
 581    ""
 582
 583 #define CONFIG_NFSBOOTCOMMAND                                           \
 584    "setenv bootargs root=/dev/nfs rw "                                  \
 585       "nfsroot=$serverip:$rootpath "                                    \
 586       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 587       "console=$consoledev,$baudrate $othbootargs;"                     \
 588    "tftp $loadaddr $bootfile;"                                          \
 589    "tftp $fdtaddr $fdtfile;"                                            \
 590    "bootm $loadaddr - $fdtaddr"
 591
 592 #define CONFIG_RAMBOOTCOMMAND                                           \
 593    "setenv bootargs root=/dev/ram rw "                                  \
 594       "console=$consoledev,$baudrate $othbootargs;"                     \
 595    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 596    "tftp $loadaddr $bootfile;"                                          \
 597    "tftp $fdtaddr $fdtfile;"                                            \
 598    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 599
 600
 601 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 602
 603 #endif  /* __CONFIG_H */