1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
6 * mpc8313epb board configuration file
13 * High Level Configuration Options
17 #define CONFIG_SPL_INIT_MINIMAL
18 #define CONFIG_SPL_FLUSH_IMAGE
19 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
20 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
22 #ifdef CONFIG_SPL_BUILD
23 #define CONFIG_NS16550_MIN_FUNCTIONS
26 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
27 #define CONFIG_SPL_MAX_SIZE (4 * 1024)
28 #define CONFIG_SPL_PAD_TO 0x4000
30 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
31 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
32 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
33 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
34 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
35 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
37 #ifdef CONFIG_SPL_BUILD
38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
41 #ifndef CONFIG_SYS_MONITOR_BASE
42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
45 #define CONFIG_PCI_INDIRECT_BRIDGE
46 #define CONFIG_FSL_ELBC 1
54 #define CONFIG_VSC7385_ENET
57 #define CONFIG_SYS_IMMR 0xE0000000
59 #if !defined(CONFIG_SPL_BUILD)
60 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
63 #define CONFIG_SYS_MEMTEST_START 0x00001000
64 #define CONFIG_SYS_MEMTEST_END 0x07f00000
66 /* Early revs of this board will lock up hard when attempting
67 * to access the PMC registers, unless a JTAG debugger is
68 * connected, or some resistor modifications are made.
70 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
72 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
73 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
76 * Device configurations
81 #ifdef CONFIG_VSC7385_ENET
85 /* The flash address and size of the VSC7385 firmware image */
86 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
87 #define CONFIG_VSC7385_IMAGE_SIZE 8192
94 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
95 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
96 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
99 * Manually set up DDR parameters, as this board does not
100 * seem to have the SPD connected to I2C.
102 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
103 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
104 | CSCONFIG_ODT_RD_NEVER \
105 | CSCONFIG_ODT_WR_ONLY_CURRENT \
106 | CSCONFIG_ROW_BIT_13 \
107 | CSCONFIG_COL_BIT_10)
110 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
111 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
112 | (0 << TIMING_CFG0_WRT_SHIFT) \
113 | (0 << TIMING_CFG0_RRT_SHIFT) \
114 | (0 << TIMING_CFG0_WWT_SHIFT) \
115 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
116 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
117 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
118 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
120 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
121 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
122 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
123 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
124 | (10 << TIMING_CFG1_REFREC_SHIFT) \
125 | (3 << TIMING_CFG1_WRREC_SHIFT) \
126 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
127 | (2 << TIMING_CFG1_WRTORD_SHIFT))
129 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
130 | (5 << TIMING_CFG2_CPO_SHIFT) \
131 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
132 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
133 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
134 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
135 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
136 /* 0x129048c6 */ /* P9-45,may need tuning */
137 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
138 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
140 #if defined(CONFIG_DDR_2T_TIMING)
141 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
142 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
147 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
148 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
152 #define CONFIG_SYS_SDRAM_CFG2 0x00401000
153 /* set burst length to 8 for 32-bit data path */
154 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
155 | (0x0632 << SDRAM_MODE_SD_SHIFT))
157 #define CONFIG_SYS_DDR_MODE_2 0x8000C000
159 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
161 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
167 * FLASH on the Local Bus
169 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
170 #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
171 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
173 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
174 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
176 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
177 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
179 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
180 !defined(CONFIG_SPL_BUILD)
181 #define CONFIG_SYS_RAMBOOT
184 #define CONFIG_SYS_INIT_RAM_LOCK 1
185 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
186 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
188 #define CONFIG_SYS_GBL_DATA_OFFSET \
189 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
190 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
192 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
193 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
194 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
197 * Local Bus LCRR and LBCR regs
199 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
200 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
201 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
202 | (0xFF << LBCR_BMT_SHIFT) \
203 | 0xF) /* 0x0004ff0f */
205 /* LB refresh timer prescal, 266MHz/32 */
206 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
208 /* drivers/mtd/nand/raw/nand.c */
209 #if defined(CONFIG_SPL_BUILD)
210 #define CONFIG_SYS_NAND_BASE 0xFFF00000
212 #define CONFIG_SYS_NAND_BASE 0xE2800000
215 #define CONFIG_MTD_PARTITION
217 #define CONFIG_SYS_MAX_NAND_DEVICE 1
218 #define CONFIG_NAND_FSL_ELBC 1
219 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
220 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
223 #define CONFIG_SYS_BR0_PRELIM (0xE2800000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
224 #define CONFIG_SYS_OR0_PRELIM (OR_AM_32KB | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_TRLX | OR_FCM_EHTR)
227 #define CONFIG_SYS_BR1_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
228 #define CONFIG_SYS_OR1_PRELIM (OR_AM_8MB | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
230 /* Still needed for spl_minimal.c */
231 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
232 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
234 /* local bus write LED / read status buffer (BCSR) mapping */
235 #define CONFIG_SYS_BCSR_ADDR 0xFA000000
236 #define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
237 /* map at 0xFA000000 on LCS3 */
239 #define CONFIG_SYS_BR3_PRELIM (0xFA000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
240 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
244 #ifdef CONFIG_VSC7385_ENET
246 /* VSC7385 Base address on LCS2 */
247 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
248 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
251 #define CONFIG_SYS_BR2_PRELIM (0xF0000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
252 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
256 #define CONFIG_MPC83XX_GPIO 1
261 #define CONFIG_SYS_NS16550_SERIAL
262 #define CONFIG_SYS_NS16550_REG_SIZE 1
264 #define CONFIG_SYS_BAUDRATE_TABLE \
265 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
267 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
268 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
271 #define CONFIG_SYS_I2C
272 #define CONFIG_SYS_I2C_FSL
273 #define CONFIG_SYS_FSL_I2C_SPEED 400000
274 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
275 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
276 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
277 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
278 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
279 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
283 * Addresses are mapped 1-1.
285 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
286 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
287 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
288 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
289 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
290 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
291 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
292 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
293 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
295 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
301 #define CONFIG_GMII /* MII PHY management */
304 #define CONFIG_HAS_ETH0
305 #define CONFIG_TSEC1_NAME "TSEC0"
306 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
307 #define TSEC1_PHY_ADDR 0x1c
308 #define TSEC1_FLAGS TSEC_GIGABIT
309 #define TSEC1_PHYIDX 0
313 #define CONFIG_HAS_ETH1
314 #define CONFIG_TSEC2_NAME "TSEC1"
315 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
316 #define TSEC2_PHY_ADDR 4
317 #define TSEC2_FLAGS TSEC_GIGABIT
318 #define TSEC2_PHYIDX 0
321 /* Options are: TSEC[0-1] */
322 #define CONFIG_ETHPRIME "TSEC1"
325 * Configure on-board RTC
327 #define CONFIG_RTC_DS1337
328 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
333 #define CONFIG_ENV_OFFSET (512 * 1024)
334 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
335 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
336 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
337 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
338 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
340 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
341 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
346 #define CONFIG_BOOTP_BOOTFILESIZE
349 * Command line configuration.
353 * Miscellaneous configurable options
355 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
356 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
358 /* Boot Argument Buffer Size */
359 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
362 * For booting Linux, the board info and command line data
363 * have to be in the first 256 MB of memory, since this is
364 * the maximum mapped by the Linux kernel during initialization.
366 /* Initial Memory map for Linux*/
367 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
368 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
370 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
372 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
374 /* System IO Config */
375 #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
376 /* Enable Internal USB Phy and GPIO on LCD Connector */
377 #define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
379 #define CONFIG_SYS_HID0_INIT 0x000000000
380 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
381 HID0_ENABLE_INSTRUCTION_CACHE | \
382 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
384 #define CONFIG_SYS_HID2 HID2_HBE
387 * Environment Configuration
389 #define CONFIG_ENV_OVERWRITE
391 #define CONFIG_NETDEV "eth1"
393 #define CONFIG_HOSTNAME "mpc8313erdb"
394 #define CONFIG_ROOTPATH "/nfs/root/path"
395 #define CONFIG_BOOTFILE "uImage"
396 /* U-Boot image on TFTP server */
397 #define CONFIG_UBOOTPATH "u-boot.bin"
398 #define CONFIG_FDTFILE "mpc8313erdb.dtb"
400 /* default location for tftp and bootm */
401 #define CONFIG_LOADADDR 800000
403 #define CONFIG_EXTRA_ENV_SETTINGS \
404 "netdev=" CONFIG_NETDEV "\0" \
406 "uboot=" CONFIG_UBOOTPATH "\0" \
407 "tftpflash=tftpboot $loadaddr $uboot; " \
408 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
410 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
412 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
414 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
416 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
419 "fdtfile=" CONFIG_FDTFILE "\0" \
421 "setbootargs=setenv bootargs " \
422 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
423 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
424 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
426 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
428 #define CONFIG_NFSBOOTCOMMAND \
429 "setenv rootdev /dev/nfs;" \
432 "tftp $loadaddr $bootfile;" \
433 "tftp $fdtaddr $fdtfile;" \
434 "bootm $loadaddr - $fdtaddr"
436 #define CONFIG_RAMBOOTCOMMAND \
437 "setenv rootdev /dev/ram;" \
439 "tftp $ramdiskaddr $ramdiskfile;" \
440 "tftp $loadaddr $bootfile;" \
441 "tftp $fdtaddr $fdtfile;" \
442 "bootm $loadaddr $ramdiskaddr $fdtaddr"
444 #endif /* __CONFIG_H */