include/configs/MPC8313ERDB_NAND.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
   4  */
   5 /*
   6  * mpc8313epb board configuration file
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1
  16
  17 #define CONFIG_SPL_INIT_MINIMAL
  18 #define CONFIG_SPL_FLUSH_IMAGE
  19 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  20 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
  21
  22 #ifdef CONFIG_SPL_BUILD
  23 #define CONFIG_NS16550_MIN_FUNCTIONS
  24 #endif
  25
  26 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  27 #define CONFIG_SPL_MAX_SIZE     (4 * 1024)
  28 #define CONFIG_SPL_PAD_TO       0x4000
  29
  30 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  31 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  32 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  33 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  34 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  35 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  36
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  39 #endif
  40
  41 #ifndef CONFIG_SYS_MONITOR_BASE
  42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  43 #endif
  44
  45 #define CONFIG_PCI_INDIRECT_BRIDGE
  46 #define CONFIG_FSL_ELBC 1
  47
  48 /*
  49  * On-board devices
  50  *
  51  * TSEC1 is VSC switch
  52  * TSEC2 is SoC TSEC
  53  */
  54 #define CONFIG_VSC7385_ENET
  55 #define CONFIG_TSEC2
  56
  57 #define CONFIG_SYS_IMMR         0xE0000000
  58
  59 #if !defined(CONFIG_SPL_BUILD)
  60 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
  61 #endif
  62
  63 #define CONFIG_SYS_MEMTEST_START        0x00001000
  64 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  65
  66 /* Early revs of this board will lock up hard when attempting
  67  * to access the PMC registers, unless a JTAG debugger is
  68  * connected, or some resistor modifications are made.
  69  */
  70 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
  71
  72 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  73 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  74
  75 /*
  76  * Device configurations
  77  */
  78
  79 /* Vitesse 7385 */
  80
  81 #ifdef CONFIG_VSC7385_ENET
  82
  83 #define CONFIG_TSEC1
  84
  85 /* The flash address and size of the VSC7385 firmware image */
  86 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  87 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  88
  89 #endif
  90
  91 /*
  92  * DDR Setup
  93  */
  94 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  95 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  97
  98 /*
  99  * Manually set up DDR parameters, as this board does not
 100  * seem to have the SPD connected to I2C.
 101  */
 102 #define CONFIG_SYS_DDR_SIZE     128             /* MB */
 103 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 104                                 | CSCONFIG_ODT_RD_NEVER \
 105                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 106                                 | CSCONFIG_ROW_BIT_13 \
 107                                 | CSCONFIG_COL_BIT_10)
 108                                 /* 0x80010102 */
 109
 110 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 111 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 112                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 113                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 114                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 115                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 116                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 117                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 118                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 119                                 /* 0x00220802 */
 120 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 121                                 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 122                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 123                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 124                                 | (10 << TIMING_CFG1_REFREC_SHIFT) \
 125                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 126                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 127                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 128                                 /* 0x3835a322 */
 129 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 130                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 131                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 132                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 133                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 134                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 135                                 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
 136                                 /* 0x129048c6 */ /* P9-45,may need tuning */
 137 #define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
 138                                 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 139                                 /* 0x05100500 */
 140 #if defined(CONFIG_DDR_2T_TIMING)
 141 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 142                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 143                                 | SDRAM_CFG_DBW_32 \
 144                                 | SDRAM_CFG_2T_EN)
 145                                 /* 0x43088000 */
 146 #else
 147 #define CONFIG_SYS_SDRAM_CFG    (SDRAM_CFG_SREN \
 148                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 149                                 | SDRAM_CFG_DBW_32)
 150                                 /* 0x43080000 */
 151 #endif
 152 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
 153 /* set burst length to 8 for 32-bit data path */
 154 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 155                                 | (0x0632 << SDRAM_MODE_SD_SHIFT))
 156                                 /* 0x44480632 */
 157 #define CONFIG_SYS_DDR_MODE_2   0x8000C000
 158
 159 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 160                                 /*0x02000000*/
 161 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 162                                 | DDRCDR_PZ_NOMZ \
 163                                 | DDRCDR_NZ_NOMZ \
 164                                 | DDRCDR_M_ODR)
 165
 166 /*
 167  * FLASH on the Local Bus
 168  */
 169 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 170 #define CONFIG_SYS_FLASH_SIZE           8       /* flash size in MB */
 171 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 172
 173 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 174 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* sectors per device */
 175
 176 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 177 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 178
 179 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
 180         !defined(CONFIG_SPL_BUILD)
 181 #define CONFIG_SYS_RAMBOOT
 182 #endif
 183
 184 #define CONFIG_SYS_INIT_RAM_LOCK        1
 185 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 186 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 187
 188 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 189                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 190 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 191
 192 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 193 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 194 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)    /* Reserved for malloc */
 195
 196 /*
 197  * Local Bus LCRR and LBCR regs
 198  */
 199 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 200 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 201 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 202                                 | (0xFF << LBCR_BMT_SHIFT) \
 203                                 | 0xF)  /* 0x0004ff0f */
 204
 205                                 /* LB refresh timer prescal, 266MHz/32 */
 206 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */
 207
 208 /* drivers/mtd/nand/raw/nand.c */
 209 #if defined(CONFIG_SPL_BUILD)
 210 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 211 #else
 212 #define CONFIG_SYS_NAND_BASE            0xE2800000
 213 #endif
 214
 215 #define CONFIG_MTD_PARTITION
 216
 217 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 218 #define CONFIG_NAND_FSL_ELBC 1
 219 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
 220 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
 221
 222 /* Still needed for spl_minimal.c */
 223 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
 224 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
 225
 226 /* local bus write LED / read status buffer (BCSR) mapping */
 227 #define CONFIG_SYS_BCSR_ADDR            0xFA000000
 228 #define CONFIG_SYS_BCSR_SIZE            (32 * 1024)     /* 0x00008000 */
 229                                         /* map at 0xFA000000 on LCS3 */
 230
 231 /* Vitesse 7385 */
 232
 233 #ifdef CONFIG_VSC7385_ENET
 234
 235                                         /* VSC7385 Base address on LCS2 */
 236 #define CONFIG_SYS_VSC7385_BASE         0xF0000000
 237 #define CONFIG_SYS_VSC7385_SIZE         (128 * 1024)    /* 0x00020000 */
 238
 239
 240 #endif
 241
 242 #define CONFIG_MPC83XX_GPIO 1
 243
 244 /*
 245  * Serial Port
 246  */
 247 #define CONFIG_SYS_NS16550_SERIAL
 248 #define CONFIG_SYS_NS16550_REG_SIZE     1
 249
 250 #define CONFIG_SYS_BAUDRATE_TABLE       \
 251         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 252
 253 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 254 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 255
 256 /* I2C */
 257 #define CONFIG_SYS_I2C
 258 #define CONFIG_SYS_I2C_FSL
 259 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 260 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 261 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 262 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 263 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 264 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 265 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 266
 267 /*
 268  * General PCI
 269  * Addresses are mapped 1-1.
 270  */
 271 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 272 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 273 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 274 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 275 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 276 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 277 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 278 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 279 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 280
 281 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 282
 283 /*
 284  * TSEC
 285  */
 286
 287 #define CONFIG_GMII                     /* MII PHY management */
 288
 289 #ifdef CONFIG_TSEC1
 290 #define CONFIG_HAS_ETH0
 291 #define CONFIG_TSEC1_NAME       "TSEC0"
 292 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 293 #define TSEC1_PHY_ADDR          0x1c
 294 #define TSEC1_FLAGS             TSEC_GIGABIT
 295 #define TSEC1_PHYIDX            0
 296 #endif
 297
 298 #ifdef CONFIG_TSEC2
 299 #define CONFIG_HAS_ETH1
 300 #define CONFIG_TSEC2_NAME       "TSEC1"
 301 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 302 #define TSEC2_PHY_ADDR          4
 303 #define TSEC2_FLAGS             TSEC_GIGABIT
 304 #define TSEC2_PHYIDX            0
 305 #endif
 306
 307 /* Options are: TSEC[0-1] */
 308 #define CONFIG_ETHPRIME                 "TSEC1"
 309
 310 /*
 311  * Configure on-board RTC
 312  */
 313 #define CONFIG_RTC_DS1337
 314 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 315
 316 /*
 317  * Environment
 318  */
 319 #define CONFIG_ENV_OFFSET               (512 * 1024)
 320 #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
 321 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 322 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 323 #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 324 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 325
 326 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 327 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 328
 329 /*
 330  * BOOTP options
 331  */
 332 #define CONFIG_BOOTP_BOOTFILESIZE
 333
 334 /*
 335  * Command line configuration.
 336  */
 337
 338 /*
 339  * Miscellaneous configurable options
 340  */
 341 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 342 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 343
 344                                 /* Boot Argument Buffer Size */
 345 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 346
 347 /*
 348  * For booting Linux, the board info and command line data
 349  * have to be in the first 256 MB of memory, since this is
 350  * the maximum mapped by the Linux kernel during initialization.
 351  */
 352                                 /* Initial Memory map for Linux*/
 353 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 354 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 355
 356 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
 357
 358 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
 359
 360 /* System IO Config */
 361 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
 362                         /* Enable Internal USB Phy and GPIO on LCD Connector */
 363 #define CONFIG_SYS_SICRL        (SICRL_USBDR_10 | SICRL_LBC)
 364
 365 /*
 366  * Environment Configuration
 367  */
 368 #define CONFIG_ENV_OVERWRITE
 369
 370 #define CONFIG_NETDEV           "eth1"
 371
 372 #define CONFIG_HOSTNAME         "mpc8313erdb"
 373 #define CONFIG_ROOTPATH         "/nfs/root/path"
 374 #define CONFIG_BOOTFILE         "uImage"
 375                                 /* U-Boot image on TFTP server */
 376 #define CONFIG_UBOOTPATH        "u-boot.bin"
 377 #define CONFIG_FDTFILE          "mpc8313erdb.dtb"
 378
 379                                 /* default location for tftp and bootm */
 380 #define CONFIG_LOADADDR         800000
 381
 382 #define CONFIG_EXTRA_ENV_SETTINGS \
 383         "netdev=" CONFIG_NETDEV "\0"                                    \
 384         "ethprime=TSEC1\0"                                              \
 385         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 386         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 387                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 388                         " +$filesize; " \
 389                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 390                         " +$filesize; " \
 391                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 392                         " $filesize; "  \
 393                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 394                         " +$filesize; " \
 395                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 396                         " $filesize\0"  \
 397         "fdtaddr=780000\0"                                              \
 398         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 399         "console=ttyS0\0"                                               \
 400         "setbootargs=setenv bootargs "                                  \
 401                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 402         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 403                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 404                                                         "$netdev:off " \
 405                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 406
 407 #define CONFIG_NFSBOOTCOMMAND                                           \
 408         "setenv rootdev /dev/nfs;"                                      \
 409         "run setbootargs;"                                              \
 410         "run setipargs;"                                                \
 411         "tftp $loadaddr $bootfile;"                                     \
 412         "tftp $fdtaddr $fdtfile;"                                       \
 413         "bootm $loadaddr - $fdtaddr"
 414
 415 #define CONFIG_RAMBOOTCOMMAND                                           \
 416         "setenv rootdev /dev/ram;"                                      \
 417         "run setbootargs;"                                              \
 418         "tftp $ramdiskaddr $ramdiskfile;"                               \
 419         "tftp $loadaddr $bootfile;"                                     \
 420         "tftp $fdtaddr $fdtfile;"                                       \
 421         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 422
 423 #endif  /* __CONFIG_H */