ARMV7: AM3517/05: Add support for CraneBoard.
[oweals/u-boot.git] / include / configs / MPC8313ERDB.h
1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 /*
23  * mpc8313epb board configuration file
24  */
25
26 #ifndef __CONFIG_H
27 #define __CONFIG_H
28
29 /*
30  * High Level Configuration Options
31  */
32 #define CONFIG_E300             1
33 #define CONFIG_MPC83xx          1
34 #define CONFIG_MPC831x          1
35 #define CONFIG_MPC8313          1
36 #define CONFIG_MPC8313ERDB      1
37
38 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
39 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
40 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
41 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
42 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
43 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
44
45 #ifdef CONFIG_NAND_U_BOOT
46 #define CONFIG_SYS_TEXT_BASE    0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
47 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
48 #ifdef CONFIG_NAND_SPL
49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
50 #endif /* CONFIG_NAND_SPL */
51 #endif /* CONFIG_NAND_U_BOOT */
52
53 #ifndef CONFIG_SYS_TEXT_BASE
54 #define CONFIG_SYS_TEXT_BASE    0xFE000000
55 #endif
56
57 #ifndef CONFIG_SYS_MONITOR_BASE
58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
59 #endif
60
61 #define CONFIG_PCI
62 #define CONFIG_FSL_ELBC 1
63
64 #define CONFIG_MISC_INIT_R
65
66 /*
67  * On-board devices
68  *
69  * TSEC1 is VSC switch
70  * TSEC2 is SoC TSEC
71  */
72 #define CONFIG_VSC7385_ENET
73 #define CONFIG_TSEC2
74
75 #ifdef CONFIG_SYS_66MHZ
76 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
77 #elif defined(CONFIG_SYS_33MHZ)
78 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
79 #else
80 #error Unknown oscillator frequency.
81 #endif
82
83 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
84
85 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
86
87 #define CONFIG_SYS_IMMR         0xE0000000
88
89 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
90 #define CONFIG_DEFAULT_IMMR     CONFIG_SYS_IMMR
91 #endif
92
93 #define CONFIG_SYS_MEMTEST_START        0x00001000
94 #define CONFIG_SYS_MEMTEST_END          0x07f00000
95
96 /* Early revs of this board will lock up hard when attempting
97  * to access the PMC registers, unless a JTAG debugger is
98  * connected, or some resistor modifications are made.
99  */
100 #define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
101
102 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
103 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
104
105 /*
106  * Device configurations
107  */
108
109 /* Vitesse 7385 */
110
111 #ifdef CONFIG_VSC7385_ENET
112
113 #define CONFIG_TSEC1
114
115 /* The flash address and size of the VSC7385 firmware image */
116 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
117 #define CONFIG_VSC7385_IMAGE_SIZE       8192
118
119 #endif
120
121 /*
122  * DDR Setup
123  */
124 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
125 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
126 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
127
128 /*
129  * Manually set up DDR parameters, as this board does not
130  * seem to have the SPD connected to I2C.
131  */
132 #define CONFIG_SYS_DDR_SIZE             128             /* MB */
133 #define CONFIG_SYS_DDR_CONFIG           ( CSCONFIG_EN \
134                                 | 0x00010000 /* TODO */ \
135                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
136                                 /* 0x80010102 */
137
138 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
139 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
140                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
141                                 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
142                                 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
143                                 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
144                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
145                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
146                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
147                                 /* 0x00220802 */
148 #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
149                                 | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
150                                 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
151                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
152                                 | (10 << TIMING_CFG1_REFREC_SHIFT ) \
153                                 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
154                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
155                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
156                                 /* 0x3835a322 */
157 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
158                                 | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
159                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
160                                 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
161                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
162                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
163                                 | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
164                                 /* 0x129048c6 */ /* P9-45,may need tuning */
165 #define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
166                                 | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
167                                 /* 0x05100500 */
168 #if defined(CONFIG_DDR_2T_TIMING)
169 #define CONFIG_SYS_SDRAM_CFG            ( SDRAM_CFG_SREN \
170                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
171                                 | SDRAM_CFG_2T_EN \
172                                 | SDRAM_CFG_DBW_32 )
173 #else
174 #define CONFIG_SYS_SDRAM_CFG            ( SDRAM_CFG_SREN \
175                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
176                                 | SDRAM_CFG_32_BE )
177                                 /* 0x43080000 */
178 #endif
179 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
180 /* set burst length to 8 for 32-bit data path */
181 #define CONFIG_SYS_DDR_MODE             ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
182                                 | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
183                                 /* 0x44480632 */
184 #define CONFIG_SYS_DDR_MODE_2           0x8000C000
185
186 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
187                                 /*0x02000000*/
188 #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
189                                 | DDRCDR_PZ_NOMZ \
190                                 | DDRCDR_NZ_NOMZ \
191                                 | DDRCDR_M_ODR )
192
193 /*
194  * FLASH on the Local Bus
195  */
196 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
197 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
198 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
199 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
200 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
201 #define CONFIG_SYS_FLASH_EMPTY_INFO                     /* display empty sectors */
202 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE               /* buffer up multiple bytes */
203
204 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE |        /* flash Base address */ \
205                                 (2 << BR_PS_SHIFT) |    /* 16 bit port size */ \
206                                 BR_V)                   /* valid */
207 #define CONFIG_SYS_NOR_OR_PRELIM        ( 0xFF800000            /* 8 MByte */ \
208                                 | OR_GPCM_XACS \
209                                 | OR_GPCM_SCY_9 \
210                                 | OR_GPCM_EHTR \
211                                 | OR_GPCM_EAD )
212                                 /* 0xFF006FF7   TODO SLOW 16 MB flash size */
213 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE   /* window base at flash base */
214 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000017      /* 16 MB window size */
215
216 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
217 #define CONFIG_SYS_MAX_FLASH_SECT       135             /* sectors per device */
218
219 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
220 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
221
222 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
223 #define CONFIG_SYS_RAMBOOT
224 #endif
225
226 #define CONFIG_SYS_INIT_RAM_LOCK        1
227 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM address */
228 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000          /* Size of used area in RAM*/
229
230 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
231 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
232
233 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
234 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384 kB for Mon */
235 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)    /* Reserved for malloc */
236
237 /*
238  * Local Bus LCRR and LBCR regs
239  */
240 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
241 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
242 #define CONFIG_SYS_LBC_LBCR     ( 0x00040000 /* TODO */ \
243                         | (0xFF << LBCR_BMT_SHIFT) \
244                         | 0xF ) /* 0x0004ff0f */
245
246 #define CONFIG_SYS_LBC_MRTPR    0x20000000  /*TODO */   /* LB refresh timer prescal, 266MHz/32 */
247
248 /* drivers/mtd/nand/nand.c */
249 #ifdef CONFIG_NAND_SPL
250 #define CONFIG_SYS_NAND_BASE            0xFFF00000
251 #else
252 #define CONFIG_SYS_NAND_BASE            0xE2800000
253 #endif
254
255 #define CONFIG_MTD_DEVICE
256 #define CONFIG_MTD_PARTITION
257 #define CONFIG_CMD_MTDPARTS
258 #define MTDIDS_DEFAULT                  "nand0=e2800000.flash"
259 #define MTDPARTS_DEFAULT                \
260         "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
261
262 #define CONFIG_SYS_MAX_NAND_DEVICE      1
263 #define CONFIG_MTD_NAND_VERIFY_WRITE
264 #define CONFIG_CMD_NAND 1
265 #define CONFIG_NAND_FSL_ELBC 1
266 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
267
268
269 #define CONFIG_SYS_NAND_BR_PRELIM       ( CONFIG_SYS_NAND_BASE \
270                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
271                                 | BR_PS_8               /* Port Size = 8 bit */ \
272                                 | BR_MS_FCM             /* MSEL = FCM */ \
273                                 | BR_V )                /* valid */
274 #define CONFIG_SYS_NAND_OR_PRELIM       ( 0xFFFF8000            /* length 32K */ \
275                                 | OR_FCM_CSCT \
276                                 | OR_FCM_CST \
277                                 | OR_FCM_CHT \
278                                 | OR_FCM_SCY_1 \
279                                 | OR_FCM_TRLX \
280                                 | OR_FCM_EHTR )
281                                 /* 0xFFFF8396 */
282
283 #ifdef CONFIG_NAND_U_BOOT
284 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
285 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
286 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
287 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
288 #else
289 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
290 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
291 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
292 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
293 #endif
294
295 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
296 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E      /* 32KB  */
297
298 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
299 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
300
301 /* local bus read write buffer mapping */
302 #define CONFIG_SYS_BR3_PRELIM           0xFA000801      /* map at 0xFA000000 */
303 #define CONFIG_SYS_OR3_PRELIM           0xFFFF8FF7      /* 32kB */
304 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0xFA000000
305 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000E      /* 32KB  */
306
307 /* Vitesse 7385 */
308
309 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
310
311 #ifdef CONFIG_VSC7385_ENET
312
313 #define CONFIG_SYS_BR2_PRELIM           0xf0000801      /* VSC7385 Base address */
314 #define CONFIG_SYS_OR2_PRELIM           0xfffe09ff      /* VSC7385, 128K bytes*/
315 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */
316 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000010      /* Access window size 128K */
317
318 #endif
319
320 /* pass open firmware flat tree */
321 #define CONFIG_OF_LIBFDT        1
322 #define CONFIG_OF_BOARD_SETUP   1
323 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
324
325 /*
326  * Serial Port
327  */
328 #define CONFIG_CONS_INDEX       1
329 #define CONFIG_SYS_NS16550
330 #define CONFIG_SYS_NS16550_SERIAL
331 #define CONFIG_SYS_NS16550_REG_SIZE     1
332
333 #define CONFIG_SYS_BAUDRATE_TABLE       \
334         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
335
336 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
337 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
338
339 /* Use the HUSH parser */
340 #define CONFIG_SYS_HUSH_PARSER
341 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
342
343 /* I2C */
344 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
345 #define CONFIG_FSL_I2C
346 #define CONFIG_I2C_MULTI_BUS
347 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
348 #define CONFIG_SYS_I2C_SLAVE            0x7F
349 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
350 #define CONFIG_SYS_I2C_OFFSET           0x3000
351 #define CONFIG_SYS_I2C2_OFFSET          0x3100
352
353 /*
354  * General PCI
355  * Addresses are mapped 1-1.
356  */
357 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
358 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
359 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
360 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
361 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
362 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
363 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
364 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
365 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
366
367 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
368 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
369
370 /*
371  * TSEC
372  */
373 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
374
375 #define CONFIG_NET_MULTI
376 #define CONFIG_GMII                     /* MII PHY management */
377
378 #ifdef CONFIG_TSEC1
379 #define CONFIG_HAS_ETH0
380 #define CONFIG_TSEC1_NAME       "TSEC0"
381 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
382 #define TSEC1_PHY_ADDR          0x1c
383 #define TSEC1_FLAGS             TSEC_GIGABIT
384 #define TSEC1_PHYIDX            0
385 #endif
386
387 #ifdef CONFIG_TSEC2
388 #define CONFIG_HAS_ETH1
389 #define CONFIG_TSEC2_NAME       "TSEC1"
390 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
391 #define TSEC2_PHY_ADDR          4
392 #define TSEC2_FLAGS             TSEC_GIGABIT
393 #define TSEC2_PHYIDX            0
394 #endif
395
396
397 /* Options are: TSEC[0-1] */
398 #define CONFIG_ETHPRIME                 "TSEC1"
399
400 /*
401  * Configure on-board RTC
402  */
403 #define CONFIG_RTC_DS1337
404 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
405
406 /*
407  * Environment
408  */
409 #if defined(CONFIG_NAND_U_BOOT)
410         #define CONFIG_ENV_IS_IN_NAND   1
411         #define CONFIG_ENV_OFFSET               (512 * 1024)
412         #define CONFIG_ENV_SECT_SIZE    CONFIG_SYS_NAND_BLOCK_SIZE
413         #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
414         #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
415         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
416         #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
417 #elif !defined(CONFIG_SYS_RAMBOOT)
418         #define CONFIG_ENV_IS_IN_FLASH  1
419         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
420         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
421         #define CONFIG_ENV_SIZE         0x2000
422
423 /* Address and size of Redundant Environment Sector */
424 #else
425         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
426         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
427         #define CONFIG_ENV_SIZE         0x2000
428 #endif
429
430 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
431 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
432
433 /*
434  * BOOTP options
435  */
436 #define CONFIG_BOOTP_BOOTFILESIZE
437 #define CONFIG_BOOTP_BOOTPATH
438 #define CONFIG_BOOTP_GATEWAY
439 #define CONFIG_BOOTP_HOSTNAME
440
441
442 /*
443  * Command line configuration.
444  */
445 #include <config_cmd_default.h>
446
447 #define CONFIG_CMD_PING
448 #define CONFIG_CMD_DHCP
449 #define CONFIG_CMD_I2C
450 #define CONFIG_CMD_MII
451 #define CONFIG_CMD_DATE
452 #define CONFIG_CMD_PCI
453
454 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
455     #undef CONFIG_CMD_SAVEENV
456     #undef CONFIG_CMD_LOADS
457 #endif
458
459 #define CONFIG_CMDLINE_EDITING 1
460 #define CONFIG_AUTO_COMPLETE    /* add autocompletion support   */
461
462 /*
463  * Miscellaneous configurable options
464  */
465 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
466 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
467 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
468 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
469
470 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
471 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
472 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
473 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
474
475 /*
476  * For booting Linux, the board info and command line data
477  * have to be in the first 256 MB of memory, since this is
478  * the maximum mapped by the Linux kernel during initialization.
479  */
480 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
481
482 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000      /* PCIHOST  */
483
484 #ifdef CONFIG_SYS_66MHZ
485
486 /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
487 /* 0x62040000 */
488 #define CONFIG_SYS_HRCW_LOW (\
489         0x20000000 /* reserved, must be set */ |\
490         HRCWL_DDRCM |\
491         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
492         HRCWL_DDR_TO_SCB_CLK_2X1 |\
493         HRCWL_CSB_TO_CLKIN_2X1 |\
494         HRCWL_CORE_TO_CSB_2X1)
495
496 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
497
498 #elif defined(CONFIG_SYS_33MHZ)
499
500 /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
501 /* 0x65040000 */
502 #define CONFIG_SYS_HRCW_LOW (\
503         0x20000000 /* reserved, must be set */ |\
504         HRCWL_DDRCM |\
505         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
506         HRCWL_DDR_TO_SCB_CLK_2X1 |\
507         HRCWL_CSB_TO_CLKIN_5X1 |\
508         HRCWL_CORE_TO_CSB_2X1)
509
510 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
511
512 #endif
513
514 #define CONFIG_SYS_HRCW_HIGH_BASE (\
515         HRCWH_PCI_HOST |\
516         HRCWH_PCI1_ARBITER_ENABLE |\
517         HRCWH_CORE_ENABLE |\
518         HRCWH_BOOTSEQ_DISABLE |\
519         HRCWH_SW_WATCHDOG_DISABLE |\
520         HRCWH_TSEC1M_IN_RGMII |\
521         HRCWH_TSEC2M_IN_RGMII |\
522         HRCWH_BIG_ENDIAN)
523
524 #ifdef CONFIG_NAND_SPL
525 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
526                        HRCWH_FROM_0XFFF00100 |\
527                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
528                        HRCWH_RL_EXT_NAND)
529 #else
530 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
531                        HRCWH_FROM_0X00000100 |\
532                        HRCWH_ROM_LOC_LOCAL_16BIT |\
533                        HRCWH_RL_EXT_LEGACY)
534 #endif
535
536 /* System IO Config */
537 #define CONFIG_SYS_SICRH        (SICRH_TSOBI1 | SICRH_TSOBI2)   /* RGMII */
538 #define CONFIG_SYS_SICRL        SICRL_USBDR_10                  /* Enable Internal USB Phy  */
539
540 #define CONFIG_SYS_HID0_INIT    0x000000000
541 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
542                                  HID0_ENABLE_INSTRUCTION_CACHE | \
543                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
544
545 #define CONFIG_SYS_HID2 HID2_HBE
546
547 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
548
549 /* DDR @ 0x00000000 */
550 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
551 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
552
553 /* PCI @ 0x80000000 */
554 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
555 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
556 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
557 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
558
559 /* PCI2 not supported on 8313 */
560 #define CONFIG_SYS_IBAT3L       (0)
561 #define CONFIG_SYS_IBAT3U       (0)
562 #define CONFIG_SYS_IBAT4L       (0)
563 #define CONFIG_SYS_IBAT4U       (0)
564
565 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
566 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
567 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
568
569 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
570 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
571 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
572
573 #define CONFIG_SYS_IBAT7L       (0)
574 #define CONFIG_SYS_IBAT7U       (0)
575
576 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
577 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
578 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
579 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
580 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
581 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
582 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
583 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
584 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
585 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
586 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
587 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
588 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
589 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
590 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
591 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
592
593 /*
594  * Environment Configuration
595  */
596 #define CONFIG_ENV_OVERWRITE
597
598 #define CONFIG_NETDEV           eth1
599
600 #define CONFIG_HOSTNAME         mpc8313erdb
601 #define CONFIG_ROOTPATH         /nfs/root/path
602 #define CONFIG_BOOTFILE         uImage
603 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
604 #define CONFIG_FDTFILE          mpc8313erdb.dtb
605
606 #define CONFIG_LOADADDR         800000  /* default location for tftp and bootm */
607 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
608 #define CONFIG_BAUDRATE         115200
609
610 #define XMK_STR(x)      #x
611 #define MK_STR(x)       XMK_STR(x)
612
613 #define CONFIG_EXTRA_ENV_SETTINGS \
614         "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
615         "ethprime=TSEC1\0"                                              \
616         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
617         "tftpflash=tftpboot $loadaddr $uboot; "                         \
618                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
619                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
620                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
621                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
622                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
623         "fdtaddr=780000\0"                                              \
624         "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"                          \
625         "console=ttyS0\0"                                               \
626         "setbootargs=setenv bootargs "                                  \
627                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
628         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
629                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
630                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
631
632 #define CONFIG_NFSBOOTCOMMAND                                           \
633         "setenv rootdev /dev/nfs;"                                      \
634         "run setbootargs;"                                              \
635         "run setipargs;"                                                \
636         "tftp $loadaddr $bootfile;"                                     \
637         "tftp $fdtaddr $fdtfile;"                                       \
638         "bootm $loadaddr - $fdtaddr"
639
640 #define CONFIG_RAMBOOTCOMMAND                                           \
641         "setenv rootdev /dev/ram;"                                      \
642         "run setbootargs;"                                              \
643         "tftp $ramdiskaddr $ramdiskfile;"                               \
644         "tftp $loadaddr $bootfile;"                                     \
645         "tftp $fdtaddr $fdtfile;"                                       \
646         "bootm $loadaddr $ramdiskaddr $fdtaddr"
647
648 #undef MK_STR
649 #undef XMK_STR
650
651 #endif  /* __CONFIG_H */