3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
10 * (C) Copyright 2003-2004 Arabella Software Ltd.
11 * Yuli Barcohen <yuli@arabellasw.com>
12 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
13 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
14 * Ported to MPC8272ADS board.
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 * High Level Configuration Options
43 #define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
46 * Figure out if we are booting low via flash HRCW or high via the BCSR.
48 #if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
49 # define CFG_LOWBOOT 1
54 #define CFG_8260ADS 1 /* MPC8260ADS */
55 #define CFG_8266ADS 2 /* MPC8266ADS */
56 #define CFG_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
57 #define CFG_8272ADS 4 /* MPC8272ADS */
59 #ifndef CONFIG_ADSTYPE
60 #define CONFIG_ADSTYPE CFG_8260ADS
61 #endif /* CONFIG_ADSTYPE */
63 #if CONFIG_ADSTYPE == CFG_8272ADS
64 #define CONFIG_MPC8272 1
66 #define CONFIG_MPC8260 1
67 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
69 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
71 /* allow serial and ethaddr to be overwritten */
72 #define CONFIG_ENV_OVERWRITE
75 * select serial console configuration
77 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
78 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
81 * if CONFIG_CONS_NONE is defined, then the serial console routines must
82 * defined elsewhere (for example, on the cogent platform, there are serial
83 * ports on the motherboard which are used for the serial console - see
84 * cogent/cma101/serial.[ch]).
86 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
87 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
88 #undef CONFIG_CONS_NONE /* define if console on something else */
89 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
92 * select ethernet configuration
94 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
95 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
98 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
99 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
100 * from CONFIG_COMMANDS to remove support for networking.
102 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
103 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
104 #undef CONFIG_ETHER_NONE /* define if ether on something else */
106 #ifdef CONFIG_ETHER_ON_FCC
108 #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
110 #if CONFIG_ETHER_INDEX == 1
112 # define CFG_PHY_ADDR 0
113 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
114 # define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
116 #elif CONFIG_ETHER_INDEX == 2
118 #if CONFIG_ADSTYPE == CFG_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
119 # define CFG_PHY_ADDR 3
120 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
121 #else /* RxCLK is CLK13, TxCLK is CLK14 */
122 # define CFG_PHY_ADDR 0
123 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
124 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
126 # define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
128 #endif /* CONFIG_ETHER_INDEX */
130 #define CFG_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
131 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
133 #define CONFIG_MII /* MII PHY management */
134 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
136 * GPIO pins used for bit-banged MII communications
138 #define MDIO_PORT 2 /* Port C */
140 #if CONFIG_ADSTYPE == CFG_8272ADS
141 #define CFG_MDIO_PIN 0x00002000 /* PC18 */
142 #define CFG_MDC_PIN 0x00001000 /* PC19 */
144 #define CFG_MDIO_PIN 0x00400000 /* PC9 */
145 #define CFG_MDC_PIN 0x00200000 /* PC10 */
146 #endif /* CONFIG_ADSTYPE == CFG_8272ADS */
148 #define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
149 #define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
150 #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
152 #define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
153 else iop->pdat &= ~CFG_MDIO_PIN
155 #define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
156 else iop->pdat &= ~CFG_MDC_PIN
158 #define MIIDELAY udelay(1)
160 #endif /* CONFIG_ETHER_ON_FCC */
162 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
163 #undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
165 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
166 #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
167 #define CFG_I2C_SLAVE 0x7F
169 #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
170 #define CONFIG_SPD_ADDR 0x50
172 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
174 #ifndef CONFIG_SDRAM_PBI
175 #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
178 #ifndef CONFIG_8260_CLKIN
179 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
180 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
182 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
186 #define CONFIG_BAUDRATE 115200
188 #define CFG_EXCLUDE CFG_CMD_BEDBUG | \
216 #if CONFIG_ADSTYPE >= CFG_PQ2FADS
217 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
222 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
224 #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
226 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
227 #include <cmd_confdefs.h>
229 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
230 #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
231 #define CONFIG_BOOTARGS "root=/dev/mtdblock2"
233 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
234 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
235 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
236 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
237 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
238 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
241 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
242 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
245 * Miscellaneous configurable options
247 #define CFG_HUSH_PARSER
248 #define CFG_PROMPT_HUSH_PS2 "> "
249 #define CFG_LONGHELP /* undef to save memory */
250 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
251 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
252 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
254 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
256 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
257 #define CFG_MAXARGS 16 /* max number of command args */
258 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
260 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
261 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
263 #define CFG_LOAD_ADDR 0x400000 /* default load address */
265 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
267 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
269 #define CFG_FLASH_BASE 0xff800000
270 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
271 #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
272 #define CFG_FLASH_SIZE 8
273 #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
274 #define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
275 #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
276 #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
277 #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
279 #define CFG_JFFS2_FIRST_SECTOR 1
280 #define CFG_JFFS2_LAST_SECTOR 27
281 #define CFG_JFFS2_SORT_FRAGMENTS
282 #define CFG_JFFS_CUSTOM_PART
284 /* this is stuff came out of the Motorola docs */
286 #define CFG_DEFAULT_IMMR 0x0F010000
289 #define CFG_IMMR 0xF0000000
290 #define CFG_BCSR 0xF4500000
291 #define CFG_SDRAM_BASE 0x00000000
292 #define CFG_LSDRAM_BASE 0xFD000000
294 #define RS232EN_1 0x02000002
295 #define RS232EN_2 0x01000001
296 #define FETHIEN1 0x08000008
297 #define FETH1_RST 0x04000004
298 #define FETHIEN2 0x10000000
299 #define FETH2_RST 0x08000000
300 #define BCSR_PCI_MODE 0x01000000
302 #define CFG_INIT_RAM_ADDR CFG_IMMR
303 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
304 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
305 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
306 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
310 /* PQ2FADS flash HRCW = 0x0EB4B645 */
311 #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
312 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
313 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
314 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
317 /* PQ2FADS BCSR HRCW = 0x0CB23645 */
318 #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
319 ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
320 ( HRCW_BMS | HRCW_APPC10 ) |\
321 ( HRCW_MODCK_H0101 ) \
325 #define CFG_HRCW_SLAVE1 0
326 #define CFG_HRCW_SLAVE2 0
327 #define CFG_HRCW_SLAVE3 0
328 #define CFG_HRCW_SLAVE4 0
329 #define CFG_HRCW_SLAVE5 0
330 #define CFG_HRCW_SLAVE6 0
331 #define CFG_HRCW_SLAVE7 0
333 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
334 #define BOOTFLAG_WARM 0x02 /* Software reboot */
336 #define CFG_MONITOR_BASE TEXT_BASE
337 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
341 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
342 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
345 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
347 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
348 #endif /* CONFIG_BZIP2 */
351 # define CFG_ENV_IS_IN_FLASH 1
352 # define CFG_ENV_SECT_SIZE 0x40000
353 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
355 # define CFG_ENV_IS_IN_NVRAM 1
356 # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
357 # define CFG_ENV_SIZE 0x200
358 #endif /* CFG_RAMBOOT */
361 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
362 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
363 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
367 #define CFG_HID0_INIT 0
368 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
372 #define CFG_SYPCR 0xFFFFFFC3
373 #define CFG_BCR 0x100C0000
374 #define CFG_SIUMCR 0x0A200000
375 #define CFG_SCCR SCCR_DFBRG01
376 #define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801
377 #define CFG_OR0_PRELIM 0xFF800876
378 #define CFG_BR1_PRELIM CFG_BCSR | 0x00001801
379 #define CFG_OR1_PRELIM 0xFFFF8010
381 #define CFG_RMR RMR_CSRE
382 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
383 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
386 #if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
387 #undef CFG_LSDRAM_BASE /* No local bus SDRAM on these boards */
388 #endif /* CONFIG_ADSTYPE == CFG_8266ADS */
390 #if CONFIG_ADSTYPE == CFG_PQ2FADS
391 #define CFG_OR2 0xFE002EC0
392 #define CFG_PSDMR 0x824B36A3
393 #define CFG_PSRT 0x13
394 #define CFG_LSDMR 0x828737A3
395 #define CFG_LSRT 0x13
396 #define CFG_MPTPR 0x2800
397 #elif CONFIG_ADSTYPE == CFG_8272ADS
398 #define CFG_OR2 0xFC002CC0
399 #define CFG_PSDMR 0x834E24A3
400 #define CFG_PSRT 0x13
401 #define CFG_MPTPR 0x2800
403 #define CFG_OR2 0xFF000CA0
404 #define CFG_PSDMR 0x016EB452
405 #define CFG_PSRT 0x21
406 #define CFG_LSDMR 0x0086A522
407 #define CFG_LSRT 0x21
408 #define CFG_MPTPR 0x1900
409 #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
411 #define CFG_RESET_ADDRESS 0x04400000
413 #endif /* __CONFIG_H */