3 * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Configuation settings for the miniHiPerCam.
10 * -----------------------------------------------------------------
11 * SPDX-License-Identifier: GPL-2.0+
15 * board/config.h - configuration options, board specific
22 * High Level Configuration Options
25 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
26 #define CONFIG_MHPC 1 /* on a miniHiPerCam */
27 #define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */
28 #define CONFIG_MISC_INIT_R 1
30 #define CONFIG_SYS_TEXT_BASE 0xfe000000
32 #define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
33 #undef CONFIG_8xx_CONS_SMC1
34 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
35 #undef CONFIG_8xx_CONS_NONE
36 #define CONFIG_BAUDRATE 9600
37 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
39 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
41 #define CONFIG_ENV_OVERWRITE 1
42 #define CONFIG_ETHADDR 00:00:5b:ee:de:ad
44 #undef CONFIG_BOOTARGS
45 #define CONFIG_BOOTCOMMAND \
47 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
48 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
51 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
52 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
54 #undef CONFIG_WATCHDOG /* watchdog disabled */
55 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
57 #undef CONFIG_UCODE_PATCH
59 /* enable I2C and select the hardware/software driver */
60 #define CONFIG_SYS_I2C
61 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
62 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
63 #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
65 * Software (bit-bang) I2C driver configuration
67 #define PB_SCL 0x00000020 /* PB 26 */
68 #define PB_SDA 0x00000010 /* PB 27 */
70 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
71 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
72 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
73 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
74 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
75 else immr->im_cpm.cp_pbdat &= ~PB_SDA
76 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
77 else immr->im_cpm.cp_pbdat &= ~PB_SCL
78 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
80 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */
81 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
82 /* mask of address bits that overflow into the "EEPROM chip address" */
83 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
84 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
85 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
87 #define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
88 #define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */
89 #define LCD_VIDEO_COLS 640
90 #define LCD_VIDEO_ROWS 480
91 #define LCD_VIDEO_FG 255
92 #define LCD_VIDEO_BG 0
94 #undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */
95 #define CONFIG_CFB_CONSOLE /* framebuffer console with std input */
96 #define CONFIG_VIDEO_LOGO
98 #define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */
99 #define VIDEO_TSTC_FCT serial_tstc
100 #define VIDEO_GETC_FCT serial_getc
102 #define CONFIG_BR0_WORKAROUND 1
106 * Command line configuration.
108 #include <config_cmd_default.h>
110 #define CONFIG_CMD_DATE
111 #define CONFIG_CMD_EEPROM
112 #define CONFIG_CMD_ELF
113 #define CONFIG_CMD_I2C
114 #define CONFIG_CMD_JFFS2
115 #define CONFIG_CMD_REGINFO
121 #define CONFIG_BOOTP_SUBNETMASK
122 #define CONFIG_BOOTP_GATEWAY
123 #define CONFIG_BOOTP_HOSTNAME
124 #define CONFIG_BOOTP_BOOTPATH
125 #define CONFIG_BOOTP_BOOTFILESIZE
129 * Miscellaneous configurable options
131 #define CONFIG_SYS_LONGHELP /* undef to save memory */
132 #if defined(CONFIG_CMD_KGDB)
133 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
135 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
137 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
138 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
139 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
141 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
142 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
144 #define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
146 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
149 * Low Level Configuration Settings
150 * (address mappings, register initial values, etc.)
151 * You should know what you are doing if you make changes here.
154 /*-----------------------------------------------------------------------
155 * Physical memory map
157 #define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/
159 /*-----------------------------------------------------------------------
160 * Definitions for initial stack pointer and data area (in DPRAM)
162 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
163 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
164 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
165 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
167 /*-----------------------------------------------------------------------
168 * Start addresses for the final memory configuration
169 * (Set up by the startup code)
170 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
172 #define CONFIG_SYS_SDRAM_BASE 0x00000000
173 #define CONFIG_SYS_FLASH_BASE 0xfe000000
175 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
176 #undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */
177 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
178 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
184 /* No command line, one static partition, whole device */
185 #undef CONFIG_CMD_MTDPARTS
186 #define CONFIG_JFFS2_DEV "nor0"
187 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
188 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
190 /* mtdparts command line support */
191 /* Note: fake mtd_id used, no linux mtd map file */
193 #define CONFIG_CMD_MTDPARTS
194 #define MTDIDS_DEFAULT "nor0=mhpc-0"
195 #define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)"
199 * For booting Linux, the board info and command line data
200 * have to be in the first 8 MB of memory, since this is
201 * the maximum mapped by the Linux kernel during initialization.
203 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */
205 /*-----------------------------------------------------------------------
208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
209 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
211 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
212 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
213 #define CONFIG_ENV_IS_IN_FLASH 1
214 #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
215 #define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
217 /*-----------------------------------------------------------------------
218 * Cache Configuration
220 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
221 #if defined(CONFIG_CMD_KGDB)
222 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
225 /*-----------------------------------------------------------------------
226 * SYPCR - System Protection Control 11-9
227 * SYPCR can only be written once after reset!
228 *-----------------------------------------------------------------------
229 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
231 #if defined(CONFIG_WATCHDOG)
232 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
233 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
235 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
239 /*-----------------------------------------------------------------------
240 * SIUMCR - SIU Module Configuration 11-6
241 *-----------------------------------------------------------------------
242 * PCMCIA config., multi-function pin tri-state
244 #define CONFIG_SYS_SIUMCR (SIUMCR_SEME)
246 /*-----------------------------------------------------------------------
247 * TBSCR - Time Base Status and Control 11-26
248 *-----------------------------------------------------------------------
249 * Clear Reference Interrupt Status, Timebase freezing enabled
251 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
253 /*-----------------------------------------------------------------------
254 * PISCR - Periodic Interrupt Status and Control 11-31
255 *-----------------------------------------------------------------------
256 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
258 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
260 /*-----------------------------------------------------------------------
261 * RTCSC - Real-Time Clock Status and Control Register 12-18
262 *-----------------------------------------------------------------------
264 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
266 /*-----------------------------------------------------------------------
267 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
268 *-----------------------------------------------------------------------
269 * Reset PLL lock status sticky bit, timer expired status bit and timer
270 * interrupt status bit - leave PLL multiplication factor unchanged !
272 #define MPC8XX_SPEED 50000000L
273 #define MPC8XX_XIN 5000000L /* ref clk */
274 #define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
275 #define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
276 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
278 /*-----------------------------------------------------------------------
279 * SCCR - System Clock and reset Control Register 15-27
280 *-----------------------------------------------------------------------
281 * Set clock output, timebase and RTC source and divider,
282 * power management and some other internal clocks
285 #define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */
286 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001)
289 /*-----------------------------------------------------------------------
290 * MAMR settings for SDRAM - 16-14
292 *-----------------------------------------------------------------------
293 * periodic timer for refresh
295 #define CONFIG_SYS_MAMR_PTA 0xC0
296 #define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
299 * BR0 and OR0 (FLASH) used to re-map FLASH
302 /* allow for max 8 MB of Flash */
303 #define FLASH_BASE 0xFE000000 /* FLASH bank #0*/
304 #define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/
305 #define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
306 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
308 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
310 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
311 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
312 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
315 * BR1 and OR1 (SDRAM)
317 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
318 #define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
319 #define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */
321 /* SDRAM timing: drive GPL5 high on first cycle */
322 #define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS)
324 #define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
325 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
330 #define CONFIG_SYS_OR2 (OR_ACS_DIV4)
331 #define CONFIG_SYS_BR2 (BR_MS_UPMA)
336 #define CONFIG_SYS_OR3 (OR_ACS_DIV4)
337 #define CONFIG_SYS_BR3 (BR_MS_UPMA)
342 #define CONFIG_SYS_OR4 0
343 #define CONFIG_SYS_BR4 0
348 #define CONFIG_SYS_OR5 0
349 #define CONFIG_SYS_BR5 0
354 #define CONFIG_SYS_OR6 0
355 #define CONFIG_SYS_BR6 0
360 #define CONFIG_SYS_OR7 0
361 #define CONFIG_SYS_BR7 0
364 /*-----------------------------------------------------------------------
366 *-----------------------------------------------------------------------
369 #define CONFIG_SYS_DER 0
371 #endif /* __CONFIG_H */