include/configs/M54455EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54455 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54455EVB_H
  15 #define _M54455EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54455EVB        /* M54455EVB board */
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25
  26 #define LDS_BOARD_TEXT                  board/freescale/m54455evb/sbf_dram_init.o (.text*)
  27
  28 #undef CONFIG_WATCHDOG
  29
  30 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  31
  32 /*
  33  * BOOTP options
  34  */
  35 #define CONFIG_BOOTP_BOOTFILESIZE
  36
  37 /* Network configuration */
  38 #define CONFIG_MCFFEC
  39 #ifdef CONFIG_MCFFEC
  40 #       define CONFIG_MII               1
  41 #       define CONFIG_MII_INIT          1
  42 #       define CONFIG_SYS_DISCOVER_PHY
  43 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  44 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  45
  46 #       define CONFIG_SYS_FEC0_PINMUX   0
  47 #       define CONFIG_SYS_FEC1_PINMUX   0
  48 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  49 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  50 #       define MCFFEC_TOUT_LOOP 50000
  51 #       define CONFIG_HAS_ETH1
  52
  53 #       define CONFIG_ETHPRIME          "FEC0"
  54 #       define CONFIG_IPADDR            192.162.1.2
  55 #       define CONFIG_NETMASK           255.255.255.0
  56 #       define CONFIG_SERVERIP          192.162.1.1
  57 #       define CONFIG_GATEWAYIP         192.162.1.1
  58
  59 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  60 #       ifndef CONFIG_SYS_DISCOVER_PHY
  61 #               define FECDUPLEX        FULL
  62 #               define FECSPEED         _100BASET
  63 #       else
  64 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  65 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  66 #               endif
  67 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  68 #endif
  69
  70 #define CONFIG_HOSTNAME         "M54455EVB"
  71 #ifdef CONFIG_SYS_STMICRO_BOOT
  72 /* ST Micro serial flash */
  73 #define CONFIG_SYS_LOAD_ADDR2           0x40010013
  74 #define CONFIG_EXTRA_ENV_SETTINGS               \
  75         "netdev=eth0\0"                         \
  76         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  77         "loadaddr=0x40010000\0"                 \
  78         "sbfhdr=sbfhdr.bin\0"                   \
  79         "uboot=u-boot.bin\0"                    \
  80         "load=tftp ${loadaddr} ${sbfhdr};"      \
  81         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
  82         "upd=run load; run prog\0"              \
  83         "prog=sf probe 0:1 1000000 3;"          \
  84         "sf erase 0 30000;"                     \
  85         "sf write ${loadaddr} 0 0x30000;"       \
  86         "save\0"                                \
  87         ""
  88 #else
  89 /* Atmel and Intel */
  90 #ifdef CONFIG_SYS_ATMEL_BOOT
  91 #       define CONFIG_SYS_UBOOT_END     0x0403FFFF
  92 #elif defined(CONFIG_SYS_INTEL_BOOT)
  93 #       define CONFIG_SYS_UBOOT_END     0x3FFFF
  94 #endif
  95 #define CONFIG_EXTRA_ENV_SETTINGS               \
  96         "netdev=eth0\0"                         \
  97         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  98         "loadaddr=0x40010000\0"                 \
  99         "uboot=u-boot.bin\0"                    \
 100         "load=tftp ${loadaddr} ${uboot}\0"      \
 101         "upd=run load; run prog\0"              \
 102         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
 103         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
 104         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
 105         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
 106         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
 107         " ${filesize}; save\0"                  \
 108         ""
 109 #endif
 110
 111 /* ATA configuration */
 112 #define CONFIG_IDE_RESET        1
 113 #define CONFIG_IDE_PREINIT      1
 114 #define CONFIG_ATAPI
 115 #undef CONFIG_LBA48
 116
 117 #define CONFIG_SYS_IDE_MAXBUS           1
 118 #define CONFIG_SYS_IDE_MAXDEVICE        2
 119
 120 #define CONFIG_SYS_ATA_BASE_ADDR        0x90000000
 121 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
 122
 123 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O                            */
 124 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
 125 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers           */
 126 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers                 */
 127
 128 /* Realtime clock */
 129 #define CONFIG_MCFRTC
 130 #undef RTC_DEBUG
 131 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 132
 133 /* Timer */
 134 #define CONFIG_MCFTMR
 135 #undef CONFIG_MCFPIT
 136
 137 /* I2c */
 138 #define CONFIG_SYS_I2C
 139 #define CONFIG_SYS_I2C_FSL
 140 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 141 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 142 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 143 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 144
 145 /* DSPI and Serial Flash */
 146 #define CONFIG_CF_DSPI
 147 #define CONFIG_HARD_SPI
 148 #define CONFIG_SYS_SBFHDR_SIZE          0x13
 149 #ifdef CONFIG_CMD_SPI
 150
 151 #       define CONFIG_SYS_DSPI_CTAR0            (DSPI_CTAR_TRSZ(7) | \
 152                                          DSPI_CTAR_PCSSCK_1CLK | \
 153                                          DSPI_CTAR_PASC(0) | \
 154                                          DSPI_CTAR_PDT(0) | \
 155                                          DSPI_CTAR_CSSCK(0) | \
 156                                          DSPI_CTAR_ASC(0) | \
 157                                          DSPI_CTAR_DT(1))
 158 #endif
 159
 160 /* PCI */
 161 #ifdef CONFIG_CMD_PCI
 162 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 163
 164 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  4
 165
 166 #define CONFIG_SYS_PCI_MEM_BUS          0xA0000000
 167 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 168 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 169
 170 #define CONFIG_SYS_PCI_IO_BUS           0xB1000000
 171 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 172 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 173
 174 #define CONFIG_SYS_PCI_CFG_BUS          0xB0000000
 175 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 176 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 177 #endif
 178
 179 /* FPGA - Spartan 2 */
 180 /* experiment
 181 #define CONFIG_FPGA_COUNT       1
 182 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 183 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 184 */
 185
 186 /* Input, PCI, Flexbus, and VCO */
 187 #define CONFIG_EXTRA_CLOCK
 188
 189 #define CONFIG_PRAM             2048    /* 2048 KB */
 190
 191 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 192
 193 #define CONFIG_SYS_MBAR         0xFC000000
 194
 195 /*
 196  * Low Level Configuration Settings
 197  * (address mappings, register initial values, etc.)
 198  * You should know what you are doing if you make changes here.
 199  */
 200
 201 /*-----------------------------------------------------------------------
 202  * Definitions for initial stack pointer and data area (in DPRAM)
 203  */
 204 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 205 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 206 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 207 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 208 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 209 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 210
 211 /*-----------------------------------------------------------------------
 212  * Start addresses for the final memory configuration
 213  * (Set up by the startup code)
 214  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 215  */
 216 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 217 #define CONFIG_SYS_SDRAM_BASE1          0x48000000
 218 #define CONFIG_SYS_SDRAM_SIZE           256     /* SDRAM size in MB */
 219 #define CONFIG_SYS_SDRAM_CFG1           0x65311610
 220 #define CONFIG_SYS_SDRAM_CFG2           0x59670000
 221 #define CONFIG_SYS_SDRAM_CTRL           0xEA0B2000
 222 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 223 #define CONFIG_SYS_SDRAM_MODE           0x00010033
 224 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0xAA
 225
 226 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 227 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 228
 229 #ifdef CONFIG_CF_SBF
 230 #       define CONFIG_SERIAL_BOOT
 231 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 232 #else
 233 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 234 #endif
 235 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 236 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 237
 238 /* Reserve 256 kB for malloc() */
 239 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 240
 241 /*
 242  * For booting Linux, the board info and command line data
 243  * have to be in the first 8 MB of memory, since this is
 244  * the maximum mapped by the Linux kernel during initialization ??
 245  */
 246 /* Initial Memory map for Linux */
 247 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 248
 249 /*
 250  * Configuration for environment
 251  * Environment is not embedded in u-boot. First time runing may have env
 252  * crc error warning if there is no correct environment on the flash.
 253  */
 254 #ifdef CONFIG_CF_SBF
 255 #       define CONFIG_ENV_SPI_CS                1
 256 #endif
 257 #undef CONFIG_ENV_OVERWRITE
 258
 259 /*-----------------------------------------------------------------------
 260  * FLASH organization
 261  */
 262 #ifdef CONFIG_SYS_STMICRO_BOOT
 263 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 264 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS1_BASE
 265 #       define CONFIG_ENV_OFFSET                0x30000
 266 #       define CONFIG_ENV_SIZE          0x2000
 267 #       define CONFIG_ENV_SECT_SIZE     0x10000
 268 #endif
 269 #ifdef CONFIG_SYS_ATMEL_BOOT
 270 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 271 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 272 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 273 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 274 #       define CONFIG_ENV_SIZE          0x2000
 275 #       define CONFIG_ENV_SECT_SIZE     0x10000
 276 #endif
 277 #ifdef CONFIG_SYS_INTEL_BOOT
 278 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 279 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 280 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 281 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 282 #       define CONFIG_ENV_SIZE          0x2000
 283 #       define CONFIG_ENV_SECT_SIZE     0x20000
 284 #endif
 285
 286 #define CONFIG_SYS_FLASH_CFI
 287 #ifdef CONFIG_SYS_FLASH_CFI
 288
 289 #       define CONFIG_FLASH_CFI_DRIVER  1
 290 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 291 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 292 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_8BIT
 293 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 294 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 295 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 296 #       define CONFIG_SYS_FLASH_CHECKSUM
 297 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 298 #       define CONFIG_FLASH_CFI_LEGACY
 299
 300 #ifdef CONFIG_FLASH_CFI_LEGACY
 301 #       define CONFIG_SYS_ATMEL_REGION          4
 302 #       define CONFIG_SYS_ATMEL_TOTALSECT       11
 303 #       define CONFIG_SYS_ATMEL_SECT            {1, 2, 1, 7}
 304 #       define CONFIG_SYS_ATMEL_SECTSZ          {0x4000, 0x2000, 0x8000, 0x10000}
 305 #endif
 306 #endif
 307
 308 /*
 309  * This is setting for JFFS2 support in u-boot.
 310  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 311  */
 312 #ifdef CONFIG_CMD_JFFS2
 313 #ifdef CF_STMICRO_BOOT
 314 #       define CONFIG_JFFS2_DEV         "nor1"
 315 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 316 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
 317 #endif
 318 #ifdef CONFIG_SYS_ATMEL_BOOT
 319 #       define CONFIG_JFFS2_DEV         "nor1"
 320 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 321 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
 322 #endif
 323 #ifdef CONFIG_SYS_INTEL_BOOT
 324 #       define CONFIG_JFFS2_DEV         "nor0"
 325 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x500000)
 326 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 327 #endif
 328 #endif
 329
 330 /*-----------------------------------------------------------------------
 331  * Cache Configuration
 332  */
 333 #define CONFIG_SYS_CACHELINE_SIZE               16
 334
 335 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 336                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 337 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 338                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 339 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 340 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 341 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 342                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 343                                          CF_ACR_EN | CF_ACR_SM_ALL)
 344 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 345                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 346 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 347                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 348                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 349
 350 /*-----------------------------------------------------------------------
 351  * Memory bank definitions
 352  */
 353 /*
 354  * CS0 - NOR Flash 1, 2, 4, or 8MB
 355  * CS1 - CompactFlash and registers
 356  * CS2 - CPLD
 357  * CS3 - FPGA
 358  * CS4 - Available
 359  * CS5 - Available
 360  */
 361
 362 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 363  /* Atmel Flash */
 364 #define CONFIG_SYS_CS0_BASE             0x04000000
 365 #define CONFIG_SYS_CS0_MASK             0x00070001
 366 #define CONFIG_SYS_CS0_CTRL             0x00001140
 367 /* Intel Flash */
 368 #define CONFIG_SYS_CS1_BASE             0x00000000
 369 #define CONFIG_SYS_CS1_MASK             0x01FF0001
 370 #define CONFIG_SYS_CS1_CTRL             0x00000D60
 371
 372 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS0_BASE
 373 #else
 374 /* Intel Flash */
 375 #define CONFIG_SYS_CS0_BASE             0x00000000
 376 #define CONFIG_SYS_CS0_MASK             0x01FF0001
 377 #define CONFIG_SYS_CS0_CTRL             0x00000D60
 378  /* Atmel Flash */
 379 #define CONFIG_SYS_CS1_BASE             0x04000000
 380 #define CONFIG_SYS_CS1_MASK             0x00070001
 381 #define CONFIG_SYS_CS1_CTRL             0x00001140
 382
 383 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS1_BASE
 384 #endif
 385
 386 /* CPLD */
 387 #define CONFIG_SYS_CS2_BASE             0x08000000
 388 #define CONFIG_SYS_CS2_MASK             0x00070001
 389 #define CONFIG_SYS_CS2_CTRL             0x003f1140
 390
 391 /* FPGA */
 392 #define CONFIG_SYS_CS3_BASE             0x09000000
 393 #define CONFIG_SYS_CS3_MASK             0x00070001
 394 #define CONFIG_SYS_CS3_CTRL             0x00000020
 395
 396 #endif                          /* _M54455EVB_H */