2 * Configuation settings for the Freescale MCF54418 TWR board.
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_M54418TWR /* M54418TWR board */
23 #define CONFIG_MCFUART
24 #define CONFIG_SYS_UART_PORT (0)
25 #define CONFIG_BAUDRATE 115200
26 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
28 #undef CONFIG_WATCHDOG
30 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
35 #define CONFIG_BOOTP_BOOTFILESIZE
36 #define CONFIG_BOOTP_BOOTPATH
37 #define CONFIG_BOOTP_GATEWAY
38 #define CONFIG_BOOTP_HOSTNAME
40 /* Command line configuration */
41 #include <config_cmd_default.h>
43 #define CONFIG_CMD_BOOTD
44 #define CONFIG_CMD_CACHE
45 #undef CONFIG_CMD_DATE
46 #define CONFIG_CMD_DHCP
47 #define CONFIG_CMD_ELF
48 #undef CONFIG_CMD_FLASH
50 #undef CONFIG_CMD_JFFS2
52 #define CONFIG_CMD_MEMORY
53 #define CONFIG_CMD_MISC
54 #define CONFIG_CMD_MII
55 #undef CONFIG_CMD_NAND
56 #undef CONFIG_CMD_NAND_YAFFS
57 #define CONFIG_CMD_NET
58 #define CONFIG_CMD_NFS
59 #define CONFIG_CMD_PING
60 #define CONFIG_CMD_REGINFO
61 #define CONFIG_CMD_SPI
63 #undef CONFIG_CMD_IMLS
65 #undef CONFIG_CMD_LOADB
66 #undef CONFIG_CMD_LOADS
71 #ifdef CONFIG_CMD_NAND
72 #define CONFIG_JFFS2_NAND
73 #define CONFIG_NAND_FSL_NFC
74 #define CONFIG_SYS_NAND_BASE 0xFC0FC000
75 #define CONFIG_SYS_MAX_NAND_DEVICE 1
76 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
77 #define CONFIG_SYS_NAND_SELECT_DEVICE
80 /* Network configuration */
83 #define CONFIG_NET_MULTI 1
85 #define CONFIG_MII_INIT 1
86 #define CONFIG_SYS_DISCOVER_PHY
87 #define CONFIG_SYS_RX_ETH_BUFFER 2
88 #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
89 #define CONFIG_SYS_TX_ETH_BUFFER 2
90 #define CONFIG_HAS_ETH1
92 #define CONFIG_SYS_FEC0_PINMUX 0
93 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
94 #define CONFIG_SYS_FEC1_PINMUX 0
95 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
96 #define MCFFEC_TOUT_LOOP 50000
97 #define CONFIG_SYS_FEC0_PHYADDR 0
98 #define CONFIG_SYS_FEC1_PHYADDR 1
100 #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
102 #ifdef CONFIG_SYS_NAND_BOOT
103 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
104 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
105 "-(jffs2) console=ttyS0,115200"
107 #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \
108 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
109 __stringify(CONFIG_IPADDR) " ip=" \
110 __stringify(CONFIG_IPADDR) ":" \
111 __stringify(CONFIG_SERVERIP)":" \
112 __stringify(CONFIG_GATEWAYIP)": " \
113 __stringify(CONFIG_NETMASK) \
114 "::eth0:off:rw console=ttyS0,115200"
117 #define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
118 #define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
119 #define CONFIG_ETHPRIME "FEC0"
120 #define CONFIG_IPADDR 192.168.1.2
121 #define CONFIG_NETMASK 255.255.255.0
122 #define CONFIG_SERVERIP 192.168.1.1
123 #define CONFIG_GATEWAYIP 192.168.1.1
125 #define CONFIG_OVERWRITE_ETHADDR_ONCE
126 #define CONFIG_SYS_FEC_BUF_USE_SRAM
127 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
128 #ifndef CONFIG_SYS_DISCOVER_PHY
129 #define FECDUPLEX FULL
130 #define FECSPEED _100BASET
134 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
135 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
137 #endif /* CONFIG_SYS_DISCOVER_PHY */
140 #define CONFIG_HOSTNAME M54418TWR
142 #if defined(CONFIG_CF_SBF)
143 /* ST Micro serial flash */
144 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
145 #define CONFIG_EXTRA_ENV_SETTINGS \
147 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
148 "loadaddr=0x40010000\0" \
149 "sbfhdr=sbfhdr.bin\0" \
150 "uboot=u-boot.bin\0" \
151 "load=tftp ${loadaddr} ${sbfhdr};" \
152 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
153 "upd=run load; run prog\0" \
154 "prog=sf probe 0:1 1000000 3;" \
155 "sf erase 0 40000;" \
156 "sf write ${loadaddr} 0 40000;" \
159 #elif defined(CONFIG_SYS_NAND_BOOT)
160 #define CONFIG_EXTRA_ENV_SETTINGS \
162 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
163 "loadaddr=0x40010000\0" \
164 "u-boot=u-boot.bin\0" \
165 "load=tftp ${loadaddr} ${u-boot};\0" \
166 "upd=run load; run prog\0" \
167 "prog=nand device 0;" \
168 "nand erase 0 40000;" \
169 "nb_update ${loadaddr} ${filesize};" \
173 #define CONFIG_SYS_UBOOT_END 0x3FFFF
174 #define CONFIG_EXTRA_ENV_SETTINGS \
176 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
177 "loadaddr=40010000\0" \
178 "u-boot=u-boot.bin\0" \
179 "load=tftp ${loadaddr) ${u-boot}\0" \
180 "upd=run load; run prog\0" \
181 "prog=prot off mram" " ;" \
182 "cp.b ${loadaddr} 0 ${filesize};" \
189 #define CONFIG_RTC_MCFRRTC
190 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
193 #define CONFIG_MCFTMR
197 #undef CONFIG_SYS_FSL_I2C
198 #undef CONFIG_HARD_I2C /* I2C with hardware support */
199 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
200 /* I2C speed and slave address */
201 #define CONFIG_SYS_I2C_SPEED 80000
202 #define CONFIG_SYS_I2C_SLAVE 0x7F
203 #define CONFIG_SYS_I2C_OFFSET 0x58000
204 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
206 /* DSPI and Serial Flash */
207 #define CONFIG_CF_SPI
208 #define CONFIG_CF_DSPI
209 #define CONFIG_SERIAL_FLASH
210 #define CONFIG_HARD_SPI
211 #define CONFIG_SYS_SBFHDR_SIZE 0x7
212 #ifdef CONFIG_CMD_SPI
213 # define CONFIG_SPI_FLASH
214 # define CONFIG_SPI_FLASH_ATMEL
216 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
217 DSPI_CTAR_PCSSCK_1CLK | \
218 DSPI_CTAR_PASC(0) | \
220 DSPI_CTAR_CSSCK(0) | \
223 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
224 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
227 /* Input, PCI, Flexbus, and VCO */
228 #define CONFIG_EXTRA_CLOCK
230 #define CONFIG_PRAM 2048 /* 2048 KB */
233 #define CONFIG_SYS_HUSH_PARSER 1
234 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
236 #define CONFIG_SYS_PROMPT "-> "
237 #define CONFIG_SYS_LONGHELP /* undef to save memory */
239 #if defined(CONFIG_CMD_KGDB)
240 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
242 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
244 /* Print Buffer Size */
245 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
246 sizeof(CONFIG_SYS_PROMPT) + 16)
247 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
248 /* Boot Argument Buffer Size */
249 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
251 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
253 #define CONFIG_SYS_MBAR 0xFC000000
256 * Low Level Configuration Settings
257 * (address mappings, register initial values, etc.)
258 * You should know what you are doing if you make changes here.
261 /*-----------------------------------------------------------------------
262 * Definitions for initial stack pointer and data area (in DPRAM)
264 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
265 /* End of used area in internal SRAM */
266 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
267 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
268 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
269 GENERATED_GBL_DATA_SIZE) - 32)
270 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
271 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
273 /*-----------------------------------------------------------------------
274 * Start addresses for the final memory configuration
275 * (Set up by the startup code)
276 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
278 #define CONFIG_SYS_SDRAM_BASE 0x40000000
279 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
281 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
282 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
283 #define CONFIG_SYS_DRAM_TEST
285 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
286 #define CONFIG_SERIAL_BOOT
289 #if defined(CONFIG_SERIAL_BOOT)
290 #define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
292 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
295 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
296 /* Reserve 256 kB for Monitor */
297 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
298 /* Reserve 256 kB for malloc() */
299 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
302 * For booting Linux, the board info and command line data
303 * have to be in the first 8 MB of memory, since this is
304 * the maximum mapped by the Linux kernel during initialization ??
306 /* Initial Memory map for Linux */
307 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
308 (CONFIG_SYS_SDRAM_SIZE << 20))
310 /* Configuration for environment
311 * Environment is embedded in u-boot in the second sector of the flash
313 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
314 #define CONFIG_SYS_NO_FLASH
315 #define CONFIG_ENV_IS_IN_MRAM 1
316 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
317 #define CONFIG_ENV_SIZE 0x1000
320 #if defined(CONFIG_CF_SBF)
321 #define CONFIG_SYS_NO_FLASH
322 #define CONFIG_ENV_IS_IN_SPI_FLASH 1
323 #define CONFIG_ENV_SPI_CS 1
324 #define CONFIG_ENV_OFFSET 0x40000
325 #define CONFIG_ENV_SIZE 0x2000
326 #define CONFIG_ENV_SECT_SIZE 0x10000
328 #if defined(CONFIG_SYS_NAND_BOOT)
329 #define CONFIG_SYS_NO_FLASH
330 #define CONFIG_ENV_IS_NOWHERE
331 #define CONFIG_ENV_OFFSET 0x80000
332 #define CONFIG_ENV_SIZE 0x20000
333 #define CONFIG_ENV_SECT_SIZE 0x20000
335 #undef CONFIG_ENV_OVERWRITE
337 /* FLASH organization */
338 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
340 #undef CONFIG_SYS_FLASH_CFI
341 #ifdef CONFIG_SYS_FLASH_CFI
343 #define CONFIG_FLASH_CFI_DRIVER 1
344 /* Max size that the board might have */
345 #define CONFIG_SYS_FLASH_SIZE 0x1000000
346 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
347 /* max number of memory banks */
348 #define CONFIG_SYS_MAX_FLASH_BANKS 1
349 /* max number of sectors on one chip */
350 #define CONFIG_SYS_MAX_FLASH_SECT 270
351 /* "Real" (hardware) sectors protection */
352 #define CONFIG_SYS_FLASH_PROTECTION
353 #define CONFIG_SYS_FLASH_CHECKSUM
354 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
356 /* max number of sectors on one chip */
357 #define CONFIG_SYS_MAX_FLASH_SECT 270
358 /* max number of sectors on one chip */
359 #define CONFIG_SYS_MAX_FLASH_BANKS 0
363 * This is setting for JFFS2 support in u-boot.
364 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
366 #ifdef CONFIG_CMD_JFFS2
367 #define CONFIG_JFFS2_DEV "nand0"
368 #define CONFIG_JFFS2_PART_OFFSET (0x800000)
369 #define CONFIG_CMD_MTDPARTS
370 #define CONFIG_MTD_DEVICE
371 #define MTDIDS_DEFAULT "nand0=m54418twr.nand"
373 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
379 #ifdef CONFIG_CMD_UBI
380 #define CONFIG_CMD_MTDPARTS
381 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */
382 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
383 #define CONFIG_RBTREE
384 #define MTDIDS_DEFAULT "nand0=NAND"
385 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
388 /* Cache Configuration */
389 #define CONFIG_SYS_CACHELINE_SIZE 16
390 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
391 CONFIG_SYS_INIT_RAM_SIZE - 8)
392 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
393 CONFIG_SYS_INIT_RAM_SIZE - 4)
394 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
395 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
396 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
397 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
398 CF_ACR_EN | CF_ACR_SM_ALL)
399 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
400 CF_CACR_ICINVA | CF_CACR_EUSP)
401 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
402 CF_CACR_DEC | CF_CACR_DDCM_P | \
403 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
405 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
406 CONFIG_SYS_INIT_RAM_SIZE - 12)
408 /*-----------------------------------------------------------------------
409 * Memory bank definitions
412 * CS0 - NOR Flash 16MB
421 #define CONFIG_SYS_CS0_BASE 0x00000000
422 #define CONFIG_SYS_CS0_MASK 0x000F0101
423 #define CONFIG_SYS_CS0_CTRL 0x00001D60
425 #endif /* _M54418TWR_H */