2 * Configuation settings for the Freescale MCF54418 TWR board.
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
11 * board/config.h - configuration options, board specific
18 * High Level Configuration Options
21 #define CONFIG_M54418TWR /* M54418TWR board */
23 #define CONFIG_MCFUART
24 #define CONFIG_SYS_UART_PORT (0)
25 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
27 #define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
29 #undef CONFIG_WATCHDOG
31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
36 #define CONFIG_BOOTP_BOOTFILESIZE
37 #define CONFIG_BOOTP_BOOTPATH
38 #define CONFIG_BOOTP_GATEWAY
39 #define CONFIG_BOOTP_HOSTNAME
44 #ifdef CONFIG_CMD_NAND
45 #define CONFIG_JFFS2_NAND
46 #define CONFIG_NAND_FSL_NFC
47 #define CONFIG_SYS_NAND_BASE 0xFC0FC000
48 #define CONFIG_SYS_MAX_NAND_DEVICE 1
49 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
50 #define CONFIG_SYS_NAND_SELECT_DEVICE
53 /* Network configuration */
57 #define CONFIG_MII_INIT 1
58 #define CONFIG_SYS_DISCOVER_PHY
59 #define CONFIG_SYS_RX_ETH_BUFFER 2
60 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
61 #define CONFIG_SYS_TX_ETH_BUFFER 2
62 #define CONFIG_HAS_ETH1
64 #define CONFIG_SYS_FEC0_PINMUX 0
65 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
66 #define CONFIG_SYS_FEC1_PINMUX 0
67 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
68 #define MCFFEC_TOUT_LOOP 50000
69 #define CONFIG_SYS_FEC0_PHYADDR 0
70 #define CONFIG_SYS_FEC1_PHYADDR 1
72 #define CONFIG_ETHPRIME "FEC0"
73 #define CONFIG_IPADDR 192.168.1.2
74 #define CONFIG_NETMASK 255.255.255.0
75 #define CONFIG_SERVERIP 192.168.1.1
76 #define CONFIG_GATEWAYIP 192.168.1.1
78 #define CONFIG_SYS_FEC_BUF_USE_SRAM
79 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
80 #ifndef CONFIG_SYS_DISCOVER_PHY
81 #define FECDUPLEX FULL
82 #define FECSPEED _100BASET
86 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
87 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
89 #endif /* CONFIG_SYS_DISCOVER_PHY */
92 #define CONFIG_HOSTNAME M54418TWR
94 #if defined(CONFIG_CF_SBF)
95 /* ST Micro serial flash */
96 #define CONFIG_SYS_LOAD_ADDR2 0x40010007
97 #define CONFIG_EXTRA_ENV_SETTINGS \
99 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
100 "loadaddr=0x40010000\0" \
101 "sbfhdr=sbfhdr.bin\0" \
102 "uboot=u-boot.bin\0" \
103 "load=tftp ${loadaddr} ${sbfhdr};" \
104 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
105 "upd=run load; run prog\0" \
106 "prog=sf probe 0:1 1000000 3;" \
107 "sf erase 0 40000;" \
108 "sf write ${loadaddr} 0 40000;" \
111 #elif defined(CONFIG_SYS_NAND_BOOT)
112 #define CONFIG_EXTRA_ENV_SETTINGS \
114 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
115 "loadaddr=0x40010000\0" \
116 "u-boot=u-boot.bin\0" \
117 "load=tftp ${loadaddr} ${u-boot};\0" \
118 "upd=run load; run prog\0" \
119 "prog=nand device 0;" \
120 "nand erase 0 40000;" \
121 "nb_update ${loadaddr} ${filesize};" \
125 #define CONFIG_SYS_UBOOT_END 0x3FFFF
126 #define CONFIG_EXTRA_ENV_SETTINGS \
128 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
129 "loadaddr=40010000\0" \
130 "u-boot=u-boot.bin\0" \
131 "load=tftp ${loadaddr) ${u-boot}\0" \
132 "upd=run load; run prog\0" \
133 "prog=prot off mram" " ;" \
134 "cp.b ${loadaddr} 0 ${filesize};" \
141 #define CONFIG_RTC_MCFRRTC
142 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
145 #define CONFIG_MCFTMR
149 #undef CONFIG_SYS_FSL_I2C
150 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
151 /* I2C speed and slave address */
152 #define CONFIG_SYS_I2C_SPEED 80000
153 #define CONFIG_SYS_I2C_SLAVE 0x7F
154 #define CONFIG_SYS_I2C_OFFSET 0x58000
155 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
157 /* DSPI and Serial Flash */
158 #define CONFIG_CF_SPI
159 #define CONFIG_CF_DSPI
160 #define CONFIG_SERIAL_FLASH
161 #define CONFIG_HARD_SPI
162 #define CONFIG_SYS_SBFHDR_SIZE 0x7
163 #ifdef CONFIG_CMD_SPI
165 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
166 DSPI_CTAR_PCSSCK_1CLK | \
167 DSPI_CTAR_PASC(0) | \
169 DSPI_CTAR_CSSCK(0) | \
172 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
173 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
176 /* Input, PCI, Flexbus, and VCO */
177 #define CONFIG_EXTRA_CLOCK
179 #define CONFIG_PRAM 2048 /* 2048 KB */
181 #define CONFIG_SYS_LONGHELP /* undef to save memory */
183 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
184 /* Boot Argument Buffer Size */
185 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
187 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
189 #define CONFIG_SYS_MBAR 0xFC000000
192 * Low Level Configuration Settings
193 * (address mappings, register initial values, etc.)
194 * You should know what you are doing if you make changes here.
197 /*-----------------------------------------------------------------------
198 * Definitions for initial stack pointer and data area (in DPRAM)
200 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
201 /* End of used area in internal SRAM */
202 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
203 #define CONFIG_SYS_INIT_RAM_CTRL 0x221
204 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
205 GENERATED_GBL_DATA_SIZE) - 32)
206 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
207 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
209 /*-----------------------------------------------------------------------
210 * Start addresses for the final memory configuration
211 * (Set up by the startup code)
212 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
214 #define CONFIG_SYS_SDRAM_BASE 0x40000000
215 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
217 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
218 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
219 #define CONFIG_SYS_DRAM_TEST
221 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
222 #define CONFIG_SERIAL_BOOT
225 #if defined(CONFIG_SERIAL_BOOT)
226 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
228 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
231 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
232 /* Reserve 256 kB for Monitor */
233 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
234 /* Reserve 256 kB for malloc() */
235 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
238 * For booting Linux, the board info and command line data
239 * have to be in the first 8 MB of memory, since this is
240 * the maximum mapped by the Linux kernel during initialization ??
242 /* Initial Memory map for Linux */
243 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
244 (CONFIG_SYS_SDRAM_SIZE << 20))
246 /* Configuration for environment
247 * Environment is embedded in u-boot in the second sector of the flash
249 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
250 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
251 #define CONFIG_ENV_SIZE 0x1000
254 #if defined(CONFIG_CF_SBF)
255 #define CONFIG_ENV_SPI_CS 1
256 #define CONFIG_ENV_OFFSET 0x40000
257 #define CONFIG_ENV_SIZE 0x2000
258 #define CONFIG_ENV_SECT_SIZE 0x10000
260 #if defined(CONFIG_SYS_NAND_BOOT)
261 #define CONFIG_ENV_OFFSET 0x80000
262 #define CONFIG_ENV_SIZE 0x20000
263 #define CONFIG_ENV_SECT_SIZE 0x20000
265 #undef CONFIG_ENV_OVERWRITE
267 /* FLASH organization */
268 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
270 #undef CONFIG_SYS_FLASH_CFI
271 #ifdef CONFIG_SYS_FLASH_CFI
273 #define CONFIG_FLASH_CFI_DRIVER 1
274 /* Max size that the board might have */
275 #define CONFIG_SYS_FLASH_SIZE 0x1000000
276 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
277 /* max number of memory banks */
278 #define CONFIG_SYS_MAX_FLASH_BANKS 1
279 /* max number of sectors on one chip */
280 #define CONFIG_SYS_MAX_FLASH_SECT 270
281 /* "Real" (hardware) sectors protection */
282 #define CONFIG_SYS_FLASH_PROTECTION
283 #define CONFIG_SYS_FLASH_CHECKSUM
284 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
286 /* max number of sectors on one chip */
287 #define CONFIG_SYS_MAX_FLASH_SECT 270
288 /* max number of sectors on one chip */
289 #define CONFIG_SYS_MAX_FLASH_BANKS 0
293 * This is setting for JFFS2 support in u-boot.
294 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
296 #ifdef CONFIG_CMD_JFFS2
297 #define CONFIG_JFFS2_DEV "nand0"
298 #define CONFIG_JFFS2_PART_OFFSET (0x800000)
299 #define CONFIG_MTD_DEVICE
300 #define MTDIDS_DEFAULT "nand0=m54418twr.nand"
302 #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
308 #ifdef CONFIG_CMD_UBI
309 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */
310 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
311 #define MTDIDS_DEFAULT "nand0=NAND"
312 #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
315 /* Cache Configuration */
316 #define CONFIG_SYS_CACHELINE_SIZE 16
317 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
318 CONFIG_SYS_INIT_RAM_SIZE - 8)
319 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
320 CONFIG_SYS_INIT_RAM_SIZE - 4)
321 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
322 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
323 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
324 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
325 CF_ACR_EN | CF_ACR_SM_ALL)
326 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
327 CF_CACR_ICINVA | CF_CACR_EUSP)
328 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
329 CF_CACR_DEC | CF_CACR_DDCM_P | \
330 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
332 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
333 CONFIG_SYS_INIT_RAM_SIZE - 12)
335 /*-----------------------------------------------------------------------
336 * Memory bank definitions
339 * CS0 - NOR Flash 16MB
348 #define CONFIG_SYS_CS0_BASE 0x00000000
349 #define CONFIG_SYS_CS0_MASK 0x000F0101
350 #define CONFIG_SYS_CS0_CTRL 0x00001D60
352 #endif /* _M54418TWR_H */