include/configs/M5275EVB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Configuation settings for the Motorola MC5275EVB board.
   4  *
   5  * By Arthur Shipkowski <art@videon-central.com>
   6  * Copyright (C) 2005 Videon Central, Inc.
   7  *
   8  * Based off of M5272C3 board code by Josef Baumgartner
   9  * <josef.baumgartner@telex.de>
  10  */
  11
  12 /*
  13  * board/config.h - configuration options, board specific
  14  */
  15
  16 #ifndef _M5275EVB_H
  17 #define _M5275EVB_H
  18
  19 /*
  20  * High Level Configuration Options
  21  * (easy to change)
  22  */
  23
  24 #define CONFIG_MCFTMR
  25
  26 #define CONFIG_MCFUART
  27 #define CONFIG_SYS_UART_PORT            (0)
  28
  29 /* Configuration for environment
  30  * Environment is embedded in u-boot in the second sector of the flash
  31  */
  32
  33 #define LDS_BOARD_TEXT \
  34         . = DEFINED(env_offset) ? env_offset : .; \
  35         env/embedded.o(.text);
  36
  37 /*
  38  * BOOTP options
  39  */
  40 #define CONFIG_BOOTP_BOOTFILESIZE
  41
  42 /* Available command configuration */
  43
  44 #define CONFIG_MCFFEC
  45 #ifdef CONFIG_MCFFEC
  46 #define CONFIG_MII_INIT         1
  47 #define CONFIG_SYS_DISCOVER_PHY
  48 #define CONFIG_SYS_RX_ETH_BUFFER        8
  49 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  50 #define CONFIG_SYS_FEC0_PINMUX          0
  51 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  52 #define CONFIG_SYS_FEC1_PINMUX          0
  53 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
  54 #define MCFFEC_TOUT_LOOP        50000
  55 #define CONFIG_HAS_ETH1
  56 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  57 #ifndef CONFIG_SYS_DISCOVER_PHY
  58 #define FECDUPLEX               FULL
  59 #define FECSPEED                _100BASET
  60 #else
  61 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  62 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  63 #endif
  64 #endif
  65 #endif
  66
  67 /* I2C */
  68 #define CONFIG_SYS_I2C
  69 #define CONFIG_SYS_I2C_FSL
  70 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  71 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  72 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
  73 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  74 #define CONFIG_SYS_I2C_PINMUX_REG       (gpio_reg->par_feci2c)
  75 #define CONFIG_SYS_I2C_PINMUX_CLR       (0xFFF0)
  76 #define CONFIG_SYS_I2C_PINMUX_SET       (0x000F)
  77
  78 #define CONFIG_SYS_LOAD_ADDR            0x800000
  79
  80 #define CONFIG_BOOTCOMMAND      "bootm ffe40000"
  81 #define CONFIG_SYS_MEMTEST_START        0x400
  82 #define CONFIG_SYS_MEMTEST_END          0x380000
  83
  84 #ifdef CONFIG_MCFFEC
  85 #       define CONFIG_NET_RETRY_COUNT   5
  86 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  87 #endif                          /* FEC_ENET */
  88
  89 #define CONFIG_EXTRA_ENV_SETTINGS               \
  90         "netdev=eth0\0"                         \
  91         "loadaddr=10000\0"                      \
  92         "uboot=u-boot.bin\0"                    \
  93         "load=tftp ${loadaddr} ${uboot}\0"      \
  94         "upd=run load; run prog\0"              \
  95         "prog=prot off ffe00000 ffe3ffff;"      \
  96         "era ffe00000 ffe3ffff;"                \
  97         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  98         "save\0"                                \
  99         ""
 100
 101 #define CONFIG_SYS_CLK                  150000000
 102
 103 /*
 104  * Low Level Configuration Settings
 105  * (address mappings, register initial values, etc.)
 106  * You should know what you are doing if you make changes here.
 107  */
 108
 109 #define CONFIG_SYS_MBAR         0x40000000
 110
 111 /*-----------------------------------------------------------------------
 112  * Definitions for initial stack pointer and data area (in DPRAM)
 113  */
 114 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 115 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 116 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 117 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 118
 119 /*-----------------------------------------------------------------------
 120  * Start addresses for the final memory configuration
 121  * (Set up by the startup code)
 122  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 123  */
 124 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 125 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 126 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 127
 128 #ifdef CONFIG_MONITOR_IS_IN_RAM
 129 #define CONFIG_SYS_MONITOR_BASE 0x20000
 130 #else
 131 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 132 #endif
 133
 134 #define CONFIG_SYS_MONITOR_LEN          0x20000
 135 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 136 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 137
 138 /*
 139  * For booting Linux, the board info and command line data
 140  * have to be in the first 8 MB of memory, since this is
 141  * the maximum mapped by the Linux kernel during initialization ??
 142  */
 143 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 144 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 145
 146 /*-----------------------------------------------------------------------
 147  * FLASH organization
 148  */
 149 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 150 #define CONFIG_SYS_MAX_FLASH_SECT       11      /* max number of sectors on one chip */
 151 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 152
 153 #define CONFIG_SYS_FLASH_SIZE           0x200000
 154
 155 /*-----------------------------------------------------------------------
 156  * Cache Configuration
 157  */
 158 #define CONFIG_SYS_CACHELINE_SIZE       16
 159
 160 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 161                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 162 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 163                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 164 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 165 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 166                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 167                                          CF_ACR_EN | CF_ACR_SM_ALL)
 168 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 169                                          CF_CACR_DISD | CF_CACR_INVI | \
 170                                          CF_CACR_CEIB | CF_CACR_DCM | \
 171                                          CF_CACR_EUSP)
 172
 173 /*-----------------------------------------------------------------------
 174  * Memory bank definitions
 175  */
 176 #define CONFIG_SYS_CS0_BASE             0xffe00000
 177 #define CONFIG_SYS_CS0_CTRL             0x00001980
 178 #define CONFIG_SYS_CS0_MASK             0x001F0001
 179
 180 #define CONFIG_SYS_CS1_BASE             0x30000000
 181 #define CONFIG_SYS_CS1_CTRL             0x00001900
 182 #define CONFIG_SYS_CS1_MASK             0x00070001
 183
 184 /*-----------------------------------------------------------------------
 185  * Port configuration
 186  */
 187 #define CONFIG_SYS_FECI2C               0x0FA0
 188
 189 #endif  /* _M5275EVB_H */