2 * Configuation settings for the Motorola MC5272C3 board.
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
6 * SPDX-License-Identifier: GPL-2.0+
10 * board/config.h - configuration options, board specific
17 * High Level Configuration Options
22 #define CONFIG_MCFUART
23 #define CONFIG_SYS_UART_PORT (0)
25 #undef CONFIG_WATCHDOG
26 #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
28 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
30 /* Configuration for environment
31 * Environment is embedded in u-boot in the second sector of the flash
33 #ifndef CONFIG_MONITOR_IS_IN_RAM
34 #define CONFIG_ENV_OFFSET 0x4000
35 #define CONFIG_ENV_SECT_SIZE 0x2000
37 #define CONFIG_ENV_ADDR 0xffe04000
38 #define CONFIG_ENV_SECT_SIZE 0x2000
41 #define LDS_BOARD_TEXT \
42 . = DEFINED(env_offset) ? env_offset : .; \
43 env/embedded.o(.text);
48 #define CONFIG_BOOTP_BOOTFILESIZE
49 #define CONFIG_BOOTP_BOOTPATH
50 #define CONFIG_BOOTP_GATEWAY
51 #define CONFIG_BOOTP_HOSTNAME
54 * Command line configuration.
60 # define CONFIG_MII_INIT 1
61 # define CONFIG_SYS_DISCOVER_PHY
62 # define CONFIG_SYS_RX_ETH_BUFFER 8
63 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
65 # define CONFIG_SYS_FEC0_PINMUX 0
66 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
67 # define MCFFEC_TOUT_LOOP 50000
68 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
69 # ifndef CONFIG_SYS_DISCOVER_PHY
70 # define FECDUPLEX FULL
71 # define FECSPEED _100BASET
73 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
74 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
76 # endif /* CONFIG_SYS_DISCOVER_PHY */
80 # define CONFIG_IPADDR 192.162.1.2
81 # define CONFIG_NETMASK 255.255.255.0
82 # define CONFIG_SERVERIP 192.162.1.1
83 # define CONFIG_GATEWAYIP 192.162.1.1
84 #endif /* CONFIG_MCFFEC */
86 #define CONFIG_HOSTNAME M5272C3
87 #define CONFIG_EXTRA_ENV_SETTINGS \
90 "u-boot=u-boot.bin\0" \
91 "load=tftp ${loadaddr) ${u-boot}\0" \
92 "upd=run load; run prog\0" \
93 "prog=prot off ffe00000 ffe3ffff;" \
94 "era ffe00000 ffe3ffff;" \
95 "cp.b ${loadaddr} ffe00000 ${filesize};"\
99 #define CONFIG_SYS_LONGHELP /* undef to save memory */
101 #define CONFIG_SYS_LOAD_ADDR 0x20000
102 #define CONFIG_SYS_MEMTEST_START 0x400
103 #define CONFIG_SYS_MEMTEST_END 0x380000
104 #define CONFIG_SYS_CLK 66000000
107 * Low Level Configuration Settings
108 * (address mappings, register initial values, etc.)
109 * You should know what you are doing if you make changes here.
111 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
112 #define CONFIG_SYS_SCR 0x0003
113 #define CONFIG_SYS_SPR 0xffff
115 /*-----------------------------------------------------------------------
116 * Definitions for initial stack pointer and data area (in DPRAM)
118 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
119 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
120 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
121 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
123 /*-----------------------------------------------------------------------
124 * Start addresses for the final memory configuration
125 * (Set up by the startup code)
126 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
128 #define CONFIG_SYS_SDRAM_BASE 0x00000000
129 #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
130 #define CONFIG_SYS_FLASH_BASE 0xffe00000
132 #ifdef CONFIG_MONITOR_IS_IN_RAM
133 #define CONFIG_SYS_MONITOR_BASE 0x20000
135 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
138 #define CONFIG_SYS_MONITOR_LEN 0x20000
139 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
140 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
143 * For booting Linux, the board info and command line data
144 * have to be in the first 8 MB of memory, since this is
145 * the maximum mapped by the Linux kernel during initialization ??
147 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
152 #define CONFIG_SYS_FLASH_CFI
153 #ifdef CONFIG_SYS_FLASH_CFI
154 # define CONFIG_FLASH_CFI_DRIVER 1
155 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
156 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
157 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
158 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
159 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
162 /*-----------------------------------------------------------------------
163 * Cache Configuration
165 #define CONFIG_SYS_CACHELINE_SIZE 16
167 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
168 CONFIG_SYS_INIT_RAM_SIZE - 8)
169 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
170 CONFIG_SYS_INIT_RAM_SIZE - 4)
171 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
172 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
173 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
174 CF_ACR_EN | CF_ACR_SM_ALL)
175 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
176 CF_CACR_DISD | CF_CACR_INVI | \
177 CF_CACR_CEIB | CF_CACR_DCM | \
180 /*-----------------------------------------------------------------------
181 * Memory bank definitions
183 #define CONFIG_SYS_BR0_PRELIM 0xFFE00201
184 #define CONFIG_SYS_OR0_PRELIM 0xFFE00014
185 #define CONFIG_SYS_BR1_PRELIM 0
186 #define CONFIG_SYS_OR1_PRELIM 0
187 #define CONFIG_SYS_BR2_PRELIM 0x30000001
188 #define CONFIG_SYS_OR2_PRELIM 0xFFF80000
189 #define CONFIG_SYS_BR3_PRELIM 0
190 #define CONFIG_SYS_OR3_PRELIM 0
191 #define CONFIG_SYS_BR4_PRELIM 0
192 #define CONFIG_SYS_OR4_PRELIM 0
193 #define CONFIG_SYS_BR5_PRELIM 0
194 #define CONFIG_SYS_OR5_PRELIM 0
195 #define CONFIG_SYS_BR6_PRELIM 0
196 #define CONFIG_SYS_OR6_PRELIM 0
197 #define CONFIG_SYS_BR7_PRELIM 0x00000701
198 #define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
200 /*-----------------------------------------------------------------------
203 #define CONFIG_SYS_PACNT 0x00000000
204 #define CONFIG_SYS_PADDR 0x0000
205 #define CONFIG_SYS_PADAT 0x0000
206 #define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
207 #define CONFIG_SYS_PBDDR 0x0000
208 #define CONFIG_SYS_PBDAT 0x0000
209 #define CONFIG_SYS_PDCNT 0x00000000
210 #endif /* _M5272C3_H */