1 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
2 * Hayden Fraser (Hayden.Fraser@freescale.com)
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_M5253DEMO /* define board type */
14 #define CONFIG_MCFUART
15 #define CONFIG_SYS_UART_PORT (0)
16 #define CONFIG_BAUDRATE 115200
18 #undef CONFIG_WATCHDOG /* disable watchdog */
20 #define CONFIG_BOOTDELAY 5
22 /* Configuration for environment
23 * Environment is embedded in u-boot in the second sector of the flash
25 #ifdef CONFIG_MONITOR_IS_IN_RAM
26 # define CONFIG_ENV_OFFSET 0x4000
27 # define CONFIG_ENV_SECT_SIZE 0x1000
28 # define CONFIG_ENV_IS_IN_FLASH 1
30 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
31 # define CONFIG_ENV_SECT_SIZE 0x1000
32 # define CONFIG_ENV_IS_IN_FLASH 1
35 #define LDS_BOARD_TEXT \
36 . = DEFINED(env_offset) ? env_offset : .; \
37 common/env_embedded.o (.text*);
40 * Command line configuration.
42 #define CONFIG_CMD_IDE
46 # define CONFIG_DOS_PARTITION
47 # define CONFIG_MAC_PARTITION
48 # define CONFIG_IDE_RESET 1
49 # define CONFIG_IDE_PREINIT 1
53 # define CONFIG_SYS_IDE_MAXBUS 1
54 # define CONFIG_SYS_IDE_MAXDEVICE 2
56 # define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
57 # define CONFIG_SYS_ATA_IDE0_OFFSET 0
59 # define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
60 # define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
61 # define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
62 # define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
65 #define CONFIG_DRIVER_DM9000
66 #ifdef CONFIG_DRIVER_DM9000
67 # define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
68 # define DM9000_IO CONFIG_DM9000_BASE
69 # define DM9000_DATA (CONFIG_DM9000_BASE + 4)
70 # undef CONFIG_DM9000_DEBUG
71 # define CONFIG_DM9000_BYTE_SWAPPED
73 # define CONFIG_OVERWRITE_ETHADDR_ONCE
75 # define CONFIG_EXTRA_ENV_SETTINGS \
77 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
79 "u-boot=u-boot.bin\0" \
80 "load=tftp ${loadaddr) ${u-boot}\0" \
81 "upd=run load; run prog\0" \
82 "prog=prot off 0xff800000 0xff82ffff;" \
83 "era 0xff800000 0xff82ffff;" \
84 "cp.b ${loadaddr} 0xff800000 ${filesize};" \
89 #define CONFIG_HOSTNAME M5253DEMO
92 #define CONFIG_SYS_I2C
93 #define CONFIG_SYS_I2C_FSL
94 #define CONFIG_SYS_FSL_I2C_SPEED 80000
95 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
96 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
97 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
98 #define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
99 #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
100 #define CONFIG_SYS_I2C_PINMUX_SET (0)
102 #define CONFIG_SYS_LONGHELP /* undef to save memory */
104 #if defined(CONFIG_CMD_KGDB)
105 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
107 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
110 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
111 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
113 #define CONFIG_SYS_LOAD_ADDR 0x00100000
115 #define CONFIG_SYS_MEMTEST_START 0x400
116 #define CONFIG_SYS_MEMTEST_END 0x380000
118 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
119 #define CONFIG_SYS_FAST_CLK
120 #ifdef CONFIG_SYS_FAST_CLK
121 # define CONFIG_SYS_PLLCR 0x1243E054
122 # define CONFIG_SYS_CLK 140000000
124 # define CONFIG_SYS_PLLCR 0x135a4140
125 # define CONFIG_SYS_CLK 70000000
129 * Low Level Configuration Settings
130 * (address mappings, register initial values, etc.)
131 * You should know what you are doing if you make changes here.
134 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
135 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
138 * Definitions for initial stack pointer and data area (in DPRAM)
140 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
141 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
142 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
143 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
146 * Start addresses for the final memory configuration
147 * (Set up by the startup code)
148 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
150 #define CONFIG_SYS_SDRAM_BASE 0x00000000
151 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
153 #ifdef CONFIG_MONITOR_IS_IN_RAM
154 # define CONFIG_SYS_MONITOR_BASE 0x20000
156 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
159 #define CONFIG_SYS_MONITOR_LEN 0x40000
160 #define CONFIG_SYS_MALLOC_LEN (256 << 10)
161 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
164 * For booting Linux, the board info and command line data
165 * have to be in the first 8 MB of memory, since this is
166 * the maximum mapped by the Linux kernel during initialization ??
168 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
169 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
171 /* FLASH organization */
172 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
173 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
174 #define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
175 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
177 #define FLASH_SST6401B 0x200
178 #define SST_ID_xF6401B 0x236D236D
180 #undef CONFIG_SYS_FLASH_CFI
181 #ifdef CONFIG_SYS_FLASH_CFI
183 * Unable to use CFI driver, due to incompatible sector erase command by SST.
184 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
185 * 0x30 is block erase in SST
187 # define CONFIG_FLASH_CFI_DRIVER 1
188 # define CONFIG_SYS_FLASH_SIZE 0x800000
189 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
190 # define CONFIG_FLASH_CFI_LEGACY
192 # define CONFIG_SYS_SST_SECT 2048
193 # define CONFIG_SYS_SST_SECTSZ 0x1000
194 # define CONFIG_SYS_FLASH_WRITE_TOUT 500
197 /* Cache Configuration */
198 #define CONFIG_SYS_CACHELINE_SIZE 16
200 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
201 CONFIG_SYS_INIT_RAM_SIZE - 8)
202 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
203 CONFIG_SYS_INIT_RAM_SIZE - 4)
204 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
205 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
207 CF_ACR_EN | CF_ACR_SM_ALL)
208 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
209 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
210 CF_ACR_EN | CF_ACR_SM_ALL)
211 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
214 /* Port configuration */
215 #define CONFIG_SYS_FECI2C 0xF0
217 #define CONFIG_SYS_CS0_BASE 0xFF800000
218 #define CONFIG_SYS_CS0_MASK 0x007F0021
219 #define CONFIG_SYS_CS0_CTRL 0x00001D80
221 #define CONFIG_SYS_CS1_BASE 0xE0000000
222 #define CONFIG_SYS_CS1_MASK 0x00000001
223 #define CONFIG_SYS_CS1_CTRL 0x00003DD8
225 /*-----------------------------------------------------------------------
228 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
229 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
230 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
231 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
232 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
233 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
234 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
236 #endif /* _M5253DEMO_H */