m68k: Drop CONFIG_MCFPIT support
[oweals/u-boot.git] / include / configs / M52277EVB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuation settings for the Freescale MCF52277 EVB board.
4  *
5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7  */
8
9 /*
10  * board/config.h - configuration options, board specific
11  */
12
13 #ifndef _M52277EVB_H
14 #define _M52277EVB_H
15
16 /*
17  * High Level Configuration Options
18  * (easy to change)
19  */
20
21 #define CONFIG_MCFUART
22 #define CONFIG_SYS_UART_PORT            (0)
23
24 #undef CONFIG_WATCHDOG
25
26 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
27
28 /*
29  * BOOTP options
30  */
31 #define CONFIG_BOOTP_BOOTFILESIZE
32
33 #define CONFIG_HOSTNAME                 "M52277EVB"
34 #define CONFIG_SYS_UBOOT_END            0x3FFFF
35 #define CONFIG_SYS_LOAD_ADDR2           0x40010007
36 #ifdef CONFIG_SYS_STMICRO_BOOT
37 /* ST Micro serial flash */
38 #define CONFIG_EXTRA_ENV_SETTINGS               \
39         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
40         "loadaddr=0x40010000\0"                 \
41         "uboot=u-boot.bin\0"                    \
42         "load=loadb ${loadaddr} ${baudrate};"   \
43         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
44         "upd=run load; run prog\0"              \
45         "prog=sf probe 0:2 10000 1;"            \
46         "sf erase 0 30000;"                     \
47         "sf write ${loadaddr} 0 30000;"         \
48         "save\0"                                \
49         ""
50 #endif
51 #ifdef CONFIG_SYS_SPANSION_BOOT
52 #define CONFIG_EXTRA_ENV_SETTINGS               \
53         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
54         "loadaddr=0x40010000\0"                 \
55         "uboot=u-boot.bin\0"                    \
56         "load=loadb ${loadaddr} ${baudrate}\0"  \
57         "upd=run load; run prog\0"              \
58         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
59         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
60         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
61         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
62         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
63         " ${filesize}; save\0"                  \
64         "updsbf=run loadsbf; run progsbf\0"     \
65         "loadsbf=loadb ${loadaddr} ${baudrate};"        \
66         "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"   \
67         "progsbf=sf probe 0:2 10000 1;"         \
68         "sf erase 0 30000;"                     \
69         "sf write ${loadaddr} 0 30000;"         \
70         ""
71 #endif
72
73 /* LCD */
74 #ifdef CONFIG_CMD_BMP
75 #define CONFIG_SPLASH_SCREEN
76 #define CONFIG_LCD_LOGO
77 #define CONFIG_SHARP_LQ035Q7DH06
78 #endif
79
80 /* USB */
81 #ifdef CONFIG_CMD_USB
82 #define CONFIG_SYS_USB_EHCI_REGS_BASE   0xFC0B0000
83 #define CONFIG_SYS_USB_EHCI_CPU_INIT
84 #endif
85
86 /* Realtime clock */
87 #define CONFIG_MCFRTC
88 #undef RTC_DEBUG
89 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
90
91 /* Timer */
92 #define CONFIG_MCFTMR
93
94 /* I2c */
95 #define CONFIG_SYS_I2C
96 #define CONFIG_SYS_I2C_FSL
97 #define CONFIG_SYS_FSL_I2C_SPEED        80000
98 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
99 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
100 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
101
102 /* DSPI and Serial Flash */
103 #define CONFIG_CF_DSPI
104 #define CONFIG_SYS_SBFHDR_SIZE          0x7
105
106 /* Input, PCI, Flexbus, and VCO */
107 #define CONFIG_EXTRA_CLOCK
108
109 #define CONFIG_SYS_INPUT_CLKSRC 16000000
110
111 #define CONFIG_PRAM             2048    /* 2048 KB */
112
113 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 0x10000)
114
115 #define CONFIG_SYS_MBAR         0xFC000000
116
117 /*
118  * Low Level Configuration Settings
119  * (address mappings, register initial values, etc.)
120  * You should know what you are doing if you make changes here.
121  */
122
123 /*
124  * Definitions for initial stack pointer and data area (in DPRAM)
125  */
126 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
127 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
128 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
129 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
130 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 32)
131 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
132
133 /*
134  * Start addresses for the final memory configuration
135  * (Set up by the startup code)
136  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
137  */
138 #define CONFIG_SYS_SDRAM_BASE           0x40000000
139 #define CONFIG_SYS_SDRAM_SIZE           64      /* SDRAM size in MB */
140 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
141 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
142 #define CONFIG_SYS_SDRAM_CTRL           0xE1092000
143 #define CONFIG_SYS_SDRAM_EMOD           0x81810000
144 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
145 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0x00
146
147 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
148 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
149
150 #ifdef CONFIG_CF_SBF
151 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
152 #else
153 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
154 #endif
155 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
156 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
157 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
158
159 /* Initial Memory map for Linux */
160 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
161 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
162
163 /*
164  * Configuration for environment
165  * Environment is not embedded in u-boot. First time runing may have env
166  * crc error warning if there is no correct environment on the flash.
167  */
168 #define CONFIG_ENV_OVERWRITE            1
169
170 /*-----------------------------------------------------------------------
171  * FLASH organization
172  */
173 #ifdef CONFIG_SYS_STMICRO_BOOT
174 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
175 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
176 #endif
177 #ifdef CONFIG_SYS_SPANSION_BOOT
178 #       define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_CS0_BASE
179 #       define CONFIG_SYS_FLASH0_BASE   CONFIG_SYS_CS0_BASE
180 #endif
181
182 #ifdef CONFIG_SYS_FLASH_CFI
183 #       define CONFIG_FLASH_SPANSION_S29WS_N    1
184 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
185 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
186 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
187 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
188 #       define CONFIG_SYS_FLASH_CHECKSUM
189 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE }
190 #endif
191
192 #define LDS_BOARD_TEXT \
193         arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
194         arch/m68k/lib/built-in.o            (.text*)
195
196 /*
197  * This is setting for JFFS2 support in u-boot.
198  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
199  */
200 #ifdef CONFIG_CMD_JFFS2
201 #       define CONFIG_JFFS2_DEV         "nor0"
202 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x40000)
203 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
204 #endif
205
206 /*-----------------------------------------------------------------------
207  * Cache Configuration
208  */
209 #define CONFIG_SYS_CACHELINE_SIZE       16
210
211 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
212                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
213 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
214                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
215 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
216 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
217                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
218                                          CF_ACR_EN | CF_ACR_SM_ALL)
219 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
220                                          CF_CACR_DISD | CF_CACR_INVI | \
221                                          CF_CACR_CEIB | CF_CACR_DCM | \
222                                          CF_CACR_EUSP)
223
224 /*-----------------------------------------------------------------------
225  * Memory bank definitions
226  */
227 /*
228  * CS0 - NOR Flash
229  * CS1 - Available
230  * CS2 - Available
231  * CS3 - Available
232  * CS4 - Available
233  * CS5 - Available
234  */
235
236 #ifdef CONFIG_CF_SBF
237 #define CONFIG_SYS_CS0_BASE             0x04000000
238 #define CONFIG_SYS_CS0_MASK             0x00FF0001
239 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
240 #else
241 #define CONFIG_SYS_CS0_BASE             0x00000000
242 #define CONFIG_SYS_CS0_MASK             0x00FF0001
243 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
244 #endif
245
246 #endif                          /* _M52277EVB_H */