2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
6 * Bruno Achauer, Exet AG, bruno@exet-ag.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * board/config.h - configuration options, board specific
29 * [derived from config_TQM850L.h]
36 * High Level Configuration Options
40 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
41 #define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */
44 * Port assignments (CONFIG_LANTEC == 1):
46 * - SMC2: J6 (Feature connector)
50 * Port assignments (CONFIG_LANTEC == 2): TBD
54 #undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */
55 #define CONFIG_8xx_CONS_SCC3
56 #undef CONFIG_8xx_CONS_NONE
57 #define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
59 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
61 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
64 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
66 #undef CONFIG_BOOTARGS
67 #define CONFIG_BOOTCOMMAND \
68 "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"
70 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
71 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
73 #undef CONFIG_WATCHDOG /* watchdog disabled */
75 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
80 #define CONFIG_BOOTP_SUBNETMASK
81 #define CONFIG_BOOTP_GATEWAY
82 #define CONFIG_BOOTP_HOSTNAME
83 #define CONFIG_BOOTP_BOOTPATH
84 #define CONFIG_BOOTP_BOOTFILESIZE
88 * Command line configuration.
90 #include <config_cmd_all.h>
92 #undef CONFIG_CMD_BEDBUG
95 #undef CONFIG_CMD_DISPLAY
98 #undef CONFIG_CMD_EEPROM
100 #undef CONFIG_CMD_EXT2
101 #undef CONFIG_CMD_FDC
102 #undef CONFIG_CMD_FDOS
103 #undef CONFIG_CMD_HWFLOW
104 #undef CONFIG_CMD_I2C
105 #undef CONFIG_CMD_IDE
106 #undef CONFIG_CMD_IRQ
107 #undef CONFIG_CMD_JFFS2
108 #undef CONFIG_CMD_KGDB
109 #undef CONFIG_CMD_MII
110 #undef CONFIG_CMD_MMC
111 #undef CONFIG_CMD_NAND
112 #undef CONFIG_CMD_PCI
113 #undef CONFIG_CMD_PCMCIA
114 #undef CONFIG_CMD_REISER
115 #undef CONFIG_CMD_SCSI
116 #undef CONFIG_CMD_SPI
117 #undef CONFIG_CMD_UNIVERSE
118 #undef CONFIG_CMD_USB
119 #undef CONFIG_CMD_VFD
120 #undef CONFIG_CMD_XIMG
122 #if !(CONFIG_LANTEC >= 2)
123 #undef CONFIG_CMD_DATE
124 #undef CONFIG_CMD_NET
128 #if CONFIG_LANTEC >= 2
129 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
133 * Miscellaneous configurable options
135 #define CFG_LONGHELP /* undef to save memory */
136 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
137 #if defined(CONFIG_CMD_KGDB)
138 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
140 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
142 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
143 #define CFG_MAXARGS 16 /* max number of command args */
144 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
146 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
147 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
149 #define CFG_LOAD_ADDR 0x100000 /* default load address */
151 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
153 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
156 * Low Level Configuration Settings
157 * (address mappings, register initial values, etc.)
158 * You should know what you are doing if you make changes here.
160 /*-----------------------------------------------------------------------
161 * Internal Memory Mapped Register
163 #define CFG_IMMR 0xFFF00000
165 /*-----------------------------------------------------------------------
166 * Definitions for initial stack pointer and data area (in DPRAM)
168 #define CFG_INIT_RAM_ADDR CFG_IMMR
169 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
170 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
171 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
172 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
174 /*-----------------------------------------------------------------------
175 * Start addresses for the final memory configuration
176 * (Set up by the startup code)
177 * Please note that CFG_SDRAM_BASE _must_ start at 0
179 #define CFG_SDRAM_BASE 0x00000000
180 #define CFG_FLASH_BASE 0x40000000
181 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
182 #define CFG_MONITOR_BASE CFG_FLASH_BASE
183 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
186 * For booting Linux, the board info and command line data
187 * have to be in the first 8 MB of memory, since this is
188 * the maximum mapped by the Linux kernel during initialization.
190 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
192 /*-----------------------------------------------------------------------
195 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
196 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
198 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
199 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
201 #define CFG_ENV_IS_IN_FLASH 1
202 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
203 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
205 /*-----------------------------------------------------------------------
206 * Cache Configuration
208 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
209 #if defined(CONFIG_CMD_KGDB)
210 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
213 /*-----------------------------------------------------------------------
214 * SYPCR - System Protection Control 11-9
215 * SYPCR can only be written once after reset!
216 *-----------------------------------------------------------------------
217 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
219 #if defined(CONFIG_WATCHDOG)
220 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
221 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
223 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
226 /*-----------------------------------------------------------------------
227 * SIUMCR - SIU Module Configuration 11-6
228 *-----------------------------------------------------------------------
229 * PCMCIA config., multi-function pin tri-state
231 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)
233 /*-----------------------------------------------------------------------
234 * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
235 *-----------------------------------------------------------------------
237 #define CONFIG_8xx_GCLK_FREQ 33000000
239 /*-----------------------------------------------------------------------
240 * TBSCR - Time Base Status and Control 11-26
241 *-----------------------------------------------------------------------
242 * Clear Reference Interrupt Status, Timebase freezing enabled
244 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
246 /*-----------------------------------------------------------------------
247 * RTCSC - Real-Time Clock Status and Control Register 11-27
248 *-----------------------------------------------------------------------
250 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
252 /*-----------------------------------------------------------------------
253 * PISCR - Periodic Interrupt Status and Control 11-31
254 *-----------------------------------------------------------------------
255 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
257 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
259 /*-----------------------------------------------------------------------
260 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
261 *-----------------------------------------------------------------------
262 * Reset PLL lock status sticky bit, timer expired status bit and timer
263 * interrupt status bit
265 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
267 /* up to 50 MHz we use a 1:1 clock */
268 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
270 /*-----------------------------------------------------------------------
271 * SCCR - System Clock and reset Control Register 15-27
272 *-----------------------------------------------------------------------
273 * Set clock output, timebase and RTC source and divider,
274 * power management and some other internal clocks
276 #define SCCR_MASK SCCR_EBDF11
277 /* up to 50 MHz we use a 1:1 clock */
278 #define CFG_SCCR (SCCR_TBS | \
279 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
280 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
283 /*-----------------------------------------------------------------------
285 *-----------------------------------------------------------------------
291 * Init Memory Controller:
293 * BR0/5 and OR0/5 (FLASH)
296 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
297 #define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */
299 /* used to re-map FLASH both when starting from SRAM or FLASH:
300 * restrict access enough to keep SRAM working (if any)
301 * but not too much to meddle with FLASH accesses
303 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
304 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
307 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \
308 OR_SCY_5_CLK | OR_TRLX)
310 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
311 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
312 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
314 #define CFG_OR5_REMAP CFG_OR0_REMAP
315 #define CFG_OR5_PRELIM CFG_OR0_PRELIM
316 #define CFG_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )
319 * BR2/3 and OR2/3 (SDRAM)
322 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
323 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
325 /* SDRAM timing: Multiplexed addresses */
326 #define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM)
328 #define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
329 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
332 * Memory Periodic Timer Prescaler
335 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
336 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
337 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
339 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
340 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
341 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
344 * MAMR settings for SDRAM
346 /* periodic timer for refresh */
347 #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
350 #define CFG_MAMR_8COL \
351 ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
352 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
353 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
356 * Internal Definitions
360 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
361 #define BOOTFLAG_WARM 0x02 /* Software reboot */
367 /* No command line, one static partition, whole device */
368 #undef CONFIG_JFFS2_CMDLINE
369 #define CONFIG_JFFS2_DEV "nor0"
370 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
371 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
373 /* mtdparts command line support */
375 #define CONFIG_JFFS2_CMDLINE
376 #define MTDIDS_DEFAULT ""
377 #define MTDPARTS_DEFAULT ""
380 #endif /* __CONFIG_H */