2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
35 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
37 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38 #define BOOTFLAG_WARM 0x02 /* Software reboot */
40 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
41 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
42 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
46 * Serial console configuration
48 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
53 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
56 * 0x40000000 - 0x4fffffff - PCI Memory
57 * 0x50000000 - 0x50ffffff - PCI IO Space
60 #define CONFIG_PCI_PNP 1
61 #define CONFIG_PCI_SCAN_SHOW 1
63 #define CONFIG_PCI_MEM_BUS 0x40000000
64 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
65 #define CONFIG_PCI_MEM_SIZE 0x10000000
67 #define CONFIG_PCI_IO_BUS 0x50000000
68 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69 #define CONFIG_PCI_IO_SIZE 0x01000000
71 #define CFG_XLB_PIPELINING 1
73 #define CONFIG_NET_MULTI 1
75 #define CONFIG_EEPRO100 1
76 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
77 #define CONFIG_NS8382X 1
79 #define ADD_PCI_CMD CFG_CMD_PCI
84 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
89 #define CONFIG_MAC_PARTITION
90 #define CONFIG_DOS_PARTITION
91 #define CONFIG_ISO_PARTITION
95 #define CONFIG_USB_OHCI
96 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
97 #define CONFIG_USB_STORAGE
102 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
107 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
117 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
118 #include <cmd_confdefs.h>
120 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
121 # define CFG_LOWBOOT 1
122 # define CFG_LOWBOOT16 1
124 #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
125 #if defined(CONFIG_LITE5200B)
126 # error CFG_LOWBOOT08 is incompatible with the Lite5200B
128 # define CFG_LOWBOOT 1
129 # define CFG_LOWBOOT08 1
136 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
138 #define CONFIG_PREBOOT "echo;" \
139 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
142 #undef CONFIG_BOOTARGS
144 #define CONFIG_EXTRA_ENV_SETTINGS \
146 "nfsargs=setenv bootargs root=/dev/nfs rw " \
147 "nfsroot=${serverip}:${rootpath}\0" \
148 "ramargs=setenv bootargs root=/dev/ram rw\0" \
149 "addip=setenv bootargs ${bootargs} " \
150 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
151 ":${hostname}:${netdev}:off panic=1\0" \
152 "flash_nfs=run nfsargs addip;" \
153 "bootm ${kernel_addr}\0" \
154 "flash_self=run ramargs addip;" \
155 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
156 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
157 "rootpath=/opt/eldk/ppc_82xx\0" \
158 "bootfile=/tftpboot/MPC5200/uImage\0" \
161 #define CONFIG_BOOTCOMMAND "run flash_self"
163 #if defined(CONFIG_MPC5200)
165 * IPB Bus clocking configuration.
167 #if defined(CONFIG_LITE5200B)
168 #define CFG_IPBSPEED_133 /* define for 133MHz speed */
170 #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
172 #endif /* CONFIG_MPC5200 */
176 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
177 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
179 #define CFG_I2C_SPEED 100000 /* 100 kHz */
180 #define CFG_I2C_SLAVE 0x7F
183 * EEPROM configuration
185 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
186 #define CFG_I2C_EEPROM_ADDR_LEN 1
187 #define CFG_EEPROM_PAGE_WRITE_BITS 3
188 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
191 * Flash configuration
193 #if defined(CONFIG_LITE5200B)
194 #define CFG_FLASH_BASE 0xFE000000
195 #define CFG_FLASH_SIZE 0x01000000
196 #if !defined(CFG_LOWBOOT)
197 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01760000 + 0x00800000)
198 #else /* CFG_LOWBOOT */
199 #if defined(CFG_LOWBOOT08)
200 # error CFG_LOWBOOT08 is incompatible with the Lite5200B
202 #if defined(CFG_LOWBOOT16)
203 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01060000)
205 #endif /* CFG_LOWBOOT */
206 #else /* !CONFIG_LITE5200B (IceCube)*/
207 #define CFG_FLASH_BASE 0xFF000000
208 #define CFG_FLASH_SIZE 0x01000000
209 #if !defined(CFG_LOWBOOT)
210 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
211 #else /* CFG_LOWBOOT */
212 #if defined(CFG_LOWBOOT08)
213 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000)
215 #if defined(CFG_LOWBOOT16)
216 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
218 #endif /* CFG_LOWBOOT */
219 #endif /* CONFIG_LITE5200B */
220 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
222 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
224 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
225 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
227 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
229 #if defined(CONFIG_LITE5200B)
230 #define CFG_FLASH_CFI_DRIVER
231 #define CFG_FLASH_CFI
232 #define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START}
237 * Environment settings
239 #define CFG_ENV_IS_IN_FLASH 1
240 #define CFG_ENV_SIZE 0x10000
241 #if defined(CONFIG_LITE5200B)
242 #define CFG_ENV_SECT_SIZE 0x20000
244 #define CFG_ENV_SECT_SIZE 0x10000
246 #define CONFIG_ENV_OVERWRITE 1
251 #define CFG_MBAR 0xF0000000
252 #define CFG_SDRAM_BASE 0x00000000
253 #define CFG_DEFAULT_MBAR 0x80000000
255 /* Use SRAM until RAM will be available */
256 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
257 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
260 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
261 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
262 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
264 #define CFG_MONITOR_BASE TEXT_BASE
265 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
266 # define CFG_RAMBOOT 1
269 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
270 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
271 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
274 * Ethernet configuration
276 #define CONFIG_MPC5xxx_FEC 1
278 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
280 /* #define CONFIG_FEC_10MBIT 1 */
281 #define CONFIG_PHY_ADDR 0x00
282 #if defined(CONFIG_LITE5200B)
283 #define CONFIG_FEC_MII100 1
289 #ifdef CONFIG_MPC5200_DDR
290 #define CFG_GPS_PORT_CONFIG 0x90000004
292 #define CFG_GPS_PORT_CONFIG 0x10000004
296 * Miscellaneous configurable options
298 #define CFG_LONGHELP /* undef to save memory */
299 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
300 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
301 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
303 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
305 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
306 #define CFG_MAXARGS 16 /* max number of command args */
307 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
309 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
310 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
312 #define CFG_LOAD_ADDR 0x100000 /* default load address */
314 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
317 * Various low-level settings
319 #if defined(CONFIG_MPC5200)
320 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
321 #define CFG_HID0_FINAL HID0_ICE
323 #define CFG_HID0_INIT 0
324 #define CFG_HID0_FINAL 0
327 #if defined(CONFIG_LITE5200B)
328 #define CFG_CS1_START CFG_FLASH_BASE
329 #define CFG_CS1_SIZE CFG_FLASH_SIZE
330 #define CFG_CS1_CFG 0x00047800
331 #define CFG_CS0_START (CFG_FLASH_BASE + CFG_FLASH_SIZE)
332 #define CFG_CS0_SIZE CFG_FLASH_SIZE
333 #define CFG_BOOTCS_START CFG_CS0_START
334 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
335 #define CFG_BOOTCS_CFG 0x00047800
336 #else /* IceCube aka Lite5200 */
337 #ifdef CONFIG_MPC5200_DDR
339 #define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE)
340 #define CFG_BOOTCS_SIZE 0x00800000
341 #define CFG_BOOTCS_CFG 0x00047801
342 #define CFG_CS1_START CFG_FLASH_BASE
343 #define CFG_CS1_SIZE 0x00800000
344 #define CFG_CS1_CFG 0x00047800
346 #else /* !CONFIG_MPC5200_DDR */
348 #define CFG_BOOTCS_START CFG_FLASH_BASE
349 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
350 #define CFG_BOOTCS_CFG 0x00047801
351 #define CFG_CS0_START CFG_FLASH_BASE
352 #define CFG_CS0_SIZE CFG_FLASH_SIZE
354 #endif /* CONFIG_MPC5200_DDR */
355 #endif /*CONFIG_LITE5200B */
357 #define CFG_CS_BURST 0x00000000
358 #define CFG_CS_DEADCYCLE 0x33333333
360 #define CFG_RESET_ADDRESS 0xff000000
362 /*-----------------------------------------------------------------------
364 *-----------------------------------------------------------------------
366 #define CONFIG_USB_CLOCK 0x0001BBBB
367 #define CONFIG_USB_CONFIG 0x00001000
369 /*-----------------------------------------------------------------------
370 * IDE/ATA stuff Supports IDE harddisk
371 *-----------------------------------------------------------------------
374 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
376 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
377 #undef CONFIG_IDE_LED /* LED for ide not supported */
379 #define CONFIG_IDE_RESET /* reset for ide supported */
380 #define CONFIG_IDE_PREINIT
382 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
383 #define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
385 #define CFG_ATA_IDE0_OFFSET 0x0000
387 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
389 /* Offset for data I/O */
390 #define CFG_ATA_DATA_OFFSET (0x0060)
392 /* Offset for normal register accesses */
393 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
395 /* Offset for alternate registers */
396 #define CFG_ATA_ALT_OFFSET (0x005C)
398 /* Interval between registers */
399 #define CFG_ATA_STRIDE 4
401 #define CONFIG_ATAPI 1
403 #endif /* __CONFIG_H */