3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37 #define CONFIG_IVML24 1 /* ...on a IVML24 board */
39 #define CONFIG_SYS_TEXT_BASE 0xFF000000
41 #if defined (CONFIG_IVML24_16M)
42 # define CONFIG_IDENT_STRING " IVML24"
43 #elif defined (CONFIG_IVML24_32M)
44 # define CONFIG_IDENT_STRING " IVML24_128"
45 #elif defined (CONFIG_IVML24_64M)
46 # define CONFIG_IDENT_STRING " IVML24_256"
49 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
50 #undef CONFIG_8xx_CONS_SMC2
51 #undef CONFIG_8xx_CONS_NONE
52 #define CONFIG_BAUDRATE 115200
54 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
55 #define CONFIG_8xx_GCLK_FREQ 50331648
57 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
59 #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
62 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
64 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
66 #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
68 #define CONFIG_BOOTARGS "root=/dev/nfs rw " \
69 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
70 "nfsaddrs=10.0.0.99:10.0.0.2"
72 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
73 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
75 #undef CONFIG_WATCHDOG /* watchdog disabled */
77 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
81 * Command line configuration.
83 #include <config_cmd_default.h>
85 #define CONFIG_CMD_IDE
88 #define CONFIG_MAC_PARTITION
89 #define CONFIG_DOS_PARTITION
94 #define CONFIG_BOOTP_SUBNETMASK
95 #define CONFIG_BOOTP_HOSTNAME
96 #define CONFIG_BOOTP_BOOTPATH
97 #define CONFIG_BOOTP_BOOTFILESIZE
101 * Miscellaneous configurable options
103 #define CONFIG_SYS_LONGHELP /* undef to save memory */
104 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
105 #if defined(CONFIG_CMD_KGDB)
106 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
108 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
110 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
111 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
112 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
114 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
115 #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
117 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
119 #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
121 #define CONFIG_SYS_PB_12V_ENABLE 0x00002000 /* PB 18 */
122 #define CONFIG_SYS_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */
123 #define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
124 #define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
125 #define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */
127 #define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
128 #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
130 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
132 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
135 * Low Level Configuration Settings
136 * (address mappings, register initial values, etc.)
137 * You should know what you are doing if you make changes here.
139 /*-----------------------------------------------------------------------
140 * Internal Memory Mapped Register
142 #define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
144 /*-----------------------------------------------------------------------
145 * Definitions for initial stack pointer and data area (in DPRAM)
147 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
149 #if defined (CONFIG_IVML24_16M)
150 # define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
151 #elif defined (CONFIG_IVML24_32M)
152 # define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
153 #elif defined (CONFIG_IVML24_64M)
154 # define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
157 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
158 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
159 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
161 /*-----------------------------------------------------------------------
162 * Start addresses for the final memory configuration
163 * (Set up by the startup code)
164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
166 #define CONFIG_SYS_SDRAM_BASE 0x00000000
167 #define CONFIG_SYS_FLASH_BASE 0xFF000000
169 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
171 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
173 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
174 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
177 * For booting Linux, the board info and command line data
178 * have to be in the first 8 MB of memory, since this is
179 * the maximum mapped by the Linux kernel during initialization.
181 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
182 /*-----------------------------------------------------------------------
185 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
186 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
188 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
191 #define CONFIG_ENV_IS_IN_FLASH 1
192 #define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
193 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
194 /*-----------------------------------------------------------------------
195 * Cache Configuration
197 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
198 #if defined(CONFIG_CMD_KGDB)
199 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
202 /*-----------------------------------------------------------------------
203 * SYPCR - System Protection Control 11-9
204 * SYPCR can only be written once after reset!
205 *-----------------------------------------------------------------------
206 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
208 #if defined(CONFIG_WATCHDOG)
210 # if defined (CONFIG_IVML24_16M)
211 # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
212 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
213 # elif defined (CONFIG_IVML24_32M)
214 # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
215 SYPCR_SWE | SYPCR_SWP)
216 # elif defined (CONFIG_IVML24_64M)
217 # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
218 SYPCR_SWE | SYPCR_SWP)
222 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
225 /*-----------------------------------------------------------------------
226 * SIUMCR - SIU Module Configuration 11-6
227 *-----------------------------------------------------------------------
228 * PCMCIA config., multi-function pin tri-state
230 /* EARB, DBGC and DBPC are initialised by the HCW */
232 #define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
234 /*-----------------------------------------------------------------------
235 * TBSCR - Time Base Status and Control 11-26
236 *-----------------------------------------------------------------------
237 * Clear Reference Interrupt Status, Timebase freezing enabled
239 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
241 /*-----------------------------------------------------------------------
242 * PISCR - Periodic Interrupt Status and Control 11-31
243 *-----------------------------------------------------------------------
244 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
246 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
248 /*-----------------------------------------------------------------------
249 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
250 *-----------------------------------------------------------------------
251 * Reset PLL lock status sticky bit, timer expired status bit and timer
252 * interrupt status bit, set PLL multiplication factor !
255 #define CONFIG_SYS_PLPRCR \
256 ( (11 << PLPRCR_MF_SHIFT) | \
257 PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
258 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
259 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
262 /*-----------------------------------------------------------------------
263 * SCCR - System Clock and reset Control Register 15-27
264 *-----------------------------------------------------------------------
265 * Set clock output, timebase and RTC source and divider,
266 * power management and some other internal clocks
268 #define SCCR_MASK SCCR_EBDF11
270 #define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
271 SCCR_RTDIV | SCCR_RTSEL | \
272 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
273 SCCR_EBDF00 | SCCR_DFSYNC00 | \
274 SCCR_DFBRG00 | SCCR_DFNL000 | \
275 SCCR_DFNH000 | SCCR_DFLCD101 | \
278 /*-----------------------------------------------------------------------
279 * RTCSC - Real-Time Clock Status and Control Register 11-27
280 *-----------------------------------------------------------------------
283 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
286 /*-----------------------------------------------------------------------
287 * RCCR - RISC Controller Configuration Register 19-4
288 *-----------------------------------------------------------------------
291 #define CONFIG_SYS_RCCR 0x0200
293 /*-----------------------------------------------------------------------
294 * RMDS - RISC Microcode Development Support Control Register
295 *-----------------------------------------------------------------------
297 #define CONFIG_SYS_RMDS 0
299 /*-----------------------------------------------------------------------
302 *-----------------------------------------------------------------------
304 #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
306 /*-----------------------------------------------------------------------
308 *-----------------------------------------------------------------------
311 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
312 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
313 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
314 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
315 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
316 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
317 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
318 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
320 /*-----------------------------------------------------------------------
322 *-----------------------------------------------------------------------
324 #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
325 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
327 #define CONFIG_SYS_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/
328 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
330 #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
331 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
332 #undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */
334 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
335 #define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
336 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
338 /*-----------------------------------------------------------------------
340 *-----------------------------------------------------------------------
343 #define CONFIG_SYS_DER 0
346 * Init Memory Controller:
348 * BR0 and OR0 (FLASH)
351 #define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
353 /* used to re-map FLASH both when starting from SRAM or FLASH:
354 * restrict access enough to keep SRAM working (if any)
355 * but not too much to meddle with FLASH accesses
357 /* EPROMs are 512kb */
358 #define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
359 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
361 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
362 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR)
364 #define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
365 CONFIG_SYS_OR_TIMING_FLASH)
366 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
367 CONFIG_SYS_OR_TIMING_FLASH)
368 /* 16 bit, bank valid */
369 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
372 * BR1/OR1 - ELIC SACCO bank @ 0xFE000000
374 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
376 #define ELIC_SACCO_BASE 0xFE000000
377 #define ELIC_SACCO_OR_AM 0xFFFF8000
378 #define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
380 #define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
382 #define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
385 * BR2/OR2 - ELIC EPIC bank @ 0xFE008000
387 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
389 #define ELIC_EPIC_BASE 0xFE008000
390 #define ELIC_EPIC_OR_AM 0xFFFF8000
391 #define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
393 #define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
395 #define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
400 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
402 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
403 #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
404 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
406 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
408 #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
409 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
412 * BR4/OR4 - HDLC Address
414 * AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
416 #define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */
417 #define HDLC_ADDR_OR_AM 0xFFFF8000
418 #define HDLC_ADDR_TIMING OR_SCY_1_CLK
420 #define CONFIG_SYS_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
421 #define CONFIG_SYS_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
424 * BR5/OR5: SHARC ADSP-2165L
426 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
428 #define SHARC_BASE 0xFE400000
429 #define SHARC_OR_AM 0xFFC00000
430 #define SHARC_TIMING OR_SCY_0_CLK
432 #define CONFIG_SYS_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
433 #define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
436 * Memory Periodic Timer Prescaler
439 /* periodic timer for refresh */
440 #define CONFIG_SYS_MBMR_PTB 204
442 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
443 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
444 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
446 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
447 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
449 #if defined (CONFIG_IVML24_16M)
450 # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
451 #elif defined (CONFIG_IVML24_32M)
452 # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
453 #elif defined (CONFIG_IVML24_64M)
454 # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
459 * MBMR settings for SDRAM
462 #if defined (CONFIG_IVML24_16M)
464 # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
465 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
466 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
467 #elif defined (CONFIG_IVML24_32M)
469 # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
470 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
471 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
472 #elif defined (CONFIG_IVML24_64M)
474 # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
475 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
476 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
478 #endif /* __CONFIG_H */