3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37 #define CONFIG_IVML24 1 /* ...on a IVML24 board */
39 #if defined (CONFIG_IVML24_16M)
40 # define CONFIG_IDENT_STRING " IVML24"
41 #elif defined (CONFIG_IVML24_32M)
42 # define CONFIG_IDENT_STRING " IVML24_128"
43 #elif defined (CONFIG_IVML24_64M)
44 # define CONFIG_IDENT_STRING " IVML24_256"
47 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
48 #undef CONFIG_8xx_CONS_SMC2
49 #undef CONFIG_8xx_CONS_NONE
50 #define CONFIG_BAUDRATE 115200
52 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
53 #define CONFIG_8xx_GCLK_FREQ 50331648
55 #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
58 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
60 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
62 #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
64 #define CONFIG_BOOTARGS "root=/dev/nfs rw " \
65 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
66 "nfsaddrs=10.0.0.99:10.0.0.2"
68 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
69 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
71 #undef CONFIG_WATCHDOG /* watchdog disabled */
73 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
77 * Command line configuration.
79 #include <config_cmd_default.h>
81 #define CONFIG_CMD_IDE
84 #define CONFIG_MAC_PARTITION
85 #define CONFIG_DOS_PARTITION
87 #define CONFIG_BOOTP_MASK \
88 ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
91 * Miscellaneous configurable options
93 #define CFG_LONGHELP /* undef to save memory */
94 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
95 #if defined(CONFIG_CMD_KGDB)
96 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
98 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
100 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
101 #define CFG_MAXARGS 16 /* max number of command args */
102 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
104 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
105 #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
107 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
109 #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
111 #define CFG_PB_12V_ENABLE 0x00002000 /* PB 18 */
112 #define CFG_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */
113 #define CFG_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
114 #define CFG_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
115 #define CFG_PB_IDE_MOTOR 0x00020000 /* PB 14 */
117 #define CFG_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
118 #define CFG_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
120 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
122 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
125 * Low Level Configuration Settings
126 * (address mappings, register initial values, etc.)
127 * You should know what you are doing if you make changes here.
129 /*-----------------------------------------------------------------------
130 * Internal Memory Mapped Register
132 #define CFG_IMMR 0xFFF00000 /* was: 0xFF000000 */
134 /*-----------------------------------------------------------------------
135 * Definitions for initial stack pointer and data area (in DPRAM)
137 #define CFG_INIT_RAM_ADDR CFG_IMMR
139 #if defined (CONFIG_IVML24_16M)
140 # define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
141 #elif defined (CONFIG_IVML24_32M)
142 # define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
143 #elif defined (CONFIG_IVML24_64M)
144 # define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
147 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
148 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
149 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
151 /*-----------------------------------------------------------------------
152 * Start addresses for the final memory configuration
153 * (Set up by the startup code)
154 * Please note that CFG_SDRAM_BASE _must_ start at 0
156 #define CFG_SDRAM_BASE 0x00000000
157 #define CFG_FLASH_BASE 0xFF000000
159 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
161 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
163 #define CFG_MONITOR_BASE CFG_FLASH_BASE
164 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
167 * For booting Linux, the board info and command line data
168 * have to be in the first 8 MB of memory, since this is
169 * the maximum mapped by the Linux kernel during initialization.
171 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
172 /*-----------------------------------------------------------------------
175 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
176 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
178 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
179 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
181 #define CFG_ENV_IS_IN_FLASH 1
182 #define CFG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
183 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
184 /*-----------------------------------------------------------------------
185 * Cache Configuration
187 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
188 #if defined(CONFIG_CMD_KGDB)
189 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
192 /*-----------------------------------------------------------------------
193 * SYPCR - System Protection Control 11-9
194 * SYPCR can only be written once after reset!
195 *-----------------------------------------------------------------------
196 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
198 #if defined(CONFIG_WATCHDOG)
200 # if defined (CONFIG_IVML24_16M)
201 # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
202 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
203 # elif defined (CONFIG_IVML24_32M)
204 # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
205 SYPCR_SWE | SYPCR_SWP)
206 # elif defined (CONFIG_IVML24_64M)
207 # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
208 SYPCR_SWE | SYPCR_SWP)
212 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
215 /*-----------------------------------------------------------------------
216 * SIUMCR - SIU Module Configuration 11-6
217 *-----------------------------------------------------------------------
218 * PCMCIA config., multi-function pin tri-state
220 /* EARB, DBGC and DBPC are initialised by the HCW */
222 #define CFG_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E)
224 /*-----------------------------------------------------------------------
225 * TBSCR - Time Base Status and Control 11-26
226 *-----------------------------------------------------------------------
227 * Clear Reference Interrupt Status, Timebase freezing enabled
229 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
231 /*-----------------------------------------------------------------------
232 * PISCR - Periodic Interrupt Status and Control 11-31
233 *-----------------------------------------------------------------------
234 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
236 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
238 /*-----------------------------------------------------------------------
239 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
240 *-----------------------------------------------------------------------
241 * Reset PLL lock status sticky bit, timer expired status bit and timer
242 * interrupt status bit, set PLL multiplication factor !
246 ( (11 << PLPRCR_MF_SHIFT) | \
247 PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
248 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
249 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
252 /*-----------------------------------------------------------------------
253 * SCCR - System Clock and reset Control Register 15-27
254 *-----------------------------------------------------------------------
255 * Set clock output, timebase and RTC source and divider,
256 * power management and some other internal clocks
258 #define SCCR_MASK SCCR_EBDF11
260 #define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \
261 SCCR_RTDIV | SCCR_RTSEL | \
262 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
263 SCCR_EBDF00 | SCCR_DFSYNC00 | \
264 SCCR_DFBRG00 | SCCR_DFNL000 | \
265 SCCR_DFNH000 | SCCR_DFLCD101 | \
268 /*-----------------------------------------------------------------------
269 * RTCSC - Real-Time Clock Status and Control Register 11-27
270 *-----------------------------------------------------------------------
273 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
276 /*-----------------------------------------------------------------------
277 * RCCR - RISC Controller Configuration Register 19-4
278 *-----------------------------------------------------------------------
281 #define CFG_RCCR 0x0200
283 /*-----------------------------------------------------------------------
284 * RMDS - RISC Microcode Development Support Control Register
285 *-----------------------------------------------------------------------
289 /*-----------------------------------------------------------------------
292 *-----------------------------------------------------------------------
294 #define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
296 /*-----------------------------------------------------------------------
298 *-----------------------------------------------------------------------
301 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
302 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
303 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
304 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
305 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
306 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
307 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
308 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
310 /*-----------------------------------------------------------------------
312 *-----------------------------------------------------------------------
314 #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
315 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
317 #define CFG_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/
318 #define CFG_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
320 #define CFG_ATA_BASE_ADDR 0xFE100000
321 #define CFG_ATA_IDE0_OFFSET 0x0000
322 #undef CFG_ATA_IDE1_OFFSET /* only one IDE bus available */
324 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
325 #define CFG_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
326 #define CFG_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
328 /*-----------------------------------------------------------------------
330 *-----------------------------------------------------------------------
336 * Init Memory Controller:
338 * BR0 and OR0 (FLASH)
341 #define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
343 /* used to re-map FLASH both when starting from SRAM or FLASH:
344 * restrict access enough to keep SRAM working (if any)
345 * but not too much to meddle with FLASH accesses
347 /* EPROMs are 512kb */
348 #define CFG_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
349 #define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
351 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
352 #define CFG_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR)
354 #define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
356 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
358 /* 16 bit, bank valid */
359 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
362 * BR1/OR1 - ELIC SACCO bank @ 0xFE000000
364 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
366 #define ELIC_SACCO_BASE 0xFE000000
367 #define ELIC_SACCO_OR_AM 0xFFFF8000
368 #define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
370 #define CFG_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
372 #define CFG_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
375 * BR2/OR2 - ELIC EPIC bank @ 0xFE008000
377 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
379 #define ELIC_EPIC_BASE 0xFE008000
380 #define ELIC_EPIC_OR_AM 0xFFFF8000
381 #define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
383 #define CFG_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
385 #define CFG_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
390 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
392 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
393 #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
394 #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
396 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
398 #define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
399 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
402 * BR4/OR4 - HDLC Address
404 * AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
406 #define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */
407 #define HDLC_ADDR_OR_AM 0xFFFF8000
408 #define HDLC_ADDR_TIMING OR_SCY_1_CLK
410 #define CFG_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
411 #define CFG_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
414 * BR5/OR5: SHARC ADSP-2165L
416 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
418 #define SHARC_BASE 0xFE400000
419 #define SHARC_OR_AM 0xFFC00000
420 #define SHARC_TIMING OR_SCY_0_CLK
422 #define CFG_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
423 #define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
426 * Memory Periodic Timer Prescaler
429 /* periodic timer for refresh */
430 #define CFG_MBMR_PTB 204
432 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
433 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
434 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
436 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
437 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
439 #if defined (CONFIG_IVML24_16M)
440 # define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
441 #elif defined (CONFIG_IVML24_32M)
442 # define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
443 #elif defined (CONFIG_IVML24_64M)
444 # define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
449 * MBMR settings for SDRAM
452 #if defined (CONFIG_IVML24_16M)
454 # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
455 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
456 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
457 #elif defined (CONFIG_IVML24_32M)
459 # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
460 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
461 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
462 #elif defined (CONFIG_IVML24_64M)
464 # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
465 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
466 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
470 * Internal Definitions
474 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
475 #define BOOTFLAG_WARM 0x02 /* Software reboot */
477 #endif /* __CONFIG_H */