2 * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
4 * This file is based on similar values for other boards found in
5 * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
33 #undef DEBUG /* General debug */
35 /*-----------------------------------------------------------------------
36 * High Level Configuration Options
40 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
41 #define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
43 #define CONFIG_CPM2 1 /* Has a CPM2 */
45 /*-----------------------------------------------------------------------
46 * select serial console configuration
48 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
49 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
52 * if CONFIG_CONS_NONE is defined, then the serial console routines must
53 * defined elsewhere (for example, on the cogent platform, there are serial
54 * ports on the motherboard which are used for the serial console - see
55 * cogent/cma101/serial.[ch]).
57 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
58 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
59 #undef CONFIG_CONS_NONE /* define if console on something else */
60 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
62 /*-----------------------------------------------------------------------
63 * select ethernet configuration
65 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
66 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
69 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
70 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
71 * from CONFIG_COMMANDS to remove support for networking.
73 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
74 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
75 #undef CONFIG_ETHER_NONE /* define if ether on something else */
76 #define CONFIG_ETHER_INDEX 3 /* which channel for ether */
78 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
80 /*-----------------------------------------------------------------------
83 * - Select bus for bd/buffers (see 28-13)
86 # define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
87 # define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
88 # define CFG_CPMFCR_RAMTYPE 0
89 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
91 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
95 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
96 #define CONFIG_BAUDRATE 19200
98 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
101 * select i2c support configuration
103 * Supported configurations are {none, software, hardware} drivers.
104 * If the software driver is chosen, there are some additional
105 * configuration items that the driver uses to drive the port pins.
107 #undef CONFIG_HARD_I2C /* I2C with hardware support */
108 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
109 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
110 #define CFG_I2C_SLAVE 0x7F
113 * Software (bit-bang) I2C driver configuration
115 #ifdef CONFIG_SOFT_I2C
116 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
117 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
118 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
119 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
120 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
121 else iop->pdat &= ~0x00010000
122 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
123 else iop->pdat &= ~0x00020000
124 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
125 #endif /* CONFIG_SOFT_I2C */
129 * Command line configuration.
131 #include <config_cmd_default.h>
134 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
135 #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
136 #define CONFIG_BOOTARGS "root=/dev/ram rw"
138 #if defined(CONFIG_CMD_KGDB)
139 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
140 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
141 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
142 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
143 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
146 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
148 /*-----------------------------------------------------------------------
149 * Miscellaneous configurable options
151 #define CFG_LONGHELP /* undef to save memory */
152 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
153 #if defined(CONFIG_CMD_KGDB)
154 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
156 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
158 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
159 #define CFG_MAXARGS 16 /* max number of command args */
160 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
162 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
163 #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */
165 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */
166 /* for versions < 2.4.5-pre5 */
168 #define CFG_LOAD_ADDR 0x100000 /* default load address */
170 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
172 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
174 #define CFG_RESET_ADDRESS 0x04400000
176 #define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */
178 /*-----------------------------------------------------------------------
179 * For booting Linux, the board info and command line data
180 * have to be in the first 8 MB of memory, since this is
181 * the maximum mapped by the Linux kernel during initialization.
183 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
185 /*-----------------------------------------------------------------------
186 * Start addresses for the final memory configuration (Setup by the
187 * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0.
189 #define CFG_SDRAM_BASE 0x00000000
190 #define CFG_FLASH_BASE 0xFF800000
192 #define CFG_MONITOR_BASE TEXT_BASE
193 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
194 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
196 /*-----------------------------------------------------------------------
199 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
200 #define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
201 #define CFG_MAX_FLASH_SIZE (CFG_MAX_FLASH_SECT * 0x10000) /* 4 MB */
203 #define CFG_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */
204 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
206 /* Environment in FLASH, there is little space left in Serial EEPROM */
207 #define CFG_ENV_IS_IN_FLASH 1
208 #define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
209 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x10000) /* 2. sector */
212 /*-----------------------------------------------------------------------
213 * Hard Reset Configuration Words
215 * if you change bits in the HRCW, you must also change the CFG_*
216 * defines for the various registers affected by the HRCW e.g. changing
217 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
219 #define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\
220 ( HRCW_L2CPC10 | HRCW_ISB110 ) |\
221 ( HRCW_MMR11 | HRCW_APPC10 ) |\
222 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
226 #define CFG_HRCW_SLAVE1 0
227 #define CFG_HRCW_SLAVE2 0
228 #define CFG_HRCW_SLAVE3 0
229 #define CFG_HRCW_SLAVE4 0
230 #define CFG_HRCW_SLAVE5 0
231 #define CFG_HRCW_SLAVE6 0
232 #define CFG_HRCW_SLAVE7 0
234 /*-----------------------------------------------------------------------
235 * Internal Memory Mapped Register
237 #define CFG_IMMR 0xFF000000 /* We keep original value */
239 /*-----------------------------------------------------------------------
240 * Definitions for initial stack pointer and data area (in DPRAM)
242 #define CFG_INIT_RAM_ADDR CFG_IMMR
243 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
244 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
245 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
246 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
248 /*-----------------------------------------------------------------------
249 * Internal Definitions
253 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
254 #define BOOTFLAG_WARM 0x02 /* Software reboot */
257 /*-----------------------------------------------------------------------
258 * Cache Configuration
260 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
261 #if defined(CONFIG_CMD_KGDB)
262 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
265 /*-----------------------------------------------------------------------
266 * HIDx - Hardware Implementation-dependent Registers 2-11
267 *-----------------------------------------------------------------------
268 * HID0 also contains cache control.
270 * HID1 has only read-only information - nothing to set.
272 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
274 #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
277 /*-----------------------------------------------------------------------
278 * RMR - Reset Mode Register 5-5
279 *-----------------------------------------------------------------------
280 * turn on Checkstop Reset Enable
282 #define CFG_RMR RMR_CSRE
284 /*-----------------------------------------------------------------------
285 * BCR - Bus Configuration 4-25
286 *-----------------------------------------------------------------------
288 #define CFG_BCR 0xA01C0000
290 /*-----------------------------------------------------------------------
291 * SIUMCR - SIU Module Configuration 4-31
292 *-----------------------------------------------------------------------
294 #define CFG_SIUMCR 0X4205C000
296 /*-----------------------------------------------------------------------
297 * SYPCR - System Protection Control 4-35
298 * SYPCR can only be written once after reset!
299 *-----------------------------------------------------------------------
300 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
302 #if defined (CONFIG_WATCHDOG)
303 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
304 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
306 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
307 SYPCR_SWRI|SYPCR_SWP)
308 #endif /* CONFIG_WATCHDOG */
310 /*-----------------------------------------------------------------------
311 * TMCNTSC - Time Counter Status and Control 4-40
312 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
313 * and enable Time Counter
314 *-----------------------------------------------------------------------
316 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
318 /*-----------------------------------------------------------------------
319 * PISCR - Periodic Interrupt Status and Control 4-42
320 *-----------------------------------------------------------------------
321 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
324 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
326 /*-----------------------------------------------------------------------
327 * SCCR - System Clock Control 9-8
328 *-----------------------------------------------------------------------
329 * Ensure DFBRG is Divide by 16
333 /*-----------------------------------------------------------------------
334 * RCCR - RISC Controller Configuration 13-7
335 *-----------------------------------------------------------------------
339 /*-----------------------------------------------------------------------
340 * Init Memory Controller:
342 * Bank Bus Machine PortSz Device
343 * ---- --- ------- ------ ------
344 * 0 60x GPCM 64 bit FLASH
345 * 1 60x SDRAM 64 bit SDRAM
348 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801)
349 #define CFG_OR0_PRELIM 0xFF800882
350 #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
351 #define CFG_OR1_PRELIM 0xF8002CD0
353 #define CFG_PSDMR 0x404A241A
354 #define CFG_MPTPR 0x00007400
355 #define CFG_PSRT 0x00000007
357 #endif /* __CONFIG_H */