2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_HH405 1 /* ...on a HH405 board */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
43 #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
45 #define CONFIG_BOARD_TYPES 1 /* support board types */
47 #define CONFIG_BAUDRATE 9600
48 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
50 #undef CONFIG_BOOTARGS
51 #undef CONFIG_BOOTCOMMAND
53 #define CONFIG_PREBOOT "autoupd"
55 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
57 #define CONFIG_MII 1 /* MII PHY management */
58 #define CONFIG_PHY_ADDR 0 /* PHY address */
59 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
61 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
63 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
76 #define CONFIG_MAC_PARTITION
77 #define CONFIG_DOS_PARTITION
79 #define CONFIG_SUPPORT_VFAT
81 #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
82 #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
84 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
85 #include <cmd_confdefs.h>
87 #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
88 #undef CONFIG_WATCHDOG /* watchdog disabled */
90 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
93 * Miscellaneous configurable options
95 #define CFG_LONGHELP /* undef to save memory */
96 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
98 #undef CFG_HUSH_PARSER /* use "hush" command parser */
99 #ifdef CFG_HUSH_PARSER
100 #define CFG_PROMPT_HUSH_PS2 "> "
103 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
104 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
106 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
108 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
109 #define CFG_MAXARGS 16 /* max number of command args */
110 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
112 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
114 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
116 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
118 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
119 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
121 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
122 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
123 #define CFG_BASE_BAUD 691200
124 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */
126 /* The following table includes the supported baudrates */
127 #define CFG_BAUDRATE_TABLE \
128 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
129 57600, 115200, 230400, 460800, 921600 }
131 #define CFG_LOAD_ADDR 0x100000 /* default load address */
132 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
134 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
136 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
138 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
140 #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
142 /*-----------------------------------------------------------------------
144 *-----------------------------------------------------------------------
146 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
147 #define SECTORSIZE 512
149 #define ADDR_COLUMN 1
151 #define ADDR_COLUMN_PAGE 3
153 #define NAND_ChipID_UNKNOWN 0x00
154 #define NAND_MAX_FLOORS 1
155 #define NAND_MAX_CHIPS 1
157 #define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
158 #define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
159 #define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
160 #define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
162 #define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
163 #define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
164 #define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
165 #define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
166 #define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
167 #define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
168 #define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
170 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
171 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
172 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
173 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
175 #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
177 /*-----------------------------------------------------------------------
179 *-----------------------------------------------------------------------
181 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
182 #define PCI_HOST_FORCE 1 /* configure as pci host */
183 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
185 #define CONFIG_PCI /* include pci support */
186 #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
187 #define CONFIG_PCI_PNP /* do pci plug-and-play */
188 /* resource configuration */
190 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
192 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
194 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
195 #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
196 #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
197 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
198 #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
199 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
200 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
201 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
202 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
204 /*-----------------------------------------------------------------------
206 *-----------------------------------------------------------------------
208 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
209 #undef CONFIG_IDE_LED /* no led for ide supported */
210 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
212 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
213 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
215 #define CFG_ATA_BASE_ADDR 0xF0100000
216 #define CFG_ATA_IDE0_OFFSET 0x0000
218 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
219 #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
220 #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
223 * For booting Linux, the board info and command line data
224 * have to be in the first 8 MB of memory, since this is
225 * the maximum mapped by the Linux kernel during initialization.
227 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
228 /*-----------------------------------------------------------------------
231 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
233 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
234 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
236 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
237 #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
239 #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
240 #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
241 #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
243 * The following defines are added for buggy IOP480 byte interface.
244 * All other boards should use the standard values (CPCI405 etc.)
246 #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
247 #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
248 #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
250 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
252 #if 0 /* test-only */
253 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
254 #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
257 /*-----------------------------------------------------------------------
258 * Start addresses for the final memory configuration
259 * (Set up by the startup code)
260 * Please note that CFG_SDRAM_BASE _must_ start at 0
262 #define CFG_SDRAM_BASE 0x00000000
263 #define CFG_FLASH_BASE 0xFFF80000
264 #define CFG_MONITOR_BASE TEXT_BASE
265 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
266 #define CFG_MALLOC_LEN (2 * 1024*1024) /* Reserve 2 MB for malloc() */
268 #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
269 # define CFG_RAMBOOT 1
274 /*-----------------------------------------------------------------------
275 * Environment Variable setup
277 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
278 #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
279 #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
280 /* total size of a CAT24WC16 is 2048 bytes */
282 #define CFG_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */
283 #define CFG_NVRAM_SIZE 0x8000 /* NVRAM size */
285 /*-----------------------------------------------------------------------
286 * I2C EEPROM (CAT24WC16) for environment
288 #define CONFIG_HARD_I2C /* I2c with hardware support */
289 #if 0 /* test-only */
290 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
292 #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
294 #define CFG_I2C_SLAVE 0x7F
296 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
297 #if 1 /* test-only */
298 /* CAT24WC08/16... */
299 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
300 /* mask of address bits that overflow into the "EEPROM chip address" */
301 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
302 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
303 /* 16 byte page write mode using*/
304 /* last 4 bits of the address */
306 /* CAT24WC32/64... */
307 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
308 /* mask of address bits that overflow into the "EEPROM chip address" */
309 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
310 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
311 /* 32 byte page write mode using*/
312 /* last 5 bits of the address */
314 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
315 #define CFG_EEPROM_PAGE_WRITE_ENABLE
317 /*-----------------------------------------------------------------------
318 * Cache Configuration
320 #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
321 /* have only 8kB, 16kB is save here */
322 #define CFG_CACHELINE_SIZE 32 /* ... */
323 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
324 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
327 /*-----------------------------------------------------------------------
328 * External Bus Controller (EBC) Setup
331 #define CAN_BA 0xF0000000 /* CAN Base Address */
332 #define LCD_BA 0xF1000000 /* Epson LCD Base Address */
333 #define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
334 #define CFG_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */
336 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
337 #define CFG_EBC_PB0AP 0x92015480
338 #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
340 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */
341 #define CFG_EBC_PB1AP 0x92015480
342 #define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
344 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
345 #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
346 #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
348 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
349 #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
350 #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
352 /* Memory Bank 4 (Epson LCD) initialization */
353 #define CFG_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
354 #define CFG_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
356 /*-----------------------------------------------------------------------
360 #define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
361 #define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
362 #define CFG_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
363 #define CFG_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
365 #define CFG_LCD_LOGO_MAX_SIZE (1024*1024)
367 /*-----------------------------------------------------------------------
368 * Universal Interrupt Controller (UIC) Setup
372 * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
374 #define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_EXT6)
376 /*-----------------------------------------------------------------------
380 #define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
382 /* FPGA internal regs */
383 #define CFG_FPGA_CTRL 0x000
385 /* FPGA Control Reg */
386 #define CFG_FPGA_CTRL_REV0 0x0001
387 #define CFG_FPGA_CTRL_REV1 0x0002
388 #define CFG_FPGA_CTRL_VGA0_BL 0x0004
389 #define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
390 #define CFG_FPGA_CTRL_CF_RESET 0x0040
391 #define CFG_FPGA_CTRL_PS2_PWR 0x0080
392 #define CFG_FPGA_CTRL_CF_PWR 0x0100 /* low active */
393 #define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
394 #define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */
396 #define LCD_CLK_OFF 0x0000 /* Off */
397 #define LCD_CLK_02083 0x1000 /* 2.083 MHz */
398 #define LCD_CLK_03135 0x2000 /* 3.135 MHz */
399 #define LCD_CLK_04165 0x3000 /* 4.165 MHz */
400 #define LCD_CLK_06250 0x4000 /* 6.250 MHz */
401 #define LCD_CLK_08330 0x5000 /* 8.330 MHz */
402 #define LCD_CLK_12500 0x6000 /* 12.50 MHz */
403 #define LCD_CLK_25000 0x7000 /* 25.00 MHz */
405 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
406 #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
408 /* FPGA program pin configuration */
409 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
410 #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
411 #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
412 #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
413 #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
415 /*-----------------------------------------------------------------------
416 * Definitions for initial stack pointer and data area (in data cache)
418 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
419 #define CFG_TEMP_STACK_OCM 1
421 /* On Chip Memory location */
422 #define CFG_OCM_DATA_ADDR 0xF8000000
423 #define CFG_OCM_DATA_SIZE 0x1000
424 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
425 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
427 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
428 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
429 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
431 /*-----------------------------------------------------------------------
432 * Definitions for GPIO setup (PPC405EP specific)
434 * GPIO0[0] - External Bus Controller BLAST output
435 * GPIO0[1-9] - Instruction trace outputs -> GPIO
436 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
437 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
438 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
439 * GPIO0[24-27] - UART0 control signal inputs/outputs
440 * GPIO0[28-29] - UART1 data signal input/output
441 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
443 #define CFG_GPIO0_OSRH 0x40000550
444 #define CFG_GPIO0_OSRL 0x00000110
445 #define CFG_GPIO0_ISR1H 0x00000000
446 #define CFG_GPIO0_ISR1L 0x15555440
447 #define CFG_GPIO0_TSRH 0x00000000
448 #define CFG_GPIO0_TSRL 0x00000000
449 #define CFG_GPIO0_TCR 0xF7FE0017
451 #define CFG_LCD_ENDIAN (0x80000000 >> 7)
452 #define CFG_TOUCH_RST (0x80000000 >> 9)
453 #define CFG_LCD0_RST (0x80000000 >> 30)
454 #define CFG_LCD1_RST (0x80000000 >> 31)
457 * Internal Definitions
461 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
462 #define BOOTFLAG_WARM 0x02 /* Software reboot */
465 * Default speed selection (cpu_plb_opb_ebc) in mhz.
466 * This value will be set if iic boot eprom is disabled.
469 #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
470 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
473 #define PLLMR0_DEFAULT PLLMR0_200_100_50_33
474 #define PLLMR1_DEFAULT PLLMR1_200_100_50_33
477 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
478 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
481 #endif /* __CONFIG_H */