ARMV7: AM3517/05: Add support for CraneBoard.
[oweals/u-boot.git] / include / configs / GEN860T.h
1 /*
2  * (C) Copyright 2000
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  * Keith Outwater, keith_outwater@mvis.com
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24
25 /*
26  * board/config_GEN860T.h - board specific configuration options
27  */
28
29 #ifndef __CONFIG_GEN860T_H
30 #define __CONFIG_H
31
32 /*
33  * High Level Configuration Options
34  */
35 #define CONFIG_MPC860
36 #define CONFIG_GEN860T
37
38 #define CONFIG_SYS_TEXT_BASE            0x40000000
39
40 /*
41  * Identify the board
42  */
43 #if !defined(CONFIG_SC)
44 #define CONFIG_IDENT_STRING             " B2"
45 #else
46 #define CONFIG_IDENT_STRING             " SC"
47 #endif
48
49 /*
50  * Don't depend on the RTC clock to determine clock frequency -
51  * the 860's internal rtc uses a 32.768 KHz clock which is
52  * generated by the DS1337 - and the DS1337 clock can be turned off.
53  */
54 #if !defined(CONFIG_SC)
55 #define CONFIG_8xx_GCLK_FREQ            66600000
56 #else
57 #define CONFIG_8xx_GCLK_FREQ            48000000
58 #endif
59
60 /*
61  * The RS-232 console port is on SMC1
62  */
63 #define CONFIG_8xx_CONS_SMC1
64 #define CONFIG_BAUDRATE                 38400
65
66 /*
67  * Set allowable console baud rates
68  */
69 #define CONFIG_SYS_BAUDRATE_TABLE               { 9600,         \
70                                           19200,        \
71                                           38400,        \
72                                           57600,        \
73                                           115200,       \
74                                         }
75
76 /*
77  * Print console information
78  */
79 #undef   CONFIG_SYS_CONSOLE_INFO_QUIET
80
81 /*
82  * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
83  */
84 #define CONFIG_BOOTDELAY                                5
85
86 /*
87  * Pass the clock frequency to the Linux kernel in units of MHz
88  */
89 #define CONFIG_CLOCKS_IN_MHZ
90
91 #define CONFIG_PREBOOT          \
92         "echo;echo"
93
94 #undef  CONFIG_BOOTARGS
95 #define CONFIG_BOOTCOMMAND      \
96         "bootp;" \
97         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
98         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
99         "bootm"
100
101 /*
102  * Turn off echo for serial download by default.  Allow baud rate to be changed
103  * for downloads
104  */
105 #undef  CONFIG_LOADS_ECHO
106 #define CONFIG_SYS_LOADS_BAUD_CHANGE
107
108 /*
109  * Set default load address for tftp network downloads
110  */
111 #define CONFIG_SYS_TFTP_LOADADDR                                0x01000000
112
113 /*
114  * Turn off the watchdog timer
115  */
116 #undef  CONFIG_WATCHDOG
117
118 /*
119  * Do not reboot if a panic occurs
120  */
121 #define CONFIG_PANIC_HANG
122
123 /*
124  * Enable the status LED
125  */
126 #define CONFIG_STATUS_LED
127
128 /*
129  * Reset address. We pick an address such that when an instruction
130  * is executed at that address, a machine check exception occurs
131  */
132 #define CONFIG_SYS_RESET_ADDRESS                                ((ulong) -1)
133
134 /*
135  * BOOTP options
136  */
137 #define CONFIG_BOOTP_SUBNETMASK
138 #define CONFIG_BOOTP_GATEWAY
139 #define CONFIG_BOOTP_HOSTNAME
140 #define CONFIG_BOOTP_BOOTPATH
141 #define CONFIG_BOOTP_BOOTFILESIZE
142
143
144 /*
145  * The GEN860T network interface uses the on-chip 10/100 FEC with
146  * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
147  * MII address is hardwired on the board to zero.
148  */
149 #define CONFIG_FEC_ENET
150 #define CONFIG_SYS_DISCOVER_PHY
151 #define CONFIG_MII
152 #define CONFIG_MII_INIT                 1
153 #define CONFIG_PHY_ADDR                 0
154
155 /*
156  * Set default IP stuff just to get bootstrap entries into the
157  * environment so that we can source the full default environment.
158  */
159 #define CONFIG_ETHADDR                                  9a:52:63:15:85:25
160 #define CONFIG_SERVERIP                                 10.0.4.201
161 #define CONFIG_IPADDR                                   10.0.4.111
162
163 /*
164  * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
165  * the MPC860T I2C interface.
166  */
167 #define CONFIG_SYS_I2C_EEPROM_ADDR                              0x50
168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS               6               /* 64 byte pages                */
169 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12              /* 10 mS w/ 20% margin  */
170 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN                  2               /* need 16 bit address  */
171 #define CONFIG_ENV_EEPROM_SIZE                          (32 * 1024)
172
173 /*
174  * Enable I2C and select the hardware/software driver
175  */
176 #define CONFIG_HARD_I2C         1                               /* CPM based I2C                        */
177 #undef  CONFIG_SOFT_I2C                                         /* Bit-banged I2C                       */
178
179 #ifdef CONFIG_HARD_I2C
180 #define CONFIG_SYS_I2C_SPEED            100000                  /* clock speed in Hz            */
181 #define CONFIG_SYS_I2C_SLAVE            0xFE                    /* I2C slave address            */
182 #endif
183
184 #ifdef CONFIG_SOFT_I2C
185 #define PB_SCL                          0x00000020              /* PB 26                                        */
186 #define PB_SDA                          0x00000010              /* PB 27                                        */
187 #define I2C_INIT                        (immr->im_cpm.cp_pbdir |=  PB_SCL)
188 #define I2C_ACTIVE                      (immr->im_cpm.cp_pbdir |=  PB_SDA)
189 #define I2C_TRISTATE            (immr->im_cpm.cp_pbdir &= ~PB_SDA)
190 #define I2C_READ                        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
191 #define I2C_SDA(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
192                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SDA
193 #define I2C_SCL(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
194                                                                 else    immr->im_cpm.cp_pbdat &= ~PB_SCL
195 #define I2C_DELAY                       udelay(5)               /* 1/4 I2C clock duration       */
196 #endif
197
198 /*
199  * Allow environment overwrites by anyone
200  */
201 #define CONFIG_ENV_OVERWRITE
202
203 #if !defined(CONFIG_SC)
204 /*
205  * The MPC860's internal RTC is horribly broken in rev D masks. Three
206  * internal MPC860T circuit nodes were inadvertently left floating; this
207  * causes KAPWR current in power down mode to be three orders of magnitude
208  * higher than specified in the datasheet (from 10 uA to 10 mA).  No
209  * reasonable battery can keep that kind RTC running during powerdown for any
210  * length of time, so we use an external RTC on the I2C bus instead.
211  */
212 #define CONFIG_RTC_DS1337
213 #define CONFIG_SYS_I2C_RTC_ADDR                         0x68
214
215 #else
216 /*
217  * No external RTC on SC variant, so we're stuck with the internal one.
218  */
219 #define CONFIG_RTC_MPC8xx
220 #endif
221
222 /*
223  * Power On Self Test support
224  */
225 #define CONFIG_POST                       ( CONFIG_SYS_POST_CACHE               | \
226                                                                 CONFIG_SYS_POST_MEMORY          | \
227                                                                 CONFIG_SYS_POST_CPU             | \
228                                                                 CONFIG_SYS_POST_UART            | \
229                                                                 CONFIG_SYS_POST_SPR )
230
231
232 /*
233  * Command line configuration.
234  */
235 #include <config_cmd_default.h>
236
237 #define CONFIG_CMD_ASKENV
238 #define CONFIG_CMD_DHCP
239 #define CONFIG_CMD_I2C
240 #define CONFIG_CMD_EEPROM
241 #define CONFIG_CMD_REGINFO
242 #define CONFIG_CMD_IMMAP
243 #define CONFIG_CMD_ELF
244 #define CONFIG_CMD_DATE
245 #define CONFIG_CMD_FPGA
246 #define CONFIG_CMD_MII
247 #define CONFIG_CMD_BEDBUG
248
249 #ifdef CONFIG_POST
250 #define CONFIG_CMD_DIAG
251 #endif
252
253 /*
254  * There is no IDE/PCMCIA hardware support on the board.
255  */
256 #undef  CONFIG_IDE_PCMCIA
257 #undef  CONFIG_IDE_LED
258 #undef  CONFIG_IDE_RESET
259
260 /*
261  * Enable the call to misc_init_r() for miscellaneous platform
262  * dependent initialization.
263  */
264 #define CONFIG_MISC_INIT_R
265
266 /*
267  * Enable call to last_stage_init() so we can twiddle some LEDS :)
268  */
269 #define CONFIG_LAST_STAGE_INIT
270
271 /*
272  * Virtex2 FPGA configuration support
273  */
274 #define CONFIG_FPGA_COUNT               1
275 #define CONFIG_FPGA
276 #define CONFIG_FPGA_XILINX
277 #define CONFIG_FPGA_VIRTEX2
278 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
279
280 /*
281  * Verbose help from command monitor.
282  */
283 #define CONFIG_SYS_LONGHELP
284 #if !defined(CONFIG_SC)
285 #define CONFIG_SYS_PROMPT                       "B2> "
286 #else
287 #define CONFIG_SYS_PROMPT                       "SC> "
288 #endif
289
290
291 /*
292  * Use the "hush" command parser
293  */
294 #define CONFIG_SYS_HUSH_PARSER
295 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
296
297 /*
298  * Set buffer size for console I/O
299  */
300 #if defined(CONFIG_CMD_KGDB)
301 #define CONFIG_SYS_CBSIZE                       1024
302 #else
303 #define CONFIG_SYS_CBSIZE                       256
304 #endif
305
306 /*
307  * Print buffer size
308  */
309 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
310
311 /*
312  * Maximum number of arguments that a command can accept
313  */
314 #define CONFIG_SYS_MAXARGS                      16
315
316 /*
317  * Boot argument buffer size
318  */
319 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
320
321 /*
322  * Default memory test range
323  */
324 #define CONFIG_SYS_MEMTEST_START        0x0100000
325 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START  + (128 * 1024))
326
327 /*
328  * Select the more full-featured memory test
329  */
330 #define CONFIG_SYS_ALT_MEMTEST
331
332 /*
333  * Default load address
334  */
335 #define CONFIG_SYS_LOAD_ADDR            0x01000000
336
337 /*
338  * Set decrementer frequency (1 ms ticks)
339  */
340 #define CONFIG_SYS_HZ                           1000
341
342 /*
343  * Device memory map (after SDRAM remap to 0x0):
344  *
345  * CS           Device                          Base Addr       Size
346  * ----------------------------------------------------
347  * CS0*         Flash                           0x40000000      64 M
348  * CS1*         SDRAM                           0x00000000      16 M
349  * CS2*         Disk-On-Chip            0x50000000      32 K
350  * CS3*         FPGA                            0x60000000      64 M
351  * CS4*         SelectMap                       0x70000000      32 K
352  * CS5*         Mil-Std 1553 I/F        0x80000000      32 K
353  * CS6*         Unused
354  * CS7*         Unused
355  * IMMR         860T Registers          0xfff00000
356  */
357
358 /*
359  * Base addresses and block sizes
360  */
361 #define CONFIG_SYS_IMMR                 0xFF000000
362
363 #define SDRAM_BASE                      0x00000000
364 #define SDRAM_SIZE                      (64 * 1024 * 1024)
365
366 #define FLASH_BASE                      0x40000000
367 #define FLASH_SIZE                      (16 * 1024 * 1024)
368
369 #define DOC_BASE                        0x50000000
370 #define DOC_SIZE                        (32 * 1024)
371
372 #define FPGA_BASE                       0x60000000
373 #define FPGA_SIZE                       (64 * 1024 * 1024)
374
375 #define SELECTMAP_BASE          0x70000000
376 #define SELECTMAP_SIZE          (32 * 1024)
377
378 #define M1553_BASE                      0x80000000
379 #define M1553_SIZE                      (64 * 1024)
380
381 /*
382  * Definitions for initial stack pointer and data area (in DPRAM)
383  */
384 #define CONFIG_SYS_INIT_RAM_ADDR                CONFIG_SYS_IMMR
385 #define CONFIG_SYS_INIT_RAM_SIZE                0x2F00  /* Size of used area in DPRAM           */
386 #define CONFIG_SYS_INIT_DATA_SIZE               64      /* # bytes reserved for initial data*/
387 #define CONFIG_SYS_GBL_DATA_OFFSET              (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
388 #define CONFIG_SYS_INIT_SP_OFFSET               CONFIG_SYS_GBL_DATA_OFFSET
389
390 /*
391  * Start addresses for the final memory configuration
392  * (Set up by the startup code)
393  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
394  */
395 #define CONFIG_SYS_SDRAM_BASE                   SDRAM_BASE
396
397 /*
398  * FLASH organization
399  */
400 #define CONFIG_SYS_FLASH_BASE                   FLASH_BASE
401 #define CONFIG_SYS_FLASH_SIZE                   FLASH_SIZE
402 #define CONFIG_SYS_FLASH_SECT_SIZE              (128 * 1024)
403 #define CONFIG_SYS_MAX_FLASH_BANKS              1
404 #define CONFIG_SYS_MAX_FLASH_SECT               128
405
406 /*
407  * The timeout values are for an entire chip and are in milliseconds.
408  * Yes I know that the write timeout is huge.  Accroding to the
409  * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
410  * case VCC and temp after 100K programming cycles.  It works out
411  * to 280 minutes (might as well be forever).
412  */
413 #define CONFIG_SYS_FLASH_ERASE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 5000)
414 #define CONFIG_SYS_FLASH_WRITE_TOUT     (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1)
415
416 /*
417  * Allow direct writes to FLASH from tftp transfers (** dangerous **)
418  */
419 #define CONFIG_SYS_DIRECT_FLASH_TFTP
420
421 /*
422  * Reserve memory for U-Boot.
423  */
424 #define CONFIG_SYS_MAX_UBOOT_SECTS              4
425 #define CONFIG_SYS_MONITOR_LEN                  (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE)
426 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
427
428 /*
429  * Select environment placement.  NOTE that u-boot.lds must
430  * be edited if this is changed!
431  */
432 #undef  CONFIG_ENV_IS_IN_FLASH
433 #define CONFIG_ENV_IS_IN_EEPROM
434
435 #if defined(CONFIG_ENV_IS_IN_EEPROM)
436 #define CONFIG_ENV_SIZE                 (2 * 1024)
437 #define CONFIG_ENV_OFFSET                       (CONFIG_ENV_EEPROM_SIZE - (8 * 1024))
438 #else
439 #define CONFIG_ENV_SIZE                 0x1000
440 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SIZE
441
442 /*
443  * This ultimately gets passed right into the linker script, so we have to
444  * use a number :(
445  */
446 #define CONFIG_ENV_OFFSET                       0x060000
447 #endif
448
449 /*
450  * Reserve memory for malloc()
451  */
452 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
453
454 /*
455  * For booting Linux, the board info and command line data
456  * have to be in the first 8 MB of memory, since this is
457  * the maximum mapped by the Linux kernel during initialization.
458  */
459 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
460
461 /*
462  * Cache Configuration
463  */
464 #define CONFIG_SYS_CACHELINE_SIZE               16      /* For all MPC8xx CPUs                          */
465 #if defined(CONFIG_CMD_KGDB)
466 #define CONFIG_SYS_CACHELINE_SHIFT              4       /* log base 2 of above value            */
467 #endif
468
469 /*------------------------------------------------------------------------
470  * SYPCR - System Protection Control                                                    UM 11-9
471  * -----------------------------------------------------------------------
472  * SYPCR can only be written once after reset!
473  *
474  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
475  */
476 #if defined(CONFIG_WATCHDOG)
477 #define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
478                                           SYPCR_BMT     | \
479                                           SYPCR_BME     | \
480                                           SYPCR_SWF     | \
481                                           SYPCR_SWE     | \
482                                           SYPCR_SWRI    | \
483                                           SYPCR_SWP               \
484                                         )
485 #else
486 #define CONFIG_SYS_SYPCR        ( SYPCR_SWTC    | \
487                                           SYPCR_BMT     | \
488                                           SYPCR_BME     | \
489                                           SYPCR_SWF     | \
490                                           SYPCR_SWP               \
491                                         )
492 #endif
493
494 /*-----------------------------------------------------------------------
495  * SIUMCR - SIU Module Configuration                                                    UM 11-6
496  *-----------------------------------------------------------------------
497  * Set debug pin mux, enable SPKROUT and GPLB5*.
498  */
499 #define CONFIG_SYS_SIUMCR       ( SIUMCR_DBGC11 | \
500                                           SIUMCR_DBPC11 | \
501                                           SIUMCR_MLRC11 | \
502                                           SIUMCR_GB5E     \
503                                         )
504
505 /*-----------------------------------------------------------------------
506  * TBSCR - Time Base Status and Control                                                 UM 11-26
507  *-----------------------------------------------------------------------
508  * Clear Reference Interrupt Status, Timebase freeze enabled
509  */
510 #define CONFIG_SYS_TBSCR        ( TBSCR_REFA | \
511                                           TBSCR_REFB | \
512                                           TBSCR_TBF        \
513                                         )
514
515 /*-----------------------------------------------------------------------
516  * RTCSC - Real-Time Clock Status and Control Register                  UM 11-27
517  *-----------------------------------------------------------------------
518  */
519 #define CONFIG_SYS_RTCSC        ( RTCSC_SEC     | \
520                                           RTCSC_ALR | \
521                                           RTCSC_RTF | \
522                                           RTCSC_RTE       \
523                                         )
524
525 /*-----------------------------------------------------------------------
526  * PISCR - Periodic Interrupt Status and Control                                UM 11-31
527  *-----------------------------------------------------------------------
528  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
529  */
530 #define CONFIG_SYS_PISCR        ( PISCR_PS              | \
531                                           PISCR_PITF      \
532                                         )
533
534 /*-----------------------------------------------------------------------
535  * PLPRCR - PLL, Low-Power, and Reset Control Register                  UM 15-30
536  *-----------------------------------------------------------------------
537  * Reset PLL lock status sticky bit, timer expired status bit and timer
538  * interrupt status bit. Set MF for 1:2:1 mode.
539  */
540 #define CONFIG_SYS_PLPRCR       ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)    | \
541                                           PLPRCR_SPLSS  | \
542                                           PLPRCR_TEXPS  | \
543                                           PLPRCR_TMIST    \
544                                         )
545
546 /*-----------------------------------------------------------------------
547  * SCCR - System Clock and reset Control Register                               UM 15-27
548  *-----------------------------------------------------------------------
549  * Set clock output, timebase and RTC source and divider,
550  * power management and some other internal clocks
551  */
552 #define SCCR_MASK   SCCR_EBDF11
553
554 #if !defined(CONFIG_SC)
555 #define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
556                                           SCCR_COM00            |       /* full strength CLKOUT */ \
557                                           SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
558                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
559                                           SCCR_DFNL000          | \
560                                           SCCR_DFNH000            \
561                                         )
562 #else
563 #define CONFIG_SYS_SCCR ( SCCR_TBS                      |       /* timebase = GCLK/2    */ \
564                                           SCCR_COM00            |       /* full strength CLKOUT */ \
565                                           SCCR_DFSYNC00 |       /* SYNCLK / 1 (normal)  */ \
566                                           SCCR_DFBRG00          |       /* BRGCLK / 1 (normal)  */ \
567                                           SCCR_DFNL000          | \
568                                           SCCR_DFNH000          | \
569                                           SCCR_RTDIV            | \
570                                           SCCR_RTSEL              \
571                                         )
572 #endif
573
574 /*-----------------------------------------------------------------------
575  * DER - Debug Enable Register                                                                  UM 37-46
576  *-----------------------------------------------------------------------
577  * Mask all events that can cause entry into debug mode
578  */
579 #define CONFIG_SYS_DER                          0
580
581 /*
582  * Initialize Memory Controller:
583  *
584  * BR0 and OR0 (FLASH memory)
585  */
586 #define FLASH_BASE0_PRELIM      FLASH_BASE
587
588 /*
589  * Flash address mask
590  */
591 #define CONFIG_SYS_PRELIM_OR_AM 0xfe000000
592
593 /*
594  * FLASH timing:
595  * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
596  */
597 #define CONFIG_SYS_OR_TIMING_FLASH      ( OR_CSNT_SAM   | \
598                                                           OR_ACS_DIV2   | \
599                                                           OR_BI                 | \
600                                                           OR_SCY_2_CLK  | \
601                                                           OR_TRLX               | \
602                                                           OR_EHTR                 \
603                                                         )
604
605 #define CONFIG_SYS_OR0_PRELIM   ( CONFIG_SYS_PRELIM_OR_AM               | \
606                                                   CONFIG_SYS_OR_TIMING_FLASH      \
607                                                 )
608
609 #define CONFIG_SYS_BR0_PRELIM   ( (FLASH_BASE0_PRELIM & BR_BA_MSK)      | \
610                                                   BR_MS_GPCM                                            | \
611                                                   BR_PS_8                                                       | \
612                                                   BR_V                                                            \
613                                                 )
614
615 /*
616  * SDRAM configuration
617  */
618 #define CONFIG_SYS_OR1_AM       0xfc000000
619 #define CONFIG_SYS_OR1          ( (CONFIG_SYS_OR1_AM & OR_AM_MSK)       | \
620                                           OR_CSNT_SAM                             \
621                                         )
622
623 #define CONFIG_SYS_BR1          ( (SDRAM_BASE & BR_BA_MSK)      | \
624                                           BR_MS_UPMA                            | \
625                                           BR_PS_32                                      | \
626                                           BR_V                                            \
627                                         )
628
629 /*
630  * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
631  * of 256 MBit SDRAM
632  */
633 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16
634
635 /*
636  * Periodic timer for refresh @ 33 MHz system clock
637  */
638 #define CONFIG_SYS_MAMR_PTA     64
639
640 /*
641  * MAMR settings for SDRAM
642  */
643 #define CONFIG_SYS_MAMR_8COL    ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)       | \
644                                                   MAMR_PTAE                             | \
645                                                   MAMR_AMA_TYPE_1                       | \
646                                                   MAMR_DSA_1_CYCL                       | \
647                                                   MAMR_G0CLA_A10                        | \
648                                                   MAMR_RLFA_1X                          | \
649                                                   MAMR_WLFA_1X                          | \
650                                                   MAMR_TLFA_4X                            \
651                                                 )
652
653 /*
654  * CS2* configuration for Disk On Chip:
655  * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
656  * no burst.
657  */
658 #define CONFIG_SYS_OR2_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
659                                                   OR_CSNT_SAM                           | \
660                                                   OR_ACS_DIV2                           | \
661                                                   OR_BI                                         | \
662                                                   OR_SCY_2_CLK                          | \
663                                                   OR_TRLX                                       | \
664                                                   OR_EHTR                                         \
665                                                 )
666
667 #define CONFIG_SYS_BR2_PRELIM   ( (DOC_BASE & BR_BA_MSK)        | \
668                                                   BR_PS_8                                       | \
669                                                   BR_MS_GPCM                            | \
670                                                   BR_V                                            \
671                                                 )
672
673 /*
674  * CS3* configuration for FPGA:
675  * 33 MHz bus with SCY=15, no burst.
676  * The FPGA uses TA and TEA to terminate bus cycles, but we
677  * clear SETA and set the cycle length to a large number so that
678  * the cycle will still complete even if there is a configuration
679  * error that prevents TA from asserting on FPGA accesss.
680  */
681 #define CONFIG_SYS_OR3_PRELIM   ( (0xfc000000 & OR_AM_MSK)  | \
682                                                   OR_SCY_15_CLK                         | \
683                                                   OR_BI                                   \
684                                                 )
685
686 #define CONFIG_SYS_BR3_PRELIM   ( (FPGA_BASE & BR_BA_MSK)       | \
687                                                   BR_PS_32                                      | \
688                                                   BR_MS_GPCM                            | \
689                                                   BR_V                                            \
690                                                 )
691 /*
692  * CS4* configuration for FPGA SelectMap configuration interface.
693  * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
694  * of GCLK1_50
695  */
696 #define CONFIG_SYS_OR4_PRELIM   ( (0xffff0000 & OR_AM_MSK)      | \
697                                                   OR_G5LS                                               | \
698                                                   OR_BI                                                   \
699                                                 )
700
701 #define CONFIG_SYS_BR4_PRELIM   ( (SELECTMAP_BASE & BR_BA_MSK)  | \
702                                                   BR_PS_8                                               | \
703                                                   BR_MS_UPMB                                    | \
704                                                   BR_V                                                    \
705                                                 )
706
707 /*
708  * CS5* configuration for Mil-Std 1553 databus interface.
709  * 33 MHz bus, GPCM, no burst.
710  * The 1553 interface  uses TA and TEA to terminate bus cycles,
711  * but we clear SETA and set the cycle length to a large number so that
712  * the cycle will still complete even if there is a configuration
713  * error that prevents TA from asserting on FPGA accesss.
714  */
715 #define CONFIG_SYS_OR5_PRELIM   ( (0xffff0000 & OR_AM_MSK)  | \
716                                                   OR_SCY_15_CLK                         | \
717                                                   OR_EHTR                                       | \
718                                                   OR_TRLX                                       | \
719                                                   OR_CSNT_SAM                           | \
720                                                   OR_BI                                           \
721                                                 )
722
723 #define CONFIG_SYS_BR5_PRELIM   ( (M1553_BASE & BR_BA_MSK)      | \
724                                                   BR_PS_16                                      | \
725                                                   BR_MS_GPCM                            | \
726                                                   BR_V                                            \
727                                                 )
728
729 /*
730  * FEC interrupt assignment
731  */
732 #define FEC_INTERRUPT   SIU_LEVEL1
733
734 /*
735  * Sanity checks
736  */
737 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
738 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
739 #endif
740
741 #endif  /* __CONFIG_GEN860T_H */