2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * board/config.h - configuration options, board specific
16 * High Level Configuration Options
20 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */
21 #define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */
23 #define CONFIG_SYS_TEXT_BASE 0x40000000
25 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
26 #define CONFIG_SYS_SMC_RXBUFLEN 128
27 #define CONFIG_SYS_MAXIDLE 10
28 #define CONFIG_BAUDRATE 115200
30 #define CONFIG_BOOTCOUNT_LIMIT
32 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
34 #define CONFIG_BOARD_TYPES 1 /* support board types */
36 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
38 #undef CONFIG_BOOTARGS
40 #define CONFIG_EXTRA_ENV_SETTINGS \
42 "nfsargs=setenv bootargs root=/dev/nfs rw " \
43 "nfsroot=${serverip}:${rootpath}\0" \
44 "ramargs=setenv bootargs root=/dev/ram rw\0" \
45 "addip=setenv bootargs ${bootargs} " \
46 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
47 ":${hostname}:${netdev}:off panic=1\0" \
48 "flash_nfs=run nfsargs addip;" \
49 "bootm ${kernel_addr}\0" \
50 "flash_self=run ramargs addip;" \
51 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
52 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
53 "rootpath=/opt/eldk/ppc_8xx\0" \
54 "hostname=FPS860L\0" \
55 "bootfile=FPS860L/uImage\0" \
56 "fdt_addr=40040000\0" \
57 "kernel_addr=40060000\0" \
58 "ramdisk_addr=40200000\0" \
59 "u-boot=FPS860L/u-image.bin\0" \
60 "load=tftp 200000 ${u-boot}\0" \
61 "update=prot off 40000000 +${filesize};" \
62 "era 40000000 +${filesize};" \
63 "cp.b 200000 40000000 ${filesize};" \
64 "sete filesize;save\0" \
66 #define CONFIG_BOOTCOMMAND "run flash_self"
68 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
69 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
71 #undef CONFIG_WATCHDOG /* watchdog disabled */
76 #define CONFIG_BOOTP_SUBNETMASK
77 #define CONFIG_BOOTP_GATEWAY
78 #define CONFIG_BOOTP_HOSTNAME
79 #define CONFIG_BOOTP_BOOTPATH
80 #define CONFIG_BOOTP_BOOTFILESIZE
81 #define CONFIG_BOOTP_SUBNETMASK
82 #define CONFIG_BOOTP_GATEWAY
83 #define CONFIG_BOOTP_HOSTNAME
84 #define CONFIG_BOOTP_NISDOMAIN
85 #define CONFIG_BOOTP_BOOTPATH
86 #define CONFIG_BOOTP_DNS
87 #define CONFIG_BOOTP_DNS2
88 #define CONFIG_BOOTP_SEND_HOSTNAME
89 #define CONFIG_BOOTP_NTPSERVER
90 #define CONFIG_BOOTP_TIMEOFFSET
92 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
95 * Command line configuration.
97 #include <config_cmd_default.h>
99 #define CONFIG_CMD_ASKENV
100 #define CONFIG_CMD_DATE
101 #define CONFIG_CMD_DHCP
102 #define CONFIG_CMD_JFFS2
103 #define CONFIG_CMD_NFS
104 #define CONFIG_CMD_SNTP
107 #define CONFIG_NETCONSOLE
111 * Miscellaneous configurable options
113 #define CONFIG_SYS_LONGHELP /* undef to save memory */
115 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
116 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
118 #if defined(CONFIG_CMD_KGDB)
119 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
121 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
123 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
124 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
125 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
127 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
128 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
130 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
132 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
135 * Low Level Configuration Settings
136 * (address mappings, register initial values, etc.)
137 * You should know what you are doing if you make changes here.
139 /*-----------------------------------------------------------------------
140 * Internal Memory Mapped Register
142 #define CONFIG_SYS_IMMR 0xFFF00000
144 /*-----------------------------------------------------------------------
145 * Definitions for initial stack pointer and data area (in DPRAM)
147 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
148 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
149 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
150 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
152 /*-----------------------------------------------------------------------
153 * Start addresses for the final memory configuration
154 * (Set up by the startup code)
155 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
157 #define CONFIG_SYS_SDRAM_BASE 0x00000000
158 #define CONFIG_SYS_FLASH_BASE 0x40000000
159 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
161 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
164 * For booting Linux, the board info and command line data
165 * have to be in the first 8 MB of memory, since this is
166 * the maximum mapped by the Linux kernel during initialization.
168 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
170 /*-----------------------------------------------------------------------
174 /* use CFI flash driver */
175 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
176 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
177 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
178 #define CONFIG_SYS_FLASH_EMPTY_INFO
179 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
180 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
181 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
183 #define CONFIG_ENV_IS_IN_FLASH 1
184 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
185 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
187 /* Address and size of Redundant Environment Sector */
188 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
189 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
191 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
193 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
195 /*-----------------------------------------------------------------------
196 * Dynamic MTD partition support
198 #define CONFIG_CMD_MTDPARTS
199 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
200 #define CONFIG_FLASH_CFI_MTD
201 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
203 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
209 /*-----------------------------------------------------------------------
210 * Hardware Information Block
212 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
213 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
214 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
216 /*-----------------------------------------------------------------------
217 * Cache Configuration
219 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
220 #if defined(CONFIG_CMD_KGDB)
221 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
224 /*-----------------------------------------------------------------------
225 * SYPCR - System Protection Control 11-9
226 * SYPCR can only be written once after reset!
227 *-----------------------------------------------------------------------
228 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
230 #if defined(CONFIG_WATCHDOG)
231 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
232 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
234 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
237 /*-----------------------------------------------------------------------
238 * SIUMCR - SIU Module Configuration 11-6
239 *-----------------------------------------------------------------------
240 * PCMCIA config., multi-function pin tri-state
242 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
244 /*-----------------------------------------------------------------------
245 * TBSCR - Time Base Status and Control 11-26
246 *-----------------------------------------------------------------------
247 * Clear Reference Interrupt Status, Timebase freezing enabled
249 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
251 /*-----------------------------------------------------------------------
252 * RTCSC - Real-Time Clock Status and Control Register 11-27
253 *-----------------------------------------------------------------------
255 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
257 /*-----------------------------------------------------------------------
258 * PISCR - Periodic Interrupt Status and Control 11-31
259 *-----------------------------------------------------------------------
260 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
262 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
264 /*-----------------------------------------------------------------------
265 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
266 *-----------------------------------------------------------------------
267 * Reset PLL lock status sticky bit, timer expired status bit and timer
268 * interrupt status bit - leave PLL multiplication factor unchanged !
270 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
272 /*-----------------------------------------------------------------------
273 * SCCR - System Clock and reset Control Register 15-27
274 *-----------------------------------------------------------------------
275 * Set clock output, timebase and RTC source and divider,
276 * power management and some other internal clocks
278 #define SCCR_MASK SCCR_EBDF11
279 #define CONFIG_SYS_SCCR (SCCR_TBS | \
280 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
281 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
284 /*-----------------------------------------------------------------------
286 *-----------------------------------------------------------------------
289 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
290 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
291 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
292 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
293 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
294 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
295 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
296 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
298 /*-----------------------------------------------------------------------
300 *-----------------------------------------------------------------------
303 #define CONFIG_SYS_DER 0
306 * Init Memory Controller:
308 * BR0/1 and OR0/1 (FLASH)
311 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
312 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
314 /* used to re-map FLASH both when starting from SRAM or FLASH:
315 * restrict access enough to keep SRAM working (if any)
316 * but not too much to meddle with FLASH accesses
318 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
319 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
324 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
325 OR_SCY_3_CLK | OR_EHTR | OR_BI)
327 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
328 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
329 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
331 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
332 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
333 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
336 * BR2/3 and OR2/3 (SDRAM)
339 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
340 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
341 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
343 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
344 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
346 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
347 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
349 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
350 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
353 * Memory Periodic Timer Prescaler
355 * The Divider for PTA (refresh timer) configuration is based on an
356 * example SDRAM configuration (64 MBit, one bank). The adjustment to
357 * the number of chip selects (NCS) and the actually needed refresh
358 * rate is done by setting MPTPR.
360 * PTA is calculated from
361 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
363 * gclk CPU clock (not bus clock!)
364 * Trefresh Refresh cycle * 4 (four word bursts used)
366 * 4096 Rows from SDRAM example configuration
367 * 1000 factor s -> ms
368 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
369 * 4 Number of refresh cycles per period
370 * 64 Refresh cycle in ms per number of rows
371 * --------------------------------------------
372 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
374 * 50 MHz => 50.000.000 / Divider = 98
375 * 66 Mhz => 66.000.000 / Divider = 129
376 * 80 Mhz => 80.000.000 / Divider = 156
379 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
380 #define CONFIG_SYS_MAMR_PTA 98
383 * For 16 MBit, refresh rates could be 31.3 us
384 * (= 64 ms / 2K = 125 / quad bursts).
385 * For a simpler initialization, 15.6 us is used instead.
387 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
388 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
390 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
391 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
393 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
394 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
395 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
398 * MAMR settings for SDRAM
402 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
403 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
404 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
406 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
407 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
408 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
410 #define CONFIG_SCC1_ENET
412 /* pass open firmware flat tree */
413 #define CONFIG_OF_LIBFDT 1
414 #define CONFIG_OF_BOARD_SETUP 1
415 #define CONFIG_HWCONFIG 1
417 #endif /* __CONFIG_H */