3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 #include <galileo/core.h>
35 #include "../board/evb64260/local.h"
38 * High Level Configuration Options
42 #define CONFIG_EVB64260 1 /* this is an EVB64260 board */
43 #define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
45 #define CONFIG_SYS_TEXT_BASE 0xfff00000
47 #define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
49 #undef CONFIG_ECC /* enable ECC support */
50 /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
52 /* which initialization functions to call for this board */
53 #define CONFIG_MISC_INIT_R 1
54 #define CONFIG_BOARD_EARLY_INIT_F 1
56 #ifndef CONFIG_EVB64260_750CX
57 #define CONFIG_SYS_BOARD_NAME "EVB64260"
59 #define CONFIG_SYS_BOARD_NAME "EVB64260-750CX"
62 #define CONFIG_SYS_HUSH_PARSER
63 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
66 * The following defines let you select what serial you want to use
67 * for your console driver.
70 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
71 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
74 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
75 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
78 #define CONFIG_MPSC_PORT 0
80 #define CONFIG_NET_MULTI /* attempt all available adapters */
82 /* define this if you want to enable GT MAC filtering */
83 #define CONFIG_GT_USE_MAC_HASH_TABLE
85 #undef CONFIG_ETHER_PORT_MII /* use RMII */
88 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
90 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
92 #define CONFIG_ZERO_BOOTDELAY_CHECK
94 #undef CONFIG_BOOTARGS
95 #define CONFIG_BOOTCOMMAND \
97 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
98 "ip=$ipaddr:$serverip:$gatewayip:" \
99 "$netmask:$hostname:eth0:none; && " \
102 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
103 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
105 #undef CONFIG_WATCHDOG /* watchdog disabled */
106 #undef CONFIG_ALTIVEC /* undef to disable */
111 #define CONFIG_BOOTP_SUBNETMASK
112 #define CONFIG_BOOTP_GATEWAY
113 #define CONFIG_BOOTP_HOSTNAME
114 #define CONFIG_BOOTP_BOOTPATH
115 #define CONFIG_BOOTP_BOOTFILESIZE
119 * Command line configuration.
121 #include <config_cmd_default.h>
123 #define CONFIG_CMD_ASKENV
127 * Miscellaneous configurable options
129 #define CONFIG_SYS_LONGHELP /* undef to save memory */
130 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
131 #if defined(CONFIG_CMD_KGDB)
132 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
134 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
136 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
137 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
138 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
140 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
141 #define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
143 #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
145 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
146 #define CONFIG_SYS_BUS_CLK 100000000 /* 100 MHz */
148 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
150 #ifdef CONFIG_EVB64260_750CX
152 #define CONFIG_SYS_BROKEN_CL2
156 * Low Level Configuration Settings
157 * (address mappings, register initial values, etc.)
158 * You should know what you are doing if you make changes here.
161 /*-----------------------------------------------------------------------
162 * Definitions for initial stack pointer and data area
164 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
165 #define CONFIG_SYS_INIT_RAM_END 0x1000
166 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
167 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
168 #define CONFIG_SYS_INIT_RAM_LOCK
171 /*-----------------------------------------------------------------------
172 * Start addresses for the final memory configuration
173 * (Set up by the startup code)
174 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
176 #define CONFIG_SYS_SDRAM_BASE 0x00000000
177 #define CONFIG_SYS_FLASH_BASE 0xfff00000
178 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
179 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
180 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
181 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
183 /* areas to map different things with the GT in physical space */
184 #define CONFIG_SYS_DRAM_BANKS 4
185 #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
187 /* What to put in the bats. */
188 #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
190 /* Peripheral Device section */
191 #define CONFIG_SYS_GT_REGS 0xf8000000
192 #define CONFIG_SYS_DEV_BASE 0xfc000000
194 #define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
195 #define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
196 #define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
197 #define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
199 #define CONFIG_SYS_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */
200 #define CONFIG_SYS_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */
201 #define CONFIG_SYS_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */
202 #define CONFIG_SYS_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */
204 #define CONFIG_SYS_DEV0_PAR 0x20205093
205 #define CONFIG_SYS_DEV1_PAR 0xcfcfffff
206 #define CONFIG_SYS_DEV2_PAR 0xc0059bd4
207 #define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c
208 #define CONFIG_SYS_32BIT_BOOT_PAR 0xc4a8241c
209 /* c 4 a 8 2 4 1 c */
210 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
211 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
212 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
213 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
215 #if 0 /* Wrong?? NTL */
216 #define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
217 /* DMAAck[1:0] GNT0[1:0] */
219 #define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
220 /* REQ0[1:0] GNT0[1:0] */
222 #define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
223 /* DMAReq[4] DMAAck[4] WDNMI WDE */
224 #if 0 /* Wrong?? NTL */
225 #define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
226 /* DMAAck[1:0] GNT1[1:0] */
228 #define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
229 /* GPP[22] (RS232IntB or PCI1Int) */
230 /* GPP[21] (RS323IntA) */
232 /* REQ1[1:0] GNT1[1:0] */
235 #if 0 /* Wrong?? NTL */
236 # define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
237 /* GPP[27:26] Int[1:0] */
239 # define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
240 /* GPP[29] (PCI1Int) */
242 /* GPP[27] (PCI0Int) */
243 /* GPP[26] (RtcInt or PCI1Int) */
247 # define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
249 #if 0 /* Wrong?? - NTL */
250 # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
252 # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
257 # define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
258 /* idmas use buffer 1,1
262 normal load (see also ifdef HVL)
263 standard SDRAM (see also ifdef REG)
264 non staggered refresh */
265 /* 31:26 25 23 20 19 18 16 */
266 /* 110110 00 111 0 0 00 1 */
267 /* refresh_count=0x200
268 phisical interleaving disable
269 virtual interleaving enable */
274 #define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
275 #define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
276 #define CONFIG_SYS_INIT_CHAN1
277 #define CONFIG_SYS_INIT_CHAN2
279 #define SRAM_BASE CONFIG_SYS_DEV0_SPACE
280 #define SRAM_SIZE 0x00100000 /* 1 MB of sram */
283 /*-----------------------------------------------------------------------
285 *-----------------------------------------------------------------------
288 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
289 #define PCI_HOST_FORCE 1 /* configure as pci host */
290 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
292 #define CONFIG_PCI /* include pci support */
293 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
294 #define CONFIG_PCI_PNP /* do pci plug-and-play */
296 /* PCI MEMORY MAP section */
297 #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
298 #define CONFIG_SYS_PCI0_MEM_SIZE _128M
299 #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
300 #define CONFIG_SYS_PCI1_MEM_SIZE _128M
302 #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
303 #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
306 /* PCI I/O MAP section */
307 #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
308 #define CONFIG_SYS_PCI0_IO_SIZE _16M
309 #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
310 #define CONFIG_SYS_PCI1_IO_SIZE _16M
312 #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
313 #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
314 #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
315 #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
318 * NS16550 Configuration
320 #define CONFIG_SYS_NS16550
322 #define CONFIG_SYS_NS16550_REG_SIZE -4
324 #define CONFIG_SYS_NS16550_CLK 3686400
326 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_DUART_IO + 0)
327 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_DUART_IO + 0x20)
329 /*----------------------------------------------------------------------
330 * Initial BAT mappings
334 * 1) GUARDED and WRITE_THRU not allowed in IBATS
335 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
339 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
340 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
341 #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
342 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
345 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
346 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
347 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
348 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
350 /* PCI0, PCI1 in one BAT */
351 #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
352 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
353 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
354 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
356 /* GT regs, bootrom, all the devices, PCI I/O */
357 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
358 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
359 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
360 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
362 /* I2C speed and slave address (for compatability) defaults */
363 #define CONFIG_SYS_I2C_SPEED 400000
364 #define CONFIG_SYS_I2C_SLAVE 0x7F
366 /* I2C addresses for the two DIMM SPD chips */
367 #ifndef CONFIG_EVB64260_750CX
368 #define DIMM0_I2C_ADDR 0x56
369 #define DIMM1_I2C_ADDR 0x54
370 #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
371 #define DIMM0_I2C_ADDR 0x54
372 #define DIMM1_I2C_ADDR 0x54
376 * For booting Linux, the board info and command line data
377 * have to be in the first 8 MB of memory, since this is
378 * the maximum mapped by the Linux kernel during initialization.
380 #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
382 /*-----------------------------------------------------------------------
385 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
386 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
388 #define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
389 #define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */
391 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
392 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
393 #define CONFIG_SYS_FLASH_CFI 1
395 #define CONFIG_ENV_IS_IN_FLASH 1
396 #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
397 #define CONFIG_ENV_SECT_SIZE 0x10000
398 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
400 /*-----------------------------------------------------------------------
401 * Cache Configuration
403 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
404 #if defined(CONFIG_CMD_KGDB)
405 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
408 /*-----------------------------------------------------------------------
409 * L2CR setup -- make sure this is right for your board!
410 * look in include/74xx_7xx.h for the defines used here
413 #define CONFIG_SYS_L2
418 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
419 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
422 #define L2_ENABLE (L2_INIT | L2CR_L2E)
424 #define CONFIG_SYS_BOARD_ASM_INIT 1
427 #endif /* __CONFIG_H */