3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_ERIC 1 /* ...on a ERIC board */
40 #define CONFIG_SYS_TEXT_BASE 0xFFFC0000
42 #define CONFIG_BOARD_EARLY_INIT_F 1 /* run board_early_init_f() */
44 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
47 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
50 #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
53 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use I2C RTC X1240 for environment vars */
54 #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
55 #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
56 #endif /* total size of a X1240 is 2048 bytes */
58 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
59 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
60 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
61 #define CONFIG_SYS_I2C_SLAVE 0x7F
63 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* X1240 has two I2C slave addresses, one for EEPROM */
64 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* address length for the eeprom */
65 #define CONFIG_I2C_RTC 1 /* we have a Xicor X1240 RTC */
66 #define CONFIG_SYS_I2C_RTC_ADDR 0x6F /* and one for RTC */
68 #ifdef CONFIG_ENV_IS_IN_FLASH
69 #undef CONFIG_ENV_IS_IN_NVRAM
70 #undef CONFIG_ENV_IS_IN_EEPROM
72 #ifdef CONFIG_ENV_IS_IN_NVRAM
73 #undef CONFIG_ENV_IS_IN_FLASH
74 #undef CONFIG_ENV_IS_IN_EEPROM
76 #ifdef CONFIG_ENV_IS_IN_EEPROM
77 #undef CONFIG_ENV_IS_IN_NVRAM
78 #undef CONFIG_ENV_IS_IN_FLASH
83 #define CONFIG_BAUDRATE 115200
84 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
87 #define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
89 #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
92 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs " \
93 "nfsroot=192.168.1.2:/eric_root_devel " \
94 "ip=192.168.1.22:192.168.1.2"
96 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
97 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
99 #define CONFIG_PPC4xx_EMAC
100 #define CONFIG_MII 1 /* MII PHY management */
101 #define CONFIG_PHY_ADDR 1 /* PHY address */
102 #define CONFIG_NET_MULTI
108 #define CONFIG_BOOTP_BOOTFILESIZE
109 #define CONFIG_BOOTP_BOOTPATH
110 #define CONFIG_BOOTP_GATEWAY
111 #define CONFIG_BOOTP_HOSTNAME
115 * Command line configuration.
117 #include <config_cmd_default.h>
119 #define CONFIG_CMD_PCI
120 #define CONFIG_CMD_IRQ
121 #define CONFIG_CMD_SAVEENV
122 #define CONFIG_CMD_FLASH
125 #undef CONFIG_WATCHDOG /* watchdog disabled */
128 * Miscellaneous configurable options
130 #undef CONFIG_SYS_LONGHELP /* undef to save memory */
131 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
132 #if defined(CONFIG_CMD_KGDB)
133 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
135 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
137 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
138 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
139 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
141 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
142 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
144 #define CONFIG_CONS_INDEX 1
145 #define CONFIG_SYS_NS16550
146 #define CONFIG_SYS_NS16550_SERIAL
147 #define CONFIG_SYS_NS16550_REG_SIZE 1
148 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
150 #define CONFIG_SYS_EXT_SERIAL_CLOCK 14318180
152 /* The following table includes the supported baudrates */
153 #define CONFIG_SYS_BAUDRATE_TABLE \
154 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
155 57600, 115200, 230400, 460800, 921600 }
157 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
158 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
160 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
162 /*-----------------------------------------------------------------------
164 *-----------------------------------------------------------------------
166 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
167 #define PCI_HOST_FORCE 1 /* configure as pci host */
168 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
170 #define CONFIG_PCI /* include pci support */
171 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
172 #undef CONFIG_PCI_PNP /* no pci plug-and-play */
173 /* resource configuration */
175 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */
176 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */
177 #define CONFIG_SYS_PCI_PTM1LA 0xFFFC0000 /* point to flash */
178 #define CONFIG_SYS_PCI_PTM1MS 0xFFFFF001 /* 4kB, enable hard-wired to 1 */
179 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
180 #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
181 #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
182 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
184 /*-----------------------------------------------------------------------
185 * External peripheral base address
186 *-----------------------------------------------------------------------
188 /* Bank 0 - Flash/SRAM 0xFF000000 16MB 16 Bit */
189 /* Bank 1 - NVRAM/RTC 0xF0000000 1MB 8 Bit */
190 /* Bank 2 - A/D converter 0xF0100000 1MB 8 Bit */
191 /* Bank 3 - Ethernet PHY Reset 0xF0200000 1MB 8 Bit */
192 /* Bank 4 - PC-MIP PRSNT1# 0xF0300000 1MB 8 Bit */
193 /* Bank 5 - PC-MIP PRSNT2# 0xF0400000 1MB 8 Bit */
194 /* Bank 6 - CPU LED0 0xF0500000 1MB 8 Bit */
195 /* Bank 7 - CPU LED1 0xF0600000 1MB 8 Bit */
197 /* ----------------------------------------------------------------------- */
198 /* Memory Bank 0 (Flash) initialization */
199 /* ----------------------------------------------------------------------- */
200 #define CS0_AP 0x9B015480
201 #define CS0_CR 0xFF87A000 /* BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
202 /* ----------------------------------------------------------------------- */
203 /* Memory Bank 1 (NVRAM/RTC) initialization */
204 /* ----------------------------------------------------------------------- */
205 #define CS1_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
206 #define CS1_CR 0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
207 /* ----------------------------------------------------------------------- */
208 /* Memory Bank 2 (A/D converter) initialization */
209 /* ----------------------------------------------------------------------- */
210 #define CS2_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
211 #define CS2_CR 0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
212 /* ----------------------------------------------------------------------- */
213 /* Memory Bank 3 (Ethernet PHY Reset) initialization */
214 /* ----------------------------------------------------------------------- */
215 #define CS3_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
216 #define CS3_CR 0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
217 /* ----------------------------------------------------------------------- */
218 /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
219 /* ----------------------------------------------------------------------- */
220 #define CS4_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
221 #define CS4_CR 0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
222 /* ----------------------------------------------------------------------- */
223 /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
224 /* ----------------------------------------------------------------------- */
225 #define CS5_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
226 #define CS5_CR 0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
227 /* ----------------------------------------------------------------------- */
228 /* Memory Bank 6 (CPU LED0) initialization */
229 /* ----------------------------------------------------------------------- */
230 #define CS6_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
231 #define CS6_CR 0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
232 /* ----------------------------------------------------------------------- */
233 /* Memory Bank 7 (CPU LED1) initialization */
234 /* ----------------------------------------------------------------------- */
235 #define CS7_AP 0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
236 #define CS7_CR 0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
238 #define CONFIG_SYS_NVRAM_REG_BASE_ADDR 0xF0000000
239 #define CONFIG_SYS_RTC_REG_BASE_ADDR (0xF0000000 + 0x7F8)
240 #define CONFIG_SYS_ADC_REG_BASE_ADDR 0xF0100000
241 #define CONFIG_SYS_PHYRES_REG_BASE_ADDR 0xF0200000
242 #define CONFIG_SYS_PRSNT1_REG_BASE_ADDR 0xF0300000
243 #define CONFIG_SYS_PRSNT2_REG_BASE_ADDR 0xF0400000
244 #define CONFIG_SYS_LED0_REG_BASE_ADDR 0xF0500000
245 #define CONFIG_SYS_LED1_REG_BASE_ADDR 0xF0600000
249 #define CONFIG_SYS_SDRAM_MANUALLY 1
250 #define CONFIG_SYS_SDRAM_SINGLE_BANK 1
252 #ifdef CONFIG_SYS_SDRAM_MANUALLY
253 /*-----------------------------------------------------------------------
254 * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
255 *----------------------------------------------------------------------*/
256 #define MB0CF 0x00062001 /* 32MB @ 0 */
257 /*-----------------------------------------------------------------------
258 * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
259 *----------------------------------------------------------------------*/
260 #ifdef CONFIG_SYS_SDRAM_SINGLE_BANK
261 #define MB1CF 0x0 /* 0MB @ 32MB */
263 #define MB1CF 0x02062001 /* 32MB @ 32MB */
265 /*-----------------------------------------------------------------------
266 * Set MB2CF for bank 2. off
267 *----------------------------------------------------------------------*/
268 #define MB2CF 0x0 /* 0MB */
269 /*-----------------------------------------------------------------------
270 * Set MB3CF for bank 3. off
271 *----------------------------------------------------------------------*/
272 #define MB3CF 0x0 /* 0MB */
274 #define SDTR_100 0x0086400D
275 #define RTR_100 0x05F0
276 #define SDTR_66 0x00854006 /* orig U-Boot-wallnut says 0x00854006 */
277 #define RTR_66 0x03f8
279 #endif /* CONFIG_SYS_SDRAM_MANUALLY */
282 /*-----------------------------------------------------------------------
283 * Start addresses for the final memory configuration
284 * (Set up by the startup code)
285 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
287 #define CONFIG_SYS_SDRAM_BASE 0x00000000
288 #define CONFIG_SYS_SDRAM_SIZE 32
289 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* 8 MByte Flash */
290 #define CONFIG_SYS_MONITOR_BASE 0xFFFE0000 /* last 128kByte within Flash */
291 /*#define CONFIG_SYS_MONITOR_LEN (192 * 1024)*/ /* Reserve 196 kB for Monitor */
292 #define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */
293 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
296 * For booting Linux, the board info and command line data
297 * have to be in the first 8 MB of memory, since this is
298 * the maximum mapped by the Linux kernel during initialization.
300 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
301 /*-----------------------------------------------------------------------
304 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
305 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
306 #define CONFIG_SYS_FLASH_16BIT 1 /* Rom 16 bit data bus */
308 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
309 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
311 /* BEG ENVIRONNEMENT FLASH */
312 #ifdef CONFIG_ENV_IS_IN_FLASH
313 #define CONFIG_ENV_SECT_SIZE (128*1024)
315 #if 0 /* force ENV to be NOT embedded */
316 #define CONFIG_ENV_ADDR 0xfffa0000
317 #else /* force ENV to be embedded */
318 #define CONFIG_ENV_SIZE (2 * 1024) /* Total Size of Environment Sector 2k */
319 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
320 /* #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE)*/
321 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
325 /* END ENVIRONNEMENT FLASH */
326 /*-----------------------------------------------------------------------
329 #define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_REG_BASE_ADDR /* NVRAM base address */
330 #define CONFIG_SYS_NVRAM_SIZE 0x7F8 /* NVRAM size 2kByte - 8 Byte for RTC */
332 #ifdef CONFIG_ENV_IS_IN_NVRAM
333 #define CONFIG_ENV_SIZE 0x7F8 /* Size of Environment vars */
334 #define CONFIG_ENV_ADDR \
335 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
339 * Init Memory Controller:
341 * BR0/1 and OR0/1 (FLASH)
344 #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */
345 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
348 /* Configuration Port location */
349 /* #define CONFIG_PORT_ADDR 0xF0000500 */
351 /*-----------------------------------------------------------------------
352 * Definitions for initial stack pointer and data area (in DPRAM)
354 #define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
355 #define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
356 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
357 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
358 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
360 /*-----------------------------------------------------------------------
361 * Definitions for Serial Presence Detect EEPROM address
362 * (to get SDRAM settings)
364 #define SPD_EEPROM_ADDRESS 0x50
366 #if defined(CONFIG_CMD_KGDB)
367 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
368 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
370 #endif /* __CONFIG_H */