2 * Copyright (C) 2005 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * Support for Embedded Planet EP88x boards.
6 * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #define CONFIG_EP88X /* Embedded Planet EP88x board */
33 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
35 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
36 #define CONFIG_ENV_OVERWRITE
38 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
39 #define CONFIG_BAUDRATE 38400
41 #define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */
42 #define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */
43 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
44 #define CFG_DISCOVER_PHY
46 #endif /* CONFIG_FEC_ENET */
48 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
49 #define CONFIG_8xx_CPUCLK_DEFAULT 100000000
50 #define CFG_8xx_CPUCLK_MIN 40000000
51 #define CFG_8xx_CPUCLK_MAX 133000000
54 * Command line configuration.
56 #include <config_cmd_default.h>
58 #define CONFIG_CMD_DHCP
59 #define CONFIG_CMD_IMMAP
60 #define CONFIG_CMD_MII
61 #define CONFIG_CMD_PING
64 #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
65 #define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */
66 #define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"
68 #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
69 #undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
71 /*-----------------------------------------------------------------------
72 * Miscellaneous configurable options
74 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
75 #define CFG_HUSH_PARSER
76 #define CFG_PROMPT_HUSH_PS2 "> "
77 #define CFG_LONGHELP /* #undef to save memory */
78 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
79 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
80 #define CFG_MAXARGS 16 /* Max number of command args */
81 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
83 #define CFG_LOAD_ADDR 0x400000 /* Default load address */
85 #define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
87 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
89 /*-----------------------------------------------------------------------
90 * RAM configuration (note that CFG_SDRAM_BASE must be zero)
92 #define CFG_SDRAM_BASE 0x00000000
93 #define CFG_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */
95 #define CFG_MAMR 0x00805000
98 * 4096 Up to 4096 SDRAM rows
100 * 32 PTP (pre-divider from MPTPR)
101 * 4 Number of refresh cycles per period
102 * 64 Refresh cycle in ms per number of rows
104 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
106 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
107 #define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
109 #define CFG_RESET_ADDRESS 0x09900000
111 /*-----------------------------------------------------------------------
112 * For booting Linux, the board info and command line data
113 * have to be in the first 8 MB of memory, since this is
114 * the maximum mapped by the Linux kernel during initialization.
116 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
118 #define CFG_MONITOR_BASE TEXT_BASE
119 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
121 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
123 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
124 #endif /* CONFIG_BZIP2 */
126 /*-----------------------------------------------------------------------
129 #define CFG_FLASH_BASE 0xFC000000
130 #define CFG_FLASH_CFI /* The flash is CFI compatible */
131 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
132 #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
133 #define CFG_MAX_FLASH_SECT 512 /* Max num of sects on one chip */
135 /* Environment is in flash */
136 #define CFG_ENV_IS_IN_FLASH
137 #define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */
138 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
140 #define CFG_OR0_PRELIM 0xFC000160
141 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)
143 #define CFG_DIRECT_FLASH_TFTP
145 /*-----------------------------------------------------------------------
148 #define CFG_OR3_PRELIM 0xFF0005B0
149 #define CFG_BR3_PRELIM (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)
151 #define CFG_BCSR 0xFA400000
153 /*-----------------------------------------------------------------------
154 * Internal Memory Map Register
156 #define CFG_IMMR 0xF0000000
158 /*-----------------------------------------------------------------------
159 * Definitions for initial stack pointer and data area (in DPRAM)
161 #define CFG_INIT_RAM_ADDR CFG_IMMR
162 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
163 #define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
164 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
165 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
167 /*-----------------------------------------------------------------------
168 * Configuration registers
170 #ifdef CONFIG_WATCHDOG
171 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
172 SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
175 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
176 SYPCR_SWF | SYPCR_SWP)
177 #endif /* CONFIG_WATCHDOG */
179 #define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
181 /* TBSCR - Time Base Status and Control Register */
182 #define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
184 /* PISCR - Periodic Interrupt Status and Control */
185 #define CFG_PISCR PISCR_PS
187 /* SCCR - System Clock and reset Control Register */
188 #define SCCR_MASK SCCR_EBDF11
189 #define CFG_SCCR SCCR_RTSEL
193 /*-----------------------------------------------------------------------
194 * Cache Configuration
196 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
198 /*-----------------------------------------------------------------------
199 * Internal Definitions
203 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
204 #define BOOTFLAG_WARM 0x02 /* Software reboot */
206 #endif /* __CONFIG_H */