3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
5 * based on the Sequoia board configuration by
6 * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 **********************************************************************
26 * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
27 **********************************************************************
33 * High Level Configuration Options
35 #define CONFIG_DU440 1 /* Board is esd DU440 */
36 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
37 #define CONFIG_4xx 1 /* ... PPC4xx family */
38 #define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
40 #ifndef CONFIG_SYS_TEXT_BASE
41 #define CONFIG_SYS_TEXT_BASE 0xFFFA0000
44 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
45 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
46 #define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
49 * Base addresses -- Note these are effective addresses where the
50 * actual resources get mapped (not physical addresses)
52 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
53 #define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
55 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
56 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
57 #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
59 #define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
60 #define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
61 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
62 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
63 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
64 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
65 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
66 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
67 #define CONFIG_SYS_PCI_IOBASE 0xe8000000
68 #define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
69 #define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
71 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
72 #define CONFIG_SYS_USB_DEVICE 0xe0000000
73 #define CONFIG_SYS_USB_HOST 0xe0000400
76 * Initial RAM & stack pointer
78 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
79 #define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */
80 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
82 #define CONFIG_SYS_INIT_RAM_END (4 << 10)
83 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
84 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
85 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
90 #define CONFIG_CONS_INDEX 1 /* Use UART0 */
91 #define CONFIG_SYS_NS16550
92 #define CONFIG_SYS_NS16550_SERIAL
93 #define CONFIG_SYS_NS16550_REG_SIZE 1
94 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
95 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
96 #define CONFIG_BAUDRATE 115200
97 #define CONFIG_SERIAL_MULTI 1
99 #define CONFIG_SYS_BAUDRATE_TABLE \
100 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
106 #define CONFIG_VIDEO_SMI_LYNXEM
107 #define CONFIG_CFB_CONSOLE
108 #define CONFIG_VIDEO_LOGO
109 #define CONFIG_VGA_AS_SINGLE_DEVICE
110 #define CONFIG_SPLASH_SCREEN
111 #define CONFIG_SPLASH_SCREEN_ALIGN
112 #define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
113 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
114 #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
115 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
116 #define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
121 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
126 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
127 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
129 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
131 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
132 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
134 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
135 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
137 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
138 /* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
139 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
141 #define CONFIG_SYS_FLASH_EMPTY_INFO
142 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
144 #ifdef CONFIG_ENV_IS_IN_FLASH
145 #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
146 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
147 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
149 /* Address and size of Redundant Environment Sector */
150 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
151 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
154 #ifdef CONFIG_ENV_IS_IN_EEPROM
155 #define CONFIG_ENV_OFFSET 0 /* environment starts at */
156 /* the beginning of the EEPROM */
157 #define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
163 #define CONFIG_SYS_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
164 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
165 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
166 /* 440EPx errata CHIP 11 */
167 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
168 #define CONFIG_DDR_ECC /* Use ECC when available */
169 #define SPD_EEPROM_ADDRESS {0x50}
170 #define CONFIG_PROG_SDRAM_TLB
175 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
176 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
177 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
178 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
179 #define CONFIG_SYS_I2C_SLAVE 0x7F
180 #define CONFIG_I2C_MULTI_BUS 1
182 #define CONFIG_SYS_SPD_BUS_NUM 0
183 #define IIC1_MCP3021_ADDR 0x4d
184 #define IIC1_USB2507_ADDR 0x2c
185 #ifdef CONFIG_I2C_MULTI_BUS
186 #define CONFIG_SYS_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
188 #define CONFIG_SYS_I2C_MULTI_EEPROMS
189 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
190 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
191 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
192 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
193 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
195 #define CONFIG_SYS_EEPROM_WREN 1
196 #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
199 * standard dtt sensor configuration - bottom bit will determine local or
200 * remote sensor of the TMP401
202 #define CONFIG_DTT_SENSORS { 0, 1 }
205 * The PMC440 uses a TI TMP401 temperature sensor. This part
206 * is basically compatible to the ADM1021 that is supported
210 * - conversion rate 0x02 = 0.25 conversions/second
211 * - ALERT ouput disabled
212 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
213 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
215 #define CONFIG_DTT_ADM1021
216 #define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
221 #define CONFIG_RTC_DS1338
222 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
224 #undef CONFIG_BOOTARGS
226 #define CONFIG_EXTRA_ENV_SETTINGS \
230 "nfsargs=setenv bootargs root=/dev/nfs rw " \
231 "nfsroot=${serverip}:${rootpath}\0" \
232 "ramargs=setenv bootargs root=/dev/ram rw\0" \
233 "addip=setenv bootargs ${bootargs} " \
234 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
235 ":${hostname}:${netdev}:off panic=1\0" \
236 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
237 "flash_self=run ramargs addip addtty optargs;" \
238 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
239 "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
241 "rootpath=/tftpboot/du440/target_root_du440\0" \
242 "img=/tftpboot/du440/uImage\0" \
243 "kernel_addr=FFC00000\0" \
244 "ramdisk_addr=FFE00000\0" \
245 "initrd_high=30000000\0" \
246 "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
247 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
248 "cp.b 100000 FFFA0000 60000\0" \
251 #define CONFIG_PREBOOT /* enable preboot variable */
253 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
255 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
256 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
259 int du440_phy_addr(int devnum);
262 #define CONFIG_PPC4xx_EMAC
263 #define CONFIG_IBM_EMAC4_V4 1
264 #define CONFIG_MII 1 /* MII PHY management */
265 #define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
267 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
268 #undef CONFIG_PHY_GIGE /* no GbE detection */
270 #define CONFIG_HAS_ETH0
271 #define CONFIG_SYS_RX_ETH_BUFFER 128
273 #define CONFIG_NET_MULTI 1
274 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
275 #define CONFIG_PHY1_ADDR du440_phy_addr(1)
280 #define CONFIG_USB_OHCI_NEW
281 #define CONFIG_USB_STORAGE
282 #define CONFIG_SYS_OHCI_BE_CONTROLLER
284 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
285 #define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
286 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "du440"
287 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
289 /* Comment this out to enable USB 1.1 device */
290 #define USB_2_0_DEVICE
293 #define CONFIG_MAC_PARTITION
294 #define CONFIG_DOS_PARTITION
295 #define CONFIG_ISO_PARTITION
297 #include <config_cmd_default.h>
299 #define CONFIG_CMD_ASKENV
300 #define CONFIG_CMD_BMP
301 #define CONFIG_CMD_BSP
302 #define CONFIG_CMD_DATE
303 #define CONFIG_CMD_DHCP
304 #define CONFIG_CMD_DIAG
305 #define CONFIG_CMD_DTT
306 #define CONFIG_CMD_EEPROM
307 #define CONFIG_CMD_ELF
308 #define CONFIG_CMD_FAT
309 #define CONFIG_CMD_I2C
310 #define CONFIG_CMD_IRQ
311 #define CONFIG_CMD_MII
312 #define CONFIG_CMD_NAND
313 #define CONFIG_CMD_NET
314 #define CONFIG_CMD_NFS
315 #define CONFIG_CMD_PCI
316 #define CONFIG_CMD_PING
317 #define CONFIG_CMD_REGINFO
318 #define CONFIG_CMD_SDRAM
319 #define CONFIG_CMD_SOURCE
320 #define CONFIG_CMD_USB
322 #define CONFIG_SUPPORT_VFAT
325 * Miscellaneous configurable options
327 #define CONFIG_SYS_LONGHELP /* undef to save memory */
328 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
329 #if defined(CONFIG_CMD_KGDB)
330 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
332 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
334 /* Print Buffer Size */
335 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
336 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
337 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
339 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
340 #define CONFIG_SYS_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
342 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
343 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
345 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
347 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
348 #define CONFIG_LOOPW 1 /* enable loopw command */
349 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
350 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
351 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
353 #define CONFIG_AUTOBOOT_KEYED 1
354 #define CONFIG_AUTOBOOT_PROMPT \
355 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
356 #define CONFIG_AUTOBOOT_DELAY_STR "d"
357 #define CONFIG_AUTOBOOT_STOP_STR " "
362 #define CONFIG_PCI /* include pci support */
363 #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
364 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
365 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
367 /* Board-specific PCI */
368 #define CONFIG_SYS_PCI_TARGET_INIT
369 #define CONFIG_SYS_PCI_MASTER_INIT
372 * For booting Linux, the board info and command line data
373 * have to be in the first 8 MB of memory, since this is
374 * the maximum mapped by the Linux kernel during initialization.
376 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
379 * External Bus Controller (EBC) Setup
381 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
383 #define CONFIG_SYS_CPLD_BASE 0xC0000000
384 #define CONFIG_SYS_CPLD_RANGE 0x00000010
385 #define CONFIG_SYS_DUMEM_BASE 0xC0100000
386 #define CONFIG_SYS_DUMEM_RANGE 0x00100000
387 #define CONFIG_SYS_DUIO_BASE 0xC0200000
388 #define CONFIG_SYS_DUIO_RANGE 0x00010000
390 #define CONFIG_SYS_NAND0_CS 2 /* NAND chip connected to CSx */
391 #define CONFIG_SYS_NAND1_CS 3 /* NAND chip connected to CSx */
392 /* Memory Bank 0 (NOR-FLASH) initialization */
393 #define CONFIG_SYS_EBC_PB0AP 0x04017200
394 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
396 /* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
397 #define CONFIG_SYS_EBC_PB1AP 0x018003c0
398 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
400 /* Memory Bank 2 (NAND-FLASH) initialization */
401 #define CONFIG_SYS_EBC_PB2AP 0x018003c0
402 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND0_ADDR | 0x1c000)
404 /* Memory Bank 3 (NAND-FLASH) initialization */
405 #define CONFIG_SYS_EBC_PB3AP 0x018003c0
406 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND1_ADDR | 0x1c000)
408 /* Memory Bank 4 (DUMEM, 1MB) initialization */
409 #define CONFIG_SYS_EBC_PB4AP 0x018053c0
410 #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_DUMEM_BASE | 0x18000)
412 /* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
413 #define CONFIG_SYS_EBC_PB5AP 0x018053c0
414 #define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_DUIO_BASE | 0x18000)
419 #define CONFIG_SYS_MAX_NAND_DEVICE 2
420 #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
421 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
422 CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
424 #if defined(CONFIG_CMD_KGDB)
425 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
426 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
429 #define CONFIG_SOURCE 1
431 #define CONFIG_OF_LIBFDT
432 #define CONFIG_OF_BOARD_SETUP
434 #endif /* __CONFIG_H */