3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
5 * based on the Sequoia board configuration by
6 * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 **********************************************************************
26 * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
27 **********************************************************************
33 * High Level Configuration Options
35 #define CONFIG_DU440 1 /* Board is esd DU440 */
36 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
37 #define CONFIG_4xx 1 /* ... PPC4xx family */
38 #define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
41 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
42 #define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
45 * Base addresses -- Note these are effective addresses where the
46 * actual resources get mapped (not physical addresses)
48 #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
49 #define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
51 #define CFG_BOOT_BASE_ADDR 0xf0000000
52 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
53 #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
54 #define CFG_MONITOR_BASE TEXT_BASE
55 #define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */
56 #define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */
57 #define CFG_OCM_BASE 0xe0010000 /* ocm */
58 #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
59 #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
60 #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
61 #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
62 #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
63 #define CFG_PCI_IOBASE 0xe8000000
66 /* Don't change either of these */
67 #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
69 #define CFG_USB2D0_BASE 0xe0000100
70 #define CFG_USB_DEVICE 0xe0000000
71 #define CFG_USB_HOST 0xe0000400
74 * Initial RAM & stack pointer
76 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
77 #define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
78 #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
80 #define CFG_INIT_RAM_END (4 << 10)
81 #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
82 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
83 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
88 /* TODO: external clock oscillator will be removed */
89 #define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
90 #define CONFIG_BAUDRATE 115200
91 #define CONFIG_SERIAL_MULTI 1
92 #undef CONFIG_UART1_CONSOLE
94 #define CFG_BAUDRATE_TABLE \
95 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
101 #define CONFIG_VIDEO_SMI_LYNXEM
102 #define CONFIG_CFB_CONSOLE
103 #define CONFIG_VIDEO_LOGO
104 #define CONFIG_VGA_AS_SINGLE_DEVICE
105 #define CONFIG_SPLASH_SCREEN
106 #define CONFIG_SPLASH_SCREEN_ALIGN
107 #define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
108 #define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
109 #define CFG_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
110 #define CFG_CONSOLE_IS_IN_ENV
111 #define CFG_ISA_IO CFG_PCI_IOBASE
116 #define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
121 #define CFG_FLASH_CFI /* The flash is CFI compatible */
122 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
124 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
126 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
127 #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
129 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
130 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
132 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
133 /* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
134 #define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
136 #define CFG_FLASH_EMPTY_INFO
137 #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
139 #ifdef CFG_ENV_IS_IN_FLASH
140 #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
141 #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
142 #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
144 /* Address and size of Redundant Environment Sector */
145 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
146 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
149 #ifdef CFG_ENV_IS_IN_EEPROM
150 #define CFG_ENV_OFFSET 0 /* environment starts at */
151 /* the beginning of the EEPROM */
152 #define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
158 #define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
159 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
160 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
162 #define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
164 #define CONFIG_DDR_ECC /* Use ECC when available */
165 #define SPD_EEPROM_ADDRESS {0x50}
166 #define CONFIG_PROG_SDRAM_TLB
171 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
172 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
173 #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
174 #define CFG_I2C_SLAVE 0x7F
175 #define CONFIG_I2C_CMD_TREE 1
176 #define CONFIG_I2C_MULTI_BUS 1
178 #define CFG_SPD_BUS_NUM 0
179 #define IIC1_MCP3021_ADDR 0x4d
180 #define IIC1_USB2507_ADDR 0x2c
181 #ifdef CONFIG_I2C_MULTI_BUS
182 #define CFG_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
184 #define CFG_I2C_MULTI_EEPROMS
185 #define CFG_I2C_EEPROM_ADDR 0x54
186 #define CFG_I2C_EEPROM_ADDR_LEN 2
187 #define CFG_EEPROM_PAGE_WRITE_ENABLE
188 #define CFG_EEPROM_PAGE_WRITE_BITS 5
189 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
190 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
192 #define CFG_EEPROM_WREN 1
193 #define CFG_I2C_BOOT_EEPROM_ADDR 0x52
196 * standard dtt sensor configuration - bottom bit will determine local or
197 * remote sensor of the TMP401
199 #define CONFIG_DTT_SENSORS { 0, 1 }
202 * The PMC440 uses a TI TMP401 temperature sensor. This part
203 * is basically compatible to the ADM1021 that is supported
207 * - conversion rate 0x02 = 0.25 conversions/second
208 * - ALERT ouput disabled
209 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
210 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
212 #define CONFIG_DTT_ADM1021
213 #define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
218 #define CONFIG_RTC_DS1338
219 #define CFG_I2C_RTC_ADDR 0x68
221 #undef CONFIG_BOOTARGS
223 #define CONFIG_EXTRA_ENV_SETTINGS \
227 "nfsargs=setenv bootargs root=/dev/nfs rw " \
228 "nfsroot=${serverip}:${rootpath}\0" \
229 "ramargs=setenv bootargs root=/dev/ram rw\0" \
230 "addip=setenv bootargs ${bootargs} " \
231 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
232 ":${hostname}:${netdev}:off panic=1\0" \
233 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
234 "flash_self=run ramargs addip addtty optargs;" \
235 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
236 "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
238 "rootpath=/tftpboot/du440/target_root_du440\0" \
239 "img=/tftpboot/du440/uImage\0" \
240 "kernel_addr=FFC00000\0" \
241 "ramdisk_addr=FFE00000\0" \
242 "initrd_high=30000000\0" \
243 "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
244 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
245 "cp.b 100000 FFFA0000 60000\0" \
248 #define CONFIG_BOOTCOMMAND "run flash_self"
251 #define CONFIG_PREBOOT /* enable preboot variable */
253 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
255 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
256 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
259 int du440_phy_addr(int devnum);
262 #define CONFIG_IBM_EMAC4_V4 1
263 #define CONFIG_MII 1 /* MII PHY management */
264 #define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
266 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
267 #define CONFIG_PHY_GIGE 1 /* Include GbE detection */
269 #define CONFIG_HAS_ETH0
270 #define CFG_RX_ETH_BUFFER 128
272 #define CONFIG_NET_MULTI 1
273 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
274 #define CONFIG_PHY1_ADDR du440_phy_addr(1)
279 #define CONFIG_USB_OHCI_NEW
280 #define CONFIG_USB_STORAGE
281 #define CFG_OHCI_BE_CONTROLLER
283 #define CFG_USB_OHCI_CPU_INIT 1
284 #define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
285 #define CFG_USB_OHCI_SLOT_NAME "du440"
286 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
288 /* Comment this out to enable USB 1.1 device */
289 #define USB_2_0_DEVICE
292 #define CONFIG_MAC_PARTITION
293 #define CONFIG_DOS_PARTITION
294 #define CONFIG_ISO_PARTITION
296 #include <config_cmd_default.h>
298 #define CONFIG_CMD_BSP
299 #define CONFIG_CMD_DATE
300 #define CONFIG_CMD_ASKENV
301 #define CONFIG_CMD_DHCP
302 #define CONFIG_CMD_DTT
303 #define CONFIG_CMD_DIAG
304 #define CONFIG_CMD_EEPROM
305 #define CONFIG_CMD_ELF
306 #define CONFIG_CMD_FAT
307 #define CONFIG_CMD_I2C
308 #define CONFIG_CMD_IRQ
309 #define CONFIG_CMD_MII
310 #define CONFIG_CMD_NAND
311 #define CONFIG_CMD_NET
312 #define CONFIG_CMD_NFS
313 #define CONFIG_CMD_PCI
314 #define CONFIG_CMD_PING
315 #define CONFIG_CMD_USB
316 #define CONFIG_CMD_REGINFO
317 #define CONFIG_CMD_SDRAM
319 #define CONFIG_SUPPORT_VFAT
322 * Miscellaneous configurable options
324 #define CFG_LONGHELP /* undef to save memory */
325 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
326 #if defined(CONFIG_CMD_KGDB)
327 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
329 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
331 /* Print Buffer Size */
332 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
333 #define CFG_MAXARGS 16 /* max number of command args */
334 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
336 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
337 #define CFG_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
339 #define CFG_LOAD_ADDR 0x100000 /* default load address */
340 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
342 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
344 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
345 #define CONFIG_LOOPW 1 /* enable loopw command */
346 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
347 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
348 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
350 #define CONFIG_AUTOBOOT_KEYED 1
351 #define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
352 #define CONFIG_AUTOBOOT_DELAY_STR "d"
353 #define CONFIG_AUTOBOOT_STOP_STR " "
358 #define CONFIG_PCI /* include pci support */
359 #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
360 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
361 #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
363 /* Board-specific PCI */
364 #define CFG_PCI_TARGET_INIT
365 #define CFG_PCI_MASTER_INIT
368 * For booting Linux, the board info and command line data
369 * have to be in the first 8 MB of memory, since this is
370 * the maximum mapped by the Linux kernel during initialization.
372 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
375 * External Bus Controller (EBC) Setup
377 #define CFG_FLASH CFG_FLASH_BASE
379 #define CFG_CPLD_BASE 0xC0000000
380 #define CFG_CPLD_RANGE 0x00000010
381 #define CFG_DUMEM_BASE 0xC0100000
382 #define CFG_DUMEM_RANGE 0x00100000
383 #define CFG_DUIO_BASE 0xC0200000
384 #define CFG_DUIO_RANGE 0x00010000
386 #define CFG_NAND0_CS 2 /* NAND chip connected to CSx */
387 #define CFG_NAND1_CS 3 /* NAND chip connected to CSx */
388 /* Memory Bank 0 (NOR-FLASH) initialization */
389 #define CFG_EBC_PB0AP 0x04017200
390 #define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
392 /* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
393 #define CFG_EBC_PB1AP 0x018003c0
394 #define CFG_EBC_PB1CR (CFG_CPLD_BASE | 0x18000)
396 /* Memory Bank 2 (NAND-FLASH) initialization */
397 #define CFG_EBC_PB2AP 0x018003c0
398 #define CFG_EBC_PB2CR (CFG_NAND0_ADDR | 0x1c000)
400 /* Memory Bank 3 (NAND-FLASH) initialization */
401 #define CFG_EBC_PB3AP 0x018003c0
402 #define CFG_EBC_PB3CR (CFG_NAND1_ADDR | 0x1c000)
404 /* Memory Bank 4 (DUMEM, 1MB) initialization */
405 #define CFG_EBC_PB4AP 0x018053c0
406 #define CFG_EBC_PB4CR (CFG_DUMEM_BASE | 0x18000)
408 /* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
409 #define CFG_EBC_PB5AP 0x018053c0
410 #define CFG_EBC_PB5CR (CFG_DUIO_BASE | 0x18000)
415 #define CFG_MAX_NAND_DEVICE 2
416 #define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
417 #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
418 #define CFG_NAND_BASE_LIST {CFG_NAND0_ADDR + CFG_NAND0_CS, \
419 CFG_NAND1_ADDR + CFG_NAND1_CS}
422 * Internal Definitions
426 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
427 #define BOOTFLAG_WARM 0x02 /* Software reboot */
429 #if defined(CONFIG_CMD_KGDB)
430 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
431 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
435 #define CONFIG_SHOW_ACTIVITY 1
438 #endif /* __CONFIG_H */