3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_DU405 1 /* ...on a DU405 board */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
42 #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
44 #define CONFIG_BAUDRATE 9600
45 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47 #undef CONFIG_BOOTARGS
48 #define CONFIG_BOOTCOMMAND "bootm fff00000"
50 #define CONFIG_PREBOOT /* enable preboot variable */
52 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
53 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
55 #define CONFIG_MII 1 /* MII PHY management */
56 #define CONFIG_PHY_ADDR 0 /* PHY address */
57 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
59 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
68 #define CONFIG_MAC_PARTITION
69 #define CONFIG_DOS_PARTITION
71 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
72 #include <cmd_confdefs.h>
74 #undef CONFIG_WATCHDOG /* watchdog disabled */
76 #define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/
77 #define CFG_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */
79 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
82 * Miscellaneous configurable options
84 #define CFG_LONGHELP /* undef to save memory */
85 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
86 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
87 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
89 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
91 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
92 #define CFG_MAXARGS 16 /* max number of command args */
93 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
95 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
97 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
98 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
100 #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */
102 /* The following table includes the supported baudrates */
103 #define CFG_BAUDRATE_TABLE \
104 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
105 57600, 115200, 230400, 460800, 921600 }
107 #define CFG_LOAD_ADDR 0x100000 /* default load address */
108 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
110 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
112 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
114 #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
116 /*-----------------------------------------------------------------------
118 *-----------------------------------------------------------------------
120 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
121 #define PCI_HOST_FORCE 1 /* configure as pci host */
122 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
124 #define CONFIG_PCI /* include pci support */
125 #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
126 #define CONFIG_PCI_PNP /* do pci plug-and-play */
127 /* resource configuration */
129 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
131 #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
133 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
134 #define CFG_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
135 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
136 #define CFG_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
137 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
138 #define CFG_PCI_PTM2LA 0xffe00000 /* point to flash */
139 #define CFG_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
140 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
142 /*-----------------------------------------------------------------------
144 *-----------------------------------------------------------------------
146 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
147 #undef CONFIG_IDE_LED /* no led for ide supported */
148 #undef CONFIG_IDE_RESET /* no reset for ide supported */
150 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
151 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
153 #define CFG_ATA_BASE_ADDR 0xF0100000
154 #define CFG_ATA_IDE0_OFFSET 0x0000
156 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
157 #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
158 #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
160 /*-----------------------------------------------------------------------
161 * Start addresses for the final memory configuration
162 * (Set up by the startup code)
163 * Please note that CFG_SDRAM_BASE _must_ start at 0
165 #define CFG_SDRAM_BASE 0x00000000
166 #define CFG_FLASH_BASE 0xFFFD0000
167 #define CFG_MONITOR_BASE CFG_FLASH_BASE
168 #define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
169 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
172 * For booting Linux, the board info and command line data
173 * have to be in the first 8 MB of memory, since this is
174 * the maximum mapped by the Linux kernel during initialization.
176 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
177 /*-----------------------------------------------------------------------
180 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
181 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
183 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
184 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
186 #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
187 #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
188 #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
190 * The following defines are added for buggy IOP480 byte interface.
191 * All other boards should use the standard values (CPCI405 etc.)
193 #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
194 #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
195 #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
197 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
199 /*-----------------------------------------------------------------------
200 * I2C EEPROM (CAT24WC08) for environment
202 #define CONFIG_HARD_I2C /* I2c with hardware support */
203 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
204 #define CFG_I2C_SLAVE 0x7F
206 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
207 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
208 /* mask of address bits that overflow into the "EEPROM chip address" */
209 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
210 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
211 /* 16 byte page write mode using*/
212 /* last 4 bits of the address */
213 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
214 #define CFG_EEPROM_PAGE_WRITE_ENABLE
216 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
217 #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
218 #define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
219 /* total size of a CAT24WC08 is 1024 bytes */
221 /*-----------------------------------------------------------------------
222 * Cache Configuration
224 #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
225 #define CFG_CACHELINE_SIZE 32 /* ... */
226 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
227 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
231 * Init Memory Controller:
233 * BR0/1 and OR0/1 (FLASH)
236 #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
237 #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
239 /*-----------------------------------------------------------------------
240 * External Bus Controller (EBC) Setup
243 #define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */
244 #define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */
245 #define CAN_BA 0xF0000000 /* CAN Base Address */
246 #define DUART_BA 0xF0300000 /* DUART Base Address */
247 #define CF_BA 0xF0100000 /* CompactFlash Base Address */
248 #define SRAM_BA 0xF0200000 /* SRAM Base Address */
249 #define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */
250 #define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */
252 #define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */
254 /* Memory Bank 0 (Flash Bank 0) initialization */
255 #define CFG_EBC_PB0AP 0x92015480
256 #define CFG_EBC_PB0CR FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
258 /* Memory Bank 1 (Flash Bank 1) initialization */
259 #define CFG_EBC_PB1AP 0x92015480
260 #define CFG_EBC_PB1CR FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
262 /* Memory Bank 2 (CAN0) initialization */
263 #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
264 #define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
266 /* Memory Bank 3 (DUART) initialization */
267 #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
268 #define CFG_EBC_PB3CR DUART_BA | 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
270 /* Memory Bank 4 (CompactFlash IDE) initialization */
271 #define CFG_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
272 #define CFG_EBC_PB4CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
274 /* Memory Bank 5 (SRAM) initialization */
275 #define CFG_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
276 #define CFG_EBC_PB5CR SRAM_BA | 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
278 /* Memory Bank 6 (DURAG Bus IO Space) initialization */
279 #define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
280 #define CFG_EBC_PB6CR DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
282 /* Memory Bank 7 (DURAG Bus Mem Space) initialization */
283 #define CFG_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
284 #define CFG_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
287 /*-----------------------------------------------------------------------
288 * Definitions for initial stack pointer and data area (in DPRAM)
291 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
292 #define CFG_TEMP_STACK_OCM 1
294 /* On Chip Memory location */
295 #define CFG_OCM_DATA_ADDR 0xF8000000
296 #define CFG_OCM_DATA_SIZE 0x1000
298 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
299 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
300 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
301 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
302 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
306 * Internal Definitions
310 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
311 #define BOOTFLAG_WARM 0x02 /* Software reboot */
313 #endif /* __CONFIG_H */