2 * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 * Stephan Linz <linz@li-pro.net>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * NIOS CPU configuration.
31 * Here we must define CPU dependencies. Any unsupported option have to
32 * be defined with zero, example CPU without data cache / OCI:
34 * #define CFG_NIOS_CPU_ICACHE 4096
35 * #define CFG_NIOS_CPU_DCACHE 0
36 * #define CFG_NIOS_CPU_OCI_BASE 0
37 * #define CFG_NIOS_CPU_OCI_SIZE 0
40 #if defined(CONFIG_NIOS_SAFE_32)
44 #elif defined(CONFIG_NIOS_STANDARD_32)
47 #define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */
48 #define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */
49 #define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */
50 #define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */
51 #define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */
53 #define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */
55 #define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */
56 #define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */
57 #define CFG_NIOS_CPU_VEC_SIZE 256 /* size */
58 #define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */
59 #define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */
60 #define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */
63 /* on-chip extensions */
64 #define CFG_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */
65 #define CFG_NIOS_CPU_RAM_SIZE 0 /* size */
67 #define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */
68 #define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */
70 #define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */
71 #define CFG_NIOS_CPU_OCI_SIZE 256 /* size */
74 #define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */
76 #define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */
77 #define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */
78 #define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */
79 #define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */
81 #define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */
83 #define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */
86 #define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */
87 #define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */
88 #define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */
89 #define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */
91 #define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */
93 #define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */
97 #define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */
99 #define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */
100 #define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */
101 #define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */
102 #define CFG_NIOS_CPU_UART0_DB 8 /* data bit */
103 #define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */
104 #define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */
107 #define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */
109 #define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */
113 #define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */
115 #define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */
116 #define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */
117 #define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */
118 #define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */
121 #define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */
123 #define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */
127 #define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */
131 #define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */
132 #undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */
133 #define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */
134 #define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */
137 #define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */
139 #define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */
143 #define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */
147 #define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */
148 #undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */
149 #define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */
150 #define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */
153 #define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */
155 #define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */
159 #define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */
163 #define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */
164 #undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */
165 #define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */
166 #define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */
169 #define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */
171 #define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */
175 #define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */
179 #define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */
180 #undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */
181 #define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */
182 #define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */
185 #define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */
187 #define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */
191 #define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */
195 #define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */
196 #define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */
197 #define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */
198 #define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */
201 #define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */
203 #define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */
207 #define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */
211 #define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */
212 #undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */
213 #define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */
214 #define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */
217 #define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */
219 #define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */
223 #define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */
227 #define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */
228 #undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */
229 #define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */
230 #define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */
233 #define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */
235 #define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */
239 #define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */
244 #define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */
245 #define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */
247 /* active serial memory i/f */
248 #define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */
249 #define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */
250 #define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */
252 /* memory accessibility */
253 #define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */
254 #define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */
256 #define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */
257 #define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */
259 #define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */
260 #define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */
263 #define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */
265 #define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */
266 #define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */
267 #define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */
268 #define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/
269 #define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */
271 /* ex: alteramac(2) */
273 /* symbolic redefinition (undef, if not present) */
274 #define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */
275 #define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/
277 #define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */
278 #define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */
279 #define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */
280 #define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */
281 #define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */
282 #define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */
283 #define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */
284 #define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */
287 #error *** CFG_ERROR: you have to setup right NIOS CPU configuration
290 /*------------------------------------------------------------------------
291 * BOARD/CPU -- TOP-LEVEL
292 *----------------------------------------------------------------------*/
293 #define CONFIG_NIOS 1 /* NIOS-32 core */
294 #define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/
295 #define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
296 #define CFG_HZ 1000 /* 1 msec time tick */
297 #undef CFG_CLKS_IN_HZ
298 #define CONFIG_BOARD_PRE_INIT 1 /* enable early board-spec. init*/
300 /*------------------------------------------------------------------------
301 * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
302 *----------------------------------------------------------------------*/
303 #if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
305 #define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
306 #define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
309 #error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
312 #define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
313 #define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
314 #define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
316 /*------------------------------------------------------------------------
317 * MEMORY ORGANIZATION - For the most part, you can put things pretty
318 * much anywhere. This is pretty flexible for Nios. So here we make some
319 * arbitrary choices & assume that the monitor is placed at the end of
320 * a memory resource (so you must make sure TEXT_BASE is chosen
323 * -The heap is placed below the monitor.
324 * -Global data is placed below the heap.
325 * -The stack is placed below global data (&grows down).
326 *----------------------------------------------------------------------*/
327 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
328 #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
329 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
331 #define CFG_MONITOR_BASE TEXT_BASE
332 #define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
333 #define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
334 #define CFG_INIT_SP CFG_GBL_DATA_OFFSET
336 /*------------------------------------------------------------------------
338 *----------------------------------------------------------------------*/
339 #if (CFG_NIOS_CPU_FLASH_SIZE != 0)
341 #define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
342 #define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
343 #define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
344 #define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
345 #define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
346 #define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
347 #define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
350 #error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
353 /*------------------------------------------------------------------------
355 *----------------------------------------------------------------------*/
356 #if (CFG_NIOS_CPU_FLASH_SIZE != 0)
358 #define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
359 #define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */
360 #define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
361 #define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
364 #define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
367 /*------------------------------------------------------------------------
369 *----------------------------------------------------------------------*/
370 #if (CFG_NIOS_CPU_UART_NUMS != 0)
372 #define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
374 #if (CFG_NIOS_CPU_UART0_BR != 0)
375 #define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
376 #define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
378 #undef CFG_NIOS_FIXEDBAUD
379 #define CONFIG_BAUDRATE 115200
382 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
385 #error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
388 /*------------------------------------------------------------------------
389 * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
390 * so an avalon bus timer is required.
391 *----------------------------------------------------------------------*/
392 #if (CFG_NIOS_CPU_TIMER_NUMS != 0)
394 #if (CFG_NIOS_CPU_TICK_TIMER == 0)
396 #error *** CFG_ERROR: tick timer at TIMER0 not supported, expand your config.h
398 #elif (CFG_NIOS_CPU_TICK_TIMER == 1)
400 #define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
401 #define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
403 #if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
404 #define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
406 #error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ
409 #endif /* CFG_NIOS_CPU_TICK_TIMER */
412 #error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
415 /*------------------------------------------------------------------------
416 * Ethernet -- needs work!
417 *----------------------------------------------------------------------*/
418 #if (CFG_NIOS_CPU_LAN_NUMS == 1)
420 #if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
422 /****************************************************/
423 /* !!! LAN91C111 works for NIOS with patch only !!! */
424 /****************************************************/
425 #define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
426 #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
427 #define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
429 #if (CFG_NIOS_CPU_LAN0_BUSW == 32)
430 #define CONFIG_SMC_USE_32_BIT 1
432 #undef CONFIG_SMC_USE_32_BIT
435 #elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
437 /********************************************/
438 /* !!! CS8900 is __not__ tested on NIOS !!! */
439 /********************************************/
440 #define CONFIG_DRIVER_CS8900 /* Using CS8900 */
441 #define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
443 #if (CFG_NIOS_CPU_LAN0_BUSW == 32)
445 #define CS8900_BUS32 1
447 #define CS8900_BUS16 1
452 #error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
455 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
456 #define CONFIG_NETMASK 255.255.255.0
457 #define CONFIG_IPADDR 192.168.2.21
458 #define CONFIG_SERVERIP 192.168.2.16
461 #error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
464 /*------------------------------------------------------------------------
466 *----------------------------------------------------------------------*/
467 #if (CFG_NIOS_CPU_PIO_NUMS != 0)
469 #if (CFG_NIOS_CPU_LED_PIO == 0)
471 #error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
473 #elif (CFG_NIOS_CPU_LED_PIO == 1)
475 #error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
477 #elif (CFG_NIOS_CPU_LED_PIO == 2)
479 #define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
480 #define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
481 #define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
483 #if (CFG_NIOS_CPU_PIO2_TYPE == 1)
484 #define STATUS_LED_WRONLY 1
486 #undef STATUS_LED_WRONLY
489 #elif (CFG_NIOS_CPU_LED_PIO == 3)
491 #error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
493 #elif (CFG_NIOS_CPU_LED_PIO == 4)
495 #error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
497 #elif (CFG_NIOS_CPU_LED_PIO == 5)
499 #error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
501 #elif (CFG_NIOS_CPU_LED_PIO == 6)
503 #error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
505 #elif (CFG_NIOS_CPU_LED_PIO == 7)
507 #error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
509 #elif (CFG_NIOS_CPU_LED_PIO == 8)
511 #error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
513 #elif (CFG_NIOS_CPU_LED_PIO == 9)
515 #error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
518 #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
521 #define CONFIG_STATUS_LED 1 /* enable status led driver */
523 #define STATUS_LED_BIT (1 << 0) /* LED[0] */
524 #define STATUS_LED_STATE STATUS_LED_BLINKING
525 #define STATUS_LED_BOOT_STATE STATUS_LED_OFF
526 #define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */
527 #define STATUS_LED_BOOT 0 /* boot LED */
529 #if (STATUS_LED_BITS > 1)
530 #define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
531 #define STATUS_LED_STATE1 STATUS_LED_OFF
532 #define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */
533 #define STATUS_LED_RED 1 /* fail LED */
536 #if (STATUS_LED_BITS > 2)
537 #define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
538 #define STATUS_LED_STATE2 STATUS_LED_OFF
539 #define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */
540 #define STATUS_LED_YELLOW 2 /* info LED */
543 #if (STATUS_LED_BITS > 3)
544 #define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
545 #define STATUS_LED_STATE3 STATUS_LED_OFF
546 #define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */
547 #define STATUS_LED_GREEN 3 /* info LED */
550 #define STATUS_LED_PAR 1 /* makes status_led.h happy */
552 #endif /* CFG_NIOS_CPU_PIO_NUMS */
554 /*------------------------------------------------------------------------
555 * SEVEN SEGMENT LED DISPLAY
556 *----------------------------------------------------------------------*/
557 #if (CFG_NIOS_CPU_PIO_NUMS != 0)
559 #if (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
561 #error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
563 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
565 #error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
567 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
569 #error *** CFG_ERROR: status LEDs at PIO2 not supported, expand your config.h
571 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
573 #define SEVENSEG_BASE CFG_NIOS_CPU_PIO3
574 #define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS
575 #define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */
577 #if (CFG_NIOS_CPU_PIO3_TYPE == 1)
578 #define SEVENSEG_WRONLY 1
580 #undef SEVENSEG_WRONLY
583 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
585 #error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
587 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
589 #error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
591 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
593 #error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
595 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
597 #error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
599 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
601 #error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
603 #elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
605 #error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
608 #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
611 #define CONFIG_SEVENSEG 1 /* enable seven segment led driver */
614 * Dual 7-Segment Display pin assignment -- read more in your
615 * "Nios Development Board Reference Manual"
618 * (U8) HI:D[15..8] (U9) LO:D[7..0]
623 * |______| |______| ___
624 * | D8 | | D0 | | A |
626 * D10| |D12 D2| |D4 | G |
627 * |______| |______| E|___|C
632 #define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */
633 #define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */
634 #define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */
635 #define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */
636 #define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */
637 #define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */
638 #define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */
639 #define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */
640 #define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */
642 #endif /* CFG_NIOS_CPU_PIO_NUMS */
644 /*------------------------------------------------------------------------
646 *----------------------------------------------------------------------*/
647 #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
677 #include <cmd_confdefs.h>
679 /*------------------------------------------------------------------------
681 *----------------------------------------------------------------------*/
682 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
683 #define CONFIG_KGDB_BAUDRATE 9600
686 /*------------------------------------------------------------------------
688 *----------------------------------------------------------------------*/
689 #define CFG_LONGHELP /* undef to save memory */
690 #define CFG_PROMPT "DK1C20 > " /* Monitor Command Prompt */
691 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
692 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
693 #define CFG_MAXARGS 16 /* max number of command args*/
694 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
696 #if (CFG_SRAM_SIZE != 0)
697 #define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */
702 #if (CFG_SDRAM_SIZE != 0)
703 #define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */
704 #define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
706 #undef CFG_MEMTEST_START
707 #undef CFG_MEMTEST_END
711 #endif /* __CONFIG_H */