2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37 #define CONFIG_CPU86 1 /* ...on a CPU86 board */
40 * select serial console configuration
42 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
43 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
46 * if CONFIG_CONS_NONE is defined, then the serial console routines must
47 * defined elsewhere (for example, on the cogent platform, there are serial
48 * ports on the motherboard which are used for the serial console - see
49 * cogent/cma101/serial.[ch]).
51 #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
52 #define CONFIG_CONS_ON_SCC /* define if console on SCC */
53 #undef CONFIG_CONS_NONE /* define if console on something else*/
54 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
56 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
57 #define CONFIG_BAUDRATE 230400
59 #define CONFIG_BAUDRATE 9600
63 * select ethernet configuration
65 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
66 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
69 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
70 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
71 * from CONFIG_COMMANDS to remove support for networking.
74 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
75 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
76 #undef CONFIG_ETHER_NONE /* define if ether on something else */
77 #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
79 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
84 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
85 * - Enable Full Duplex in FSMR
87 # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
88 # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
89 # define CFG_CPMFCR_RAMTYPE 0
90 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
92 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
97 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
98 * - Enable Full Duplex in FSMR
100 # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
101 # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
102 # define CFG_CPMFCR_RAMTYPE 0
103 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
105 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
107 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
108 #define CONFIG_8260_CLKIN 64000000 /* in Hz */
110 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
112 #define CONFIG_PREBOOT \
114 "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \
117 #undef CONFIG_BOOTARGS
118 #define CONFIG_BOOTCOMMAND \
120 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
121 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
124 /*-----------------------------------------------------------------------
125 * I2C/EEPROM/RTC configuration
127 #define CONFIG_SOFT_I2C /* Software I2C support enabled */
129 # define CFG_I2C_SPEED 50000
130 # define CFG_I2C_SLAVE 0xFE
132 * Software (bit-bang) I2C driver configuration
134 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
135 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
136 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
137 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
138 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
139 else iop->pdat &= ~0x00010000
140 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
141 else iop->pdat &= ~0x00020000
142 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
144 #define CONFIG_RTC_PCF8563
145 #define CFG_I2C_RTC_ADDR 0x51
147 #undef CONFIG_WATCHDOG /* watchdog disabled */
149 /*-----------------------------------------------------------------------
150 * Disk-On-Chip configuration
153 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
155 #define CFG_DOC_SUPPORT_2000
156 #define CFG_DOC_SUPPORT_MILLENNIUM
158 /*-----------------------------------------------------------------------
159 * Miscellaneous configuration options
162 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
163 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
165 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
167 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
177 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
178 #include <cmd_confdefs.h>
181 * Miscellaneous configurable options
183 #define CFG_LONGHELP /* undef to save memory */
184 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
185 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
186 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
188 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
190 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
191 #define CFG_MAXARGS 16 /* max number of command args */
192 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
194 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
195 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
197 #define CFG_LOAD_ADDR 0x100000 /* default load address */
199 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
201 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
203 #define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
206 * For booting Linux, the board info and command line data
207 * have to be in the first 8 MB of memory, since this is
208 * the maximum mapped by the Linux kernel during initialization.
210 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
212 /*-----------------------------------------------------------------------
213 * Flash configuration
216 #define CFG_BOOTROM_BASE 0xFF800000
217 #define CFG_BOOTROM_SIZE 0x00080000
218 #define CFG_FLASH_BASE 0xFF000000
219 #define CFG_FLASH_SIZE 0x00800000
221 /*-----------------------------------------------------------------------
224 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
225 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
227 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
228 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
230 /*-----------------------------------------------------------------------
231 * Other areas to be mapped
234 /* CS3: Dual ported SRAM */
235 #define CFG_DPSRAM_BASE 0x40000000
236 #define CFG_DPSRAM_SIZE 0x00020000
238 /* CS4: DiskOnChip */
239 #define CFG_DOC_BASE 0xF4000000
240 #define CFG_DOC_SIZE 0x00100000
242 /* CS5: FDC37C78 controller */
243 #define CFG_FDC37C78_BASE 0xF1000000
244 #define CFG_FDC37C78_SIZE 0x00100000
246 /* CS6: Board configuration registers */
247 #define CFG_BCRS_BASE 0xF2000000
248 #define CFG_BCRS_SIZE 0x00010000
250 /* CS7: VME Extended Access Range */
251 #define CFG_VMEEAR_BASE 0x80000000
252 #define CFG_VMEEAR_SIZE 0x01000000
254 /* CS8: VME Standard Access Range */
255 #define CFG_VMESAR_BASE 0xFE000000
256 #define CFG_VMESAR_SIZE 0x01000000
258 /* CS9: VME Short I/O Access Range */
259 #define CFG_VMESIOAR_BASE 0xFD000000
260 #define CFG_VMESIOAR_SIZE 0x01000000
262 /*-----------------------------------------------------------------------
263 * Hard Reset Configuration Words
265 * if you change bits in the HRCW, you must also change the CFG_*
266 * defines for the various registers affected by the HRCW e.g. changing
267 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
269 #if defined(CONFIG_BOOT_ROM)
270 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
271 HRCW_BPS01 | HRCW_CS10PC01)
273 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
276 /* no slaves so just fill with zeros */
277 #define CFG_HRCW_SLAVE1 0
278 #define CFG_HRCW_SLAVE2 0
279 #define CFG_HRCW_SLAVE3 0
280 #define CFG_HRCW_SLAVE4 0
281 #define CFG_HRCW_SLAVE5 0
282 #define CFG_HRCW_SLAVE6 0
283 #define CFG_HRCW_SLAVE7 0
285 /*-----------------------------------------------------------------------
286 * Internal Memory Mapped Register
288 #define CFG_IMMR 0xF0000000
290 /*-----------------------------------------------------------------------
291 * Definitions for initial stack pointer and data area (in DPRAM)
293 #define CFG_INIT_RAM_ADDR CFG_IMMR
294 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
295 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
296 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
297 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
299 /*-----------------------------------------------------------------------
300 * Start addresses for the final memory configuration
301 * (Set up by the startup code)
302 * Please note that CFG_SDRAM_BASE _must_ start at 0
304 * 60x SDRAM is mapped at CFG_SDRAM_BASE.
306 #define CFG_SDRAM_BASE 0x00000000
307 #define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
308 #define CFG_MONITOR_BASE TEXT_BASE
309 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
310 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
312 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
317 /* environment is in Flash */
318 #define CFG_ENV_IS_IN_FLASH 1
319 #ifdef CONFIG_BOOT_ROM
320 # define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000)
321 # define CFG_ENV_SIZE 0x10000
322 # define CFG_ENV_SECT_SIZE 0x10000
325 /* environment is in EEPROM */
326 #define CFG_ENV_IS_IN_EEPROM 1
327 #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
328 #define CFG_I2C_EEPROM_ADDR_LEN 1
329 /* mask of address bits that overflow into the "EEPROM chip address" */
330 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
331 #define CFG_EEPROM_PAGE_WRITE_BITS 4
332 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
333 #define CFG_ENV_OFFSET 512
334 #define CFG_ENV_SIZE (2048 - 512)
338 * Internal Definitions
342 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
343 #define BOOTFLAG_WARM 0x02 /* Software reboot */
346 /*-----------------------------------------------------------------------
347 * Cache Configuration
349 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
350 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
351 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
354 /*-----------------------------------------------------------------------
355 * HIDx - Hardware Implementation-dependent Registers 2-11
356 *-----------------------------------------------------------------------
357 * HID0 also contains cache control - initially enable both caches and
358 * invalidate contents, then the final state leaves only the instruction
359 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
360 * but Soft reset does not.
362 * HID1 has only read-only information - nothing to set.
364 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
365 HID0_DCI|HID0_IFEM|HID0_ABE)
366 #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
369 /*-----------------------------------------------------------------------
370 * RMR - Reset Mode Register 5-5
371 *-----------------------------------------------------------------------
372 * turn on Checkstop Reset Enable
374 #define CFG_RMR RMR_CSRE
376 /*-----------------------------------------------------------------------
377 * BCR - Bus Configuration 4-25
378 *-----------------------------------------------------------------------
380 #define BCR_APD01 0x10000000
381 #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
383 /*-----------------------------------------------------------------------
384 * SIUMCR - SIU Module Configuration 4-31
385 *-----------------------------------------------------------------------
387 #define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
388 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
390 /*-----------------------------------------------------------------------
391 * SYPCR - System Protection Control 4-35
392 * SYPCR can only be written once after reset!
393 *-----------------------------------------------------------------------
394 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
396 #if defined(CONFIG_WATCHDOG)
397 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
398 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
400 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
401 SYPCR_SWRI|SYPCR_SWP)
402 #endif /* CONFIG_WATCHDOG */
404 /*-----------------------------------------------------------------------
405 * TMCNTSC - Time Counter Status and Control 4-40
406 *-----------------------------------------------------------------------
407 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
408 * and enable Time Counter
410 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
412 /*-----------------------------------------------------------------------
413 * PISCR - Periodic Interrupt Status and Control 4-42
414 *-----------------------------------------------------------------------
415 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
418 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
420 /*-----------------------------------------------------------------------
421 * SCCR - System Clock Control 9-8
422 *-----------------------------------------------------------------------
423 * Ensure DFBRG is Divide by 16
425 #define CFG_SCCR SCCR_DFBRG01
427 /*-----------------------------------------------------------------------
428 * RCCR - RISC Controller Configuration 13-7
429 *-----------------------------------------------------------------------
433 #define CFG_MIN_AM_MASK 0xC0000000
434 /*-----------------------------------------------------------------------
435 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
436 *-----------------------------------------------------------------------
438 #define CFG_MPTPR 0x1F00
440 /*-----------------------------------------------------------------------
441 * PSRT - Refresh Timer Register 10-16
442 *-----------------------------------------------------------------------
444 #define CFG_PSRT 0x0f
446 /*-----------------------------------------------------------------------
447 * PSRT - SDRAM Mode Register 10-10
448 *-----------------------------------------------------------------------
451 /* SDRAM initialization values for 8-column chips
453 #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
455 ORxS_ROWST_PBI0_A9 |\
458 #define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
459 PSDMR_BSMA_A14_A16 |\
460 PSDMR_SDA10_PBI0_A10 |\
468 /* SDRAM initialization values for 9-column chips
470 #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
472 ORxS_ROWST_PBI0_A7 |\
475 #define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
476 PSDMR_BSMA_A13_A15 |\
477 PSDMR_SDA10_PBI0_A9 |\
486 * Init Memory Controller:
488 * Bank Bus Machine PortSz Device
489 * ---- --- ------- ------ ------
490 * 0 60x GPCM 8 bit Boot ROM
491 * 1 60x GPCM 64 bit FLASH
492 * 2 60x SDRAM 64 bit SDRAM
496 #define CFG_MRS_OFFS 0x00000000
498 #ifdef CONFIG_BOOT_ROM
501 #define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
506 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
514 #define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
519 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
525 #else /* CONFIG_BOOT_ROM */
528 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
533 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
541 #define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
546 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
552 #endif /* CONFIG_BOOT_ROM */
555 /* Bank 2 - 60x bus SDRAM
558 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
563 #define CFG_OR2_PRELIM CFG_OR2_9COL
565 #define CFG_PSDMR CFG_PSDMR_9COL
566 #endif /* CFG_RAMBOOT */
568 /* Bank 3 - Dual Ported SRAM
570 #define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
575 #define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\
581 /* Bank 4 - DiskOnChip
583 #define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
588 #define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
593 /* Bank 5 - FDC37C78 controller
595 #define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
600 #define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\
605 /* Bank 6 - Board control registers
607 #define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\
612 #define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\
616 /* Bank 7 - VME Extended Access Range
618 #define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
623 #define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\
629 /* Bank 8 - VME Standard Access Range
631 #define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
636 #define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\
642 /* Bank 9 - VME Short I/O Access Range
644 #define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
649 #define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\
655 #endif /* __CONFIG_H */