ARMV7: AM3517/05: Add support for CraneBoard.
[oweals/u-boot.git] / include / configs / CPU86.h
1 /*
2  * (C) Copyright 2001-2005
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 /*
25  * board/config.h - configuration options, board specific
26  */
27
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30
31 /*
32  * High Level Configuration Options
33  * (easy to change)
34  */
35
36 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
37 #define CONFIG_CPU86            1       /* ...on a CPU86 board  */
38 #define CONFIG_CPM2             1       /* Has a CPM2 */
39
40 #ifdef CONFIG_BOOT_ROM
41 #define CONFIG_SYS_TEXT_BASE    0xFF800000
42 #else
43 #define CONFIG_SYS_TEXT_BASE    0xFF000000
44 #endif
45
46 /*
47  * select serial console configuration
48  *
49  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
50  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
51  * for SCC).
52  *
53  * if CONFIG_CONS_NONE is defined, then the serial console routines must
54  * defined elsewhere (for example, on the cogent platform, there are serial
55  * ports on the motherboard which are used for the serial console - see
56  * cogent/cma101/serial.[ch]).
57  */
58 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
59 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
60 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
61 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
62
63 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
64 #define CONFIG_BAUDRATE         230400
65 #else
66 #define CONFIG_BAUDRATE         9600
67 #endif
68
69 /*
70  * select ethernet configuration
71  *
72  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
73  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
74  * for FCC)
75  *
76  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
77  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
78  */
79 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
80 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
81 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
82 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
83
84 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
85
86 /*
87  * - Rx-CLK is CLK11
88  * - Tx-CLK is CLK12
89  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
90  * - Enable Full Duplex in FSMR
91  */
92 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
93 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
94 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
95 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
96
97 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
98
99 /*
100  * - Rx-CLK is CLK13
101  * - Tx-CLK is CLK14
102  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
103  * - Enable Full Duplex in FSMR
104  */
105 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
106 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
107 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
108 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
109
110 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
111
112 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
113 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
114
115 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
116
117 #define CONFIG_PREBOOT                                                          \
118         "echo; "                                                                \
119         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
120         "echo"
121
122 #undef  CONFIG_BOOTARGS
123 #define CONFIG_BOOTCOMMAND                                                      \
124         "bootp; "                                                               \
125         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
126         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
127         "bootm"
128
129 /*-----------------------------------------------------------------------
130  * I2C/EEPROM/RTC configuration
131  */
132 #define CONFIG_SOFT_I2C                 /* Software I2C support enabled */
133
134 # define CONFIG_SYS_I2C_SPEED           50000
135 # define CONFIG_SYS_I2C_SLAVE           0xFE
136 /*
137  * Software (bit-bang) I2C driver configuration
138  */
139 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
140 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
141 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
142 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
143 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
144                         else    iop->pdat &= ~0x00010000
145 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
146                         else    iop->pdat &= ~0x00020000
147 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
148
149 #define CONFIG_RTC_PCF8563
150 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
151
152 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
153
154 /*-----------------------------------------------------------------------
155  * Miscellaneous configuration options
156  */
157
158 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
159 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
160
161 /*
162  * BOOTP options
163  */
164 #define CONFIG_BOOTP_SUBNETMASK
165 #define CONFIG_BOOTP_GATEWAY
166 #define CONFIG_BOOTP_HOSTNAME
167 #define CONFIG_BOOTP_BOOTPATH
168 #define CONFIG_BOOTP_BOOTFILESIZE
169
170
171 /*
172  * Command line configuration.
173  */
174 #include <config_cmd_default.h>
175
176 #define CONFIG_CMD_BEDBUG
177 #define CONFIG_CMD_DATE
178 #define CONFIG_CMD_DHCP
179 #define CONFIG_CMD_EEPROM
180 #define CONFIG_CMD_I2C
181 #define CONFIG_CMD_NFS
182 #define CONFIG_CMD_SNTP
183
184
185 /*
186  * Miscellaneous configurable options
187  */
188 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
189 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
190 #if defined(CONFIG_CMD_KGDB)
191 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
192 #else
193 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
194 #endif
195 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
196 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
197 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
198
199 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
200 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
201
202 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
203
204 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
205
206 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
207
208 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
209
210 /*
211  * For booting Linux, the board info and command line data
212  * have to be in the first 8 MB of memory, since this is
213  * the maximum mapped by the Linux kernel during initialization.
214  */
215 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
216
217 /*-----------------------------------------------------------------------
218  * Flash configuration
219  */
220
221 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
222 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
223 #define CONFIG_SYS_FLASH_BASE           0xFF000000
224 #define CONFIG_SYS_FLASH_SIZE           0x00800000
225
226 /*-----------------------------------------------------------------------
227  * FLASH organization
228  */
229 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
230 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
231
232 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
233 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
234
235 /*-----------------------------------------------------------------------
236  * Other areas to be mapped
237  */
238
239 /* CS3: Dual ported SRAM */
240 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
241 #define CONFIG_SYS_DPSRAM_SIZE          0x00020000
242
243 /* CS4: DiskOnChip */
244 #define CONFIG_SYS_DOC_BASE             0xF4000000
245 #define CONFIG_SYS_DOC_SIZE             0x00100000
246
247 /* CS5: FDC37C78 controller */
248 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
249 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
250
251 /* CS6: Board configuration registers */
252 #define CONFIG_SYS_BCRS_BASE            0xF2000000
253 #define CONFIG_SYS_BCRS_SIZE            0x00010000
254
255 /* CS7: VME Extended Access Range */
256 #define CONFIG_SYS_VMEEAR_BASE          0x80000000
257 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
258
259 /* CS8: VME Standard Access Range */
260 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
261 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
262
263 /* CS9: VME Short I/O Access Range */
264 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
265 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
266
267 /*-----------------------------------------------------------------------
268  * Hard Reset Configuration Words
269  *
270  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
271  * defines for the various registers affected by the HRCW e.g. changing
272  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
273  */
274 #if defined(CONFIG_BOOT_ROM)
275 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
276                                  HRCW_BPS01 | HRCW_CS10PC01)
277 #else
278 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
279 #endif
280
281 /* no slaves so just fill with zeros */
282 #define CONFIG_SYS_HRCW_SLAVE1          0
283 #define CONFIG_SYS_HRCW_SLAVE2          0
284 #define CONFIG_SYS_HRCW_SLAVE3          0
285 #define CONFIG_SYS_HRCW_SLAVE4          0
286 #define CONFIG_SYS_HRCW_SLAVE5          0
287 #define CONFIG_SYS_HRCW_SLAVE6          0
288 #define CONFIG_SYS_HRCW_SLAVE7          0
289
290 /*-----------------------------------------------------------------------
291  * Internal Memory Mapped Register
292  */
293 #define CONFIG_SYS_IMMR         0xF0000000
294
295 /*-----------------------------------------------------------------------
296  * Definitions for initial stack pointer and data area (in DPRAM)
297  */
298 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
299 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
300 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
301 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
302
303 /*-----------------------------------------------------------------------
304  * Start addresses for the final memory configuration
305  * (Set up by the startup code)
306  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
307  *
308  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
309  */
310 #define CONFIG_SYS_SDRAM_BASE           0x00000000
311 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
312 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
313 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
314 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
315
316 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
317 # define CONFIG_SYS_RAMBOOT
318 #endif
319
320 #if 0
321 /* environment is in Flash */
322 #define CONFIG_ENV_IS_IN_FLASH  1
323 #ifdef CONFIG_BOOT_ROM
324 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
325 # define CONFIG_ENV_SIZE                0x10000
326 # define CONFIG_ENV_SECT_SIZE   0x10000
327 #endif
328 #else
329 /* environment is in EEPROM */
330 #define CONFIG_ENV_IS_IN_EEPROM 1
331 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
332 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
333 /* mask of address bits that overflow into the "EEPROM chip address"    */
334 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
335 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
336 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
337 #define CONFIG_ENV_OFFSET               512
338 #define CONFIG_ENV_SIZE         (2048 - 512)
339 #endif
340
341 /*-----------------------------------------------------------------------
342  * Cache Configuration
343  */
344 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
345 #if defined(CONFIG_CMD_KGDB)
346 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
347 #endif
348
349 /*-----------------------------------------------------------------------
350  * HIDx - Hardware Implementation-dependent Registers                    2-11
351  *-----------------------------------------------------------------------
352  * HID0 also contains cache control - initially enable both caches and
353  * invalidate contents, then the final state leaves only the instruction
354  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
355  * but Soft reset does not.
356  *
357  * HID1 has only read-only information - nothing to set.
358  */
359 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
360                          HID0_DCI|HID0_IFEM|HID0_ABE)
361 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
362 #define CONFIG_SYS_HID2        0
363
364 /*-----------------------------------------------------------------------
365  * RMR - Reset Mode Register                                     5-5
366  *-----------------------------------------------------------------------
367  * turn on Checkstop Reset Enable
368  */
369 #define CONFIG_SYS_RMR         RMR_CSRE
370
371 /*-----------------------------------------------------------------------
372  * BCR - Bus Configuration                                       4-25
373  *-----------------------------------------------------------------------
374  */
375 #define BCR_APD01       0x10000000
376 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
377
378 /*-----------------------------------------------------------------------
379  * SIUMCR - SIU Module Configuration                             4-31
380  *-----------------------------------------------------------------------
381  */
382 #define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
383                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
384
385 /*-----------------------------------------------------------------------
386  * SYPCR - System Protection Control                             4-35
387  * SYPCR can only be written once after reset!
388  *-----------------------------------------------------------------------
389  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
390  */
391 #if defined(CONFIG_WATCHDOG)
392 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
393                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
394 #else
395 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
396                          SYPCR_SWRI|SYPCR_SWP)
397 #endif /* CONFIG_WATCHDOG */
398
399 /*-----------------------------------------------------------------------
400  * TMCNTSC - Time Counter Status and Control                     4-40
401  *-----------------------------------------------------------------------
402  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
403  * and enable Time Counter
404  */
405 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
406
407 /*-----------------------------------------------------------------------
408  * PISCR - Periodic Interrupt Status and Control                 4-42
409  *-----------------------------------------------------------------------
410  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
411  * Periodic timer
412  */
413 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
414
415 /*-----------------------------------------------------------------------
416  * SCCR - System Clock Control                                   9-8
417  *-----------------------------------------------------------------------
418  * Ensure DFBRG is Divide by 16
419  */
420 #define CONFIG_SYS_SCCR        SCCR_DFBRG01
421
422 /*-----------------------------------------------------------------------
423  * RCCR - RISC Controller Configuration                         13-7
424  *-----------------------------------------------------------------------
425  */
426 #define CONFIG_SYS_RCCR        0
427
428 #define CONFIG_SYS_MIN_AM_MASK  0xC0000000
429 /*-----------------------------------------------------------------------
430  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
431  *-----------------------------------------------------------------------
432  */
433 #define CONFIG_SYS_MPTPR       0x1F00
434
435 /*-----------------------------------------------------------------------
436  * PSRT - Refresh Timer Register                                10-16
437  *-----------------------------------------------------------------------
438  */
439 #define CONFIG_SYS_PSRT        0x0f
440
441 /*-----------------------------------------------------------------------
442  * PSRT - SDRAM Mode Register                                   10-10
443  *-----------------------------------------------------------------------
444  */
445
446         /* SDRAM initialization values for 8-column chips
447          */
448 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
449                          ORxS_BPD_4                     |\
450                          ORxS_ROWST_PBI0_A9             |\
451                          ORxS_NUMR_12)
452
453 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
454                          PSDMR_BSMA_A14_A16             |\
455                          PSDMR_SDA10_PBI0_A10           |\
456                          PSDMR_RFRC_7_CLK               |\
457                          PSDMR_PRETOACT_2W              |\
458                          PSDMR_ACTTORW_1W               |\
459                          PSDMR_LDOTOPRE_1C              |\
460                          PSDMR_WRC_1C                   |\
461                          PSDMR_CL_2)
462
463         /* SDRAM initialization values for 9-column chips
464          */
465 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
466                          ORxS_BPD_4                     |\
467                          ORxS_ROWST_PBI0_A7             |\
468                          ORxS_NUMR_13)
469
470 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
471                          PSDMR_BSMA_A13_A15             |\
472                          PSDMR_SDA10_PBI0_A9            |\
473                          PSDMR_RFRC_7_CLK               |\
474                          PSDMR_PRETOACT_2W              |\
475                          PSDMR_ACTTORW_1W               |\
476                          PSDMR_LDOTOPRE_1C              |\
477                          PSDMR_WRC_1C                   |\
478                          PSDMR_CL_2)
479
480 /*
481  * Init Memory Controller:
482  *
483  * Bank Bus     Machine PortSz  Device
484  * ---- ---     ------- ------  ------
485  *  0   60x     GPCM    8  bit  Boot ROM
486  *  1   60x     GPCM    64 bit  FLASH
487  *  2   60x     SDRAM   64 bit  SDRAM
488  *
489  */
490
491 #define CONFIG_SYS_MRS_OFFS     0x00000000
492
493 #ifdef CONFIG_BOOT_ROM
494 /* Bank 0 - Boot ROM
495  */
496 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
497                          BRx_PS_8                       |\
498                          BRx_MS_GPCM_P                  |\
499                          BRx_V)
500
501 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
502                          ORxG_CSNT                      |\
503                          ORxG_ACS_DIV1                  |\
504                          ORxG_SCY_3_CLK                 |\
505                          ORxU_EHTR_8IDLE)
506
507 /* Bank 1 - FLASH
508  */
509 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
510                          BRx_PS_64                      |\
511                          BRx_MS_GPCM_P                  |\
512                          BRx_V)
513
514 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
515                          ORxG_CSNT                      |\
516                          ORxG_ACS_DIV1                  |\
517                          ORxG_SCY_3_CLK                 |\
518                          ORxU_EHTR_8IDLE)
519
520 #else /* CONFIG_BOOT_ROM */
521 /* Bank 0 - FLASH
522  */
523 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
524                          BRx_PS_64                      |\
525                          BRx_MS_GPCM_P                  |\
526                          BRx_V)
527
528 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
529                          ORxG_CSNT                      |\
530                          ORxG_ACS_DIV1                  |\
531                          ORxG_SCY_3_CLK                 |\
532                          ORxU_EHTR_8IDLE)
533
534 /* Bank 1 - Boot ROM
535  */
536 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
537                          BRx_PS_8                       |\
538                          BRx_MS_GPCM_P                  |\
539                          BRx_V)
540
541 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
542                          ORxG_CSNT                      |\
543                          ORxG_ACS_DIV1                  |\
544                          ORxG_SCY_3_CLK                 |\
545                          ORxU_EHTR_8IDLE)
546
547 #endif /* CONFIG_BOOT_ROM */
548
549
550 /* Bank 2 - 60x bus SDRAM
551  */
552 #ifndef CONFIG_SYS_RAMBOOT
553 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
554                          BRx_PS_64                      |\
555                          BRx_MS_SDRAM_P                 |\
556                          BRx_V)
557
558 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_9COL
559
560 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_9COL
561 #endif /* CONFIG_SYS_RAMBOOT */
562
563 /* Bank 3 - Dual Ported SRAM
564  */
565 #define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
566                          BRx_PS_16                      |\
567                          BRx_MS_GPCM_P                  |\
568                          BRx_V)
569
570 #define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)    |\
571                          ORxG_CSNT                      |\
572                          ORxG_ACS_DIV1                  |\
573                          ORxG_SCY_5_CLK                 |\
574                          ORxG_SETA)
575
576 /* Bank 4 - DiskOnChip
577  */
578 #define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)    |\
579                          BRx_PS_8                       |\
580                          BRx_MS_GPCM_P                  |\
581                          BRx_V)
582
583 #define CONFIG_SYS_OR4_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)       |\
584                          ORxG_ACS_DIV2                  |\
585                          ORxG_SCY_5_CLK                 |\
586                          ORxU_EHTR_8IDLE)
587
588 /* Bank 5 - FDC37C78 controller
589  */
590 #define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
591                          BRx_PS_8                         |\
592                          BRx_MS_GPCM_P                    |\
593                          BRx_V)
594
595 #define CONFIG_SYS_OR5_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)    |\
596                          ORxG_ACS_DIV2                    |\
597                          ORxG_SCY_8_CLK                   |\
598                          ORxU_EHTR_8IDLE)
599
600 /* Bank 6 - Board control registers
601  */
602 #define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)   |\
603                          BRx_PS_8                       |\
604                          BRx_MS_GPCM_P                  |\
605                          BRx_V)
606
607 #define CONFIG_SYS_OR6_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)      |\
608                          ORxG_CSNT                      |\
609                          ORxG_SCY_5_CLK)
610
611 /* Bank 7 - VME Extended Access Range
612  */
613 #define CONFIG_SYS_BR7_PRELIM  ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
614                          BRx_PS_32                      |\
615                          BRx_MS_GPCM_P                  |\
616                          BRx_V)
617
618 #define CONFIG_SYS_OR7_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)    |\
619                          ORxG_CSNT                      |\
620                          ORxG_ACS_DIV1                  |\
621                          ORxG_SCY_5_CLK                 |\
622                          ORxG_SETA)
623
624 /* Bank 8 - VME Standard Access Range
625  */
626 #define CONFIG_SYS_BR8_PRELIM  ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
627                          BRx_PS_16                      |\
628                          BRx_MS_GPCM_P                  |\
629                          BRx_V)
630
631 #define CONFIG_SYS_OR8_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)    |\
632                          ORxG_CSNT                      |\
633                          ORxG_ACS_DIV1                  |\
634                          ORxG_SCY_5_CLK                 |\
635                          ORxG_SETA)
636
637 /* Bank 9 - VME Short I/O Access Range
638  */
639 #define CONFIG_SYS_BR9_PRELIM  ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
640                          BRx_PS_16                        |\
641                          BRx_MS_GPCM_P                    |\
642                          BRx_V)
643
644 #define CONFIG_SYS_OR9_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)    |\
645                          ORxG_CSNT                        |\
646                          ORxG_ACS_DIV1                    |\
647                          ORxG_SCY_5_CLK                   |\
648                          ORxG_SETA)
649
650 #endif  /* __CONFIG_H */