3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
28 /*************************************************************************
29 * (c) 2004 esd gmbh Hannover
33 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
35 ************************************************************************/
41 /* This define must be before the core.h include */
42 #define CONFIG_CPCI750 1 /* this is an CPCI750 board */
45 #include <../board/Marvell/include/core.h>
47 /*-----------------------------------------------------*/
49 #include "../board/esd/cpci750/local.h"
52 * High Level Configuration Options
56 #define CONFIG_750FX /* we have a 750FX (override local.h) */
58 #define CONFIG_CPCI750 1 /* this is an CPCI750 board */
60 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
62 #undef CONFIG_ECC /* enable ECC support */
64 /* which initialization functions to call for this board */
65 #define CONFIG_MISC_INIT_R
66 #define CONFIG_BOARD_PRE_INIT
67 #define CONFIG_BOARD_EARLY_INIT_F 1
69 #define CFG_BOARD_NAME "CPCI750"
70 #define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX"
72 /*#define CFG_HUSH_PARSER*/
73 #define CFG_HUSH_PARSER
75 #define CFG_PROMPT_HUSH_PS2 "> "
77 #define CFG_AUTO_COMPLETE 1
79 /* Define which ETH port will be used for connecting the network */
80 #define CFG_ETH_PORT ETH_0
83 * The following defines let you select what serial you want to use
84 * for your console driver.
87 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
88 * cable onto the second DUART channel, change the CFG_DUART port from 1
91 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
92 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
95 #define CONFIG_MPSC_PORT 0
97 /* to change the default ethernet port, use this define (options: 0, 1, 2) */
98 #define CONFIG_NET_MULTI
100 #define CONFIG_ETHER_PORT 0
102 #undef CONFIG_ETHER_PORT_MII /* use RMII */
104 #define CONFIG_BOOTDELAY 5 /* autoboot disabled */
106 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
108 #define CONFIG_ZERO_BOOTDELAY_CHECK
111 #undef CONFIG_BOOTARGS
113 /* -----------------------------------------------------------------------------
114 * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
117 #define CONFIG_IPADDR "192.168.0.185"
119 #define CONFIG_SERIAL "AA000001"
120 #define CONFIG_SERVERIP "10.0.0.79"
121 #define CONFIG_ROOTPATH "/export/nfs_cpci750/%s"
123 #define CONFIG_TESTDRAMDATA y
124 #define CONFIG_TESTDRAMADDRESS n
125 #define CONFIG_TESETDRAMWALK n
127 /* ----------------------------------------------------------------------------- */
130 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
131 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
133 #undef CONFIG_WATCHDOG /* watchdog disabled */
134 #undef CONFIG_ALTIVEC /* undef to disable */
136 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
137 CONFIG_BOOTP_BOOTFILESIZE)
140 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
155 #define CONFIG_DOS_PARTITION
157 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
158 #include <cmd_confdefs.h>
160 #define CONFIG_USE_CPCIDVI
162 #ifdef CONFIG_USE_CPCIDVI
164 #define CONFIG_VIDEO_CT69000
165 #define CONFIG_CFB_CONSOLE
166 #define CONFIG_VIDEO_SW_CURSOR
167 #define CONFIG_VIDEO_LOGO
168 #define CONFIG_I8042_KBD
173 * Miscellaneous configurable options
175 #define CFG_I2C_EEPROM_ADDR_LEN 2
176 #define CFG_I2C_MULTI_EEPROMS
177 #define CFG_I2C_SPEED 80000 /* I2C speed default */
179 #define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */
180 #define CFG_LONGHELP /* undef to save memory */
181 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
182 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
183 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
185 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
187 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
188 #define CFG_MAXARGS 16 /* max number of command args */
189 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
191 /*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */
192 /*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
193 /*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */
196 #define CFG_DRAM_TEST
198 * CFG_DRAM_TEST - enables the following tests.
200 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
201 * Environment variable 'test_dram_data' must be
203 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
204 * addressable. Environment variable
205 * 'test_dram_address' must be set to 'y'.
206 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
207 * This test takes about 6 minutes to test 64 MB.
208 * Environment variable 'test_dram_walk' must be
211 #define CFG_DRAM_TEST
212 #if defined(CFG_DRAM_TEST)
213 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
214 /*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
215 #define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
216 #define CFG_DRAM_TEST_DATA
217 #define CFG_DRAM_TEST_ADDRESS
218 #define CFG_DRAM_TEST_WALK
219 #endif /* CFG_DRAM_TEST */
221 #define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
222 #undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
224 #define CFG_LOAD_ADDR 0x00300000 /* default load address */
226 #define CFG_HZ 1000 /* decr freq: 1ms ticks */
227 #define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
228 #define CFG_BUS_CLK CFG_BUS_HZ
230 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
232 #define CFG_TCLK 133000000
234 /*#define CFG_750FX_HID0 0x8000c084*/
235 #define CFG_750FX_HID0 0x80008484
236 #define CFG_750FX_HID1 0x54800000
237 #define CFG_750FX_HID2 0x00000000
240 * Low Level Configuration Settings
241 * (address mappings, register initial values, etc.)
242 * You should know what you are doing if you make changes here.
245 /*-----------------------------------------------------------------------
246 * Definitions for initial stack pointer and data area
250 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
251 * To an unused memory region. The stack will remain in cache until RAM
254 #undef CFG_INIT_RAM_LOCK
255 /* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */
256 /* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */
257 #define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */
258 #define CFG_INIT_RAM_END 0x1000
259 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
260 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
262 #define RELOCATE_INTERNAL_RAM_ADDR
263 #ifdef RELOCATE_INTERNAL_RAM_ADDR
264 /*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/
265 #define CFG_INTERNAL_RAM_ADDR 0xf1080000
268 /*-----------------------------------------------------------------------
269 * Start addresses for the final memory configuration
270 * (Set up by the startup code)
271 * Please note that CFG_SDRAM_BASE _must_ start at 0
273 #define CFG_SDRAM_BASE 0x00000000
274 /* Dummies for BAT 4-7 */
275 #define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
276 #define CFG_SDRAM2_BASE 0x20000000
277 #define CFG_SDRAM3_BASE 0x30000000
278 #define CFG_SDRAM4_BASE 0x40000000
279 #define CFG_RESET_ADDRESS 0xfff00100
280 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
281 #define CFG_MONITOR_BASE 0xfff00000
282 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */
284 /*-----------------------------------------------------------------------
286 *----------------------------------------------------------------------*/
288 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
289 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
290 #define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
291 #define CFG_FLASH_INCREMENT 0x01000000 /* there is only one bank */
292 #define CFG_FLASH_PROTECTION 1 /* use hardware protection */
293 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
294 #define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */
296 /* areas to map different things with the GT in physical space */
297 #define CFG_DRAM_BANKS 4
299 /* What to put in the bats. */
300 #define CFG_MISC_REGION_BASE 0xf0000000
302 /* Peripheral Device section */
304 /*******************************************************/
305 /* We have on the cpci750 Board : */
306 /* GT-Chipset Register Area */
307 /* GT-Chipset internal SRAM 256k */
308 /* SRAM on external device module */
309 /* Real time clock on external device module */
310 /* dobble UART on external device module */
311 /* Data flash on external device module */
312 /* Boot flash on external device module */
313 /*******************************************************/
314 #define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
315 #define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */
317 #undef MARVEL_STANDARD_CFG
318 #ifndef MARVEL_STANDARD_CFG
319 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
320 #define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
321 /*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */
322 #define CFG_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */
324 #define CFG_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */
325 #define CFG_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */
326 #define CFG_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */
327 #define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */
328 #define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */
330 #define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */
331 #define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */
332 #define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */
333 #define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */
334 #define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */
336 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
339 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
340 #define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */
341 #define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */
342 #define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */
343 #define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */
344 #define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */
346 /* c 4 a 8 2 4 1 c */
347 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
348 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
349 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
350 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
353 /* MPP Control MV64360 Appendix P P. 632*/
354 #define CFG_MPP_CONTROL_0 0x00002222 /* */
355 #define CFG_MPP_CONTROL_1 0x11110000 /* */
356 #define CFG_MPP_CONTROL_2 0x11111111 /* */
357 #define CFG_MPP_CONTROL_3 0x00001111 /* */
358 /* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */
361 #define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/
363 /* setup new config_value for MV64360 DDR-RAM To_do !! */
364 /*# define CFG_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */
365 /*# define CFG_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */
369 pci has low prio 1 and 2
371 Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
373 non registered DRAM */
374 /* 31:26 25:22 21:20 19 18 17 16 */
375 /* 100001 0000 010 0 0 0 0 */
376 /* refresh_count=0x400
377 phisical interleaving disable
378 virtual interleaving enable */
381 # define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
384 /*-----------------------------------------------------------------------
386 *-----------------------------------------------------------------------
389 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
390 #define PCI_HOST_FORCE 1 /* configure as pci host */
391 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
393 #define CONFIG_PCI /* include pci support */
394 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
395 #define CONFIG_PCI_PNP /* do pci plug-and-play */
396 #define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
398 /* PCI MEMORY MAP section */
399 #define CFG_PCI0_MEM_BASE 0x80000000
400 #define CFG_PCI0_MEM_SIZE _128M
401 #define CFG_PCI1_MEM_BASE 0x88000000
402 #define CFG_PCI1_MEM_SIZE _128M
404 #define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
405 #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
407 /* PCI I/O MAP section */
408 #define CFG_PCI0_IO_BASE 0xfa000000
409 #define CFG_PCI0_IO_SIZE _16M
410 #define CFG_PCI1_IO_BASE 0xfb000000
411 #define CFG_PCI1_IO_SIZE _16M
413 #define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
414 #define CFG_PCI0_IO_SPACE_PCI 0x00000000
415 #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
416 #define CFG_PCI1_IO_SPACE_PCI 0x00000000
418 #define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
420 #if defined (CONFIG_750CX)
421 #define CFG_PCI_IDSEL 0x0
423 #define CFG_PCI_IDSEL 0x30
426 /*-----------------------------------------------------------------------
428 *-----------------------------------------------------------------------
430 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
431 #undef CONFIG_IDE_LED /* no led for ide supported */
432 #define CONFIG_IDE_RESET /* no reset for ide supported */
433 #define CONFIG_IDE_PREINIT /* check for units */
435 #define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */
436 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
438 #define CFG_ATA_BASE_ADDR 0
439 #define CFG_ATA_IDE0_OFFSET 0
440 #define CFG_ATA_IDE1_OFFSET 0
442 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
443 #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
444 #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
447 /*----------------------------------------------------------------------
448 * Initial BAT mappings
452 * 1) GUARDED and WRITE_THRU not allowed in IBATS
453 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
457 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
458 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
459 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
460 #define CFG_DBAT0U CFG_IBAT0U
463 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
464 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
465 #define CFG_DBAT1L CFG_IBAT1L
466 #define CFG_DBAT1U CFG_IBAT1U
468 /* PCI0, PCI1 in one BAT */
469 #define CFG_IBAT2L BATL_NO_ACCESS
470 #define CFG_IBAT2U CFG_DBAT2U
471 #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
472 #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
474 /* GT regs, bootrom, all the devices, PCI I/O */
475 #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
476 #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
477 #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
478 #define CFG_DBAT3U CFG_IBAT3U
481 * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
483 * FIXME: ingo disable BATs for Linux Kernel
485 #undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */
486 /*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */
488 #ifdef SETUP_HIGH_BATS_FX750
489 #define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
490 #define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
491 #define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
492 #define CFG_DBAT4U CFG_IBAT4U
494 /* IBAT5 and DBAT5 */
495 #define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
496 #define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
497 #define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
498 #define CFG_DBAT5U CFG_IBAT5U
500 /* IBAT6 and DBAT6 */
501 #define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
502 #define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
503 #define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
504 #define CFG_DBAT6U CFG_IBAT6U
506 /* IBAT7 and DBAT7 */
507 #define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
508 #define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
509 #define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
510 #define CFG_DBAT7U CFG_IBAT7U
512 #else /* set em out of range for Linux !!!!!!!!!!! */
513 #define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
514 #define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
515 #define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
516 #define CFG_DBAT4U CFG_IBAT4U
518 /* IBAT5 and DBAT5 */
519 #define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
520 #define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
521 #define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
522 #define CFG_DBAT5U CFG_IBAT4U
524 /* IBAT6 and DBAT6 */
525 #define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
526 #define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
527 #define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
528 #define CFG_DBAT6U CFG_IBAT4U
530 /* IBAT7 and DBAT7 */
531 #define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
532 #define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
533 #define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
534 #define CFG_DBAT7U CFG_IBAT4U
537 /* FIXME: ingo end: disable BATs for Linux Kernel */
539 /* I2C addresses for the two DIMM SPD chips */
540 #define DIMM0_I2C_ADDR 0x51
541 #define DIMM1_I2C_ADDR 0x52
544 * For booting Linux, the board info and command line data
545 * have to be in the first 8 MB of memory, since this is
546 * the maximum mapped by the Linux kernel during initialization.
548 #define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
550 /*-----------------------------------------------------------------------
553 #define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */
555 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
556 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
557 #define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
560 #define CFG_ENV_IS_IN_FLASH 0
561 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
562 #define CFG_ENV_SECT_SIZE 0x10000
563 #define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
564 /* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
567 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
568 #define CFG_EEPROM_PAGE_WRITE_BITS 5
569 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
570 #define CFG_I2C_EEPROM_ADDR 0x050
571 #define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */
572 #define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/
574 #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
575 #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
576 #define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
578 /*-----------------------------------------------------------------------
579 * Cache Configuration
581 #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
582 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
583 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
586 /*-----------------------------------------------------------------------
587 * L2CR setup -- make sure this is right for your board!
588 * look in include/mpc74xx.h for the defines used here
594 /* #ifdef CONFIG_750CX*/
595 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
598 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
599 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
602 #define L2_ENABLE (L2_INIT | L2CR_L2E)
605 * Internal Definitions
609 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
610 #define BOOTFLAG_WARM 0x02 /* Software reboot */
612 #define CFG_BOARD_ASM_INIT 1
614 #endif /* __CONFIG_H */