3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
43 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
45 #define CONFIG_BAUDRATE 9600
46 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48 #undef CONFIG_BOOTARGS
49 #undef CONFIG_BOOTCOMMAND
51 #define CONFIG_PREBOOT /* enable preboot variable */
53 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
54 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
56 #define CONFIG_PPC4xx_EMAC
57 #define CONFIG_MII 1 /* MII PHY management */
58 #define CONFIG_PHY_ADDR 0 /* PHY address */
59 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
60 #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
62 #define CONFIG_NET_MULTI 1
63 #undef CONFIG_HAS_ETH1
68 #define CONFIG_BOOTP_SUBNETMASK
69 #define CONFIG_BOOTP_GATEWAY
70 #define CONFIG_BOOTP_HOSTNAME
71 #define CONFIG_BOOTP_BOOTPATH
72 #define CONFIG_BOOTP_DNS
73 #define CONFIG_BOOTP_DNS2
74 #define CONFIG_BOOTP_SEND_HOSTNAME
78 * Command line configuration.
80 #include <config_cmd_default.h>
82 #define CONFIG_CMD_DHCP
83 #define CONFIG_CMD_PCI
84 #define CONFIG_CMD_IRQ
85 #define CONFIG_CMD_IDE
86 #define CONFIG_CMD_FAT
87 #define CONFIG_CMD_ELF
88 #define CONFIG_CMD_MII
89 #define CONFIG_CMD_EEPROM
92 #define CONFIG_MAC_PARTITION
93 #define CONFIG_DOS_PARTITION
95 #define CONFIG_SUPPORT_VFAT
97 #undef CONFIG_WATCHDOG /* watchdog disabled */
99 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
102 * Miscellaneous configurable options
104 #define CONFIG_SYS_LONGHELP /* undef to save memory */
105 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
107 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
108 #ifdef CONFIG_SYS_HUSH_PARSER
109 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
112 #if defined(CONFIG_CMD_KGDB)
113 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
115 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
117 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
118 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
119 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
121 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
123 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
125 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
126 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
128 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
129 #define CONFIG_SYS_BASE_BAUD 691200
131 /* The following table includes the supported baudrates */
132 #define CONFIG_SYS_BAUDRATE_TABLE \
133 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
134 57600, 115200, 230400, 460800, 921600 }
136 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
137 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
139 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
141 #define CONFIG_LOOPW 1 /* enable loopw command */
143 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
145 /*-----------------------------------------------------------------------
147 *-----------------------------------------------------------------------
149 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
150 #define PCI_HOST_FORCE 1 /* configure as pci host */
151 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
153 #define CONFIG_PCI /* include pci support */
154 #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
155 #define CONFIG_PCI_PNP /* do pci plug-and-play */
156 /* resource configuration */
158 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
160 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
162 #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
164 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
165 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
166 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
167 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
168 #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
169 #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
170 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
171 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
172 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
173 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
175 #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
177 /*-----------------------------------------------------------------------
179 *-----------------------------------------------------------------------
181 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
182 #undef CONFIG_IDE_LED /* no led for ide supported */
183 #undef CONFIG_IDE_RESET /* no reset for ide supported */
185 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
186 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
188 #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
189 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
191 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
192 #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
193 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
195 /*-----------------------------------------------------------------------
196 * Start addresses for the final memory configuration
197 * (Set up by the startup code)
198 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
200 #define CONFIG_SYS_SDRAM_BASE 0x00000000
201 #define CONFIG_SYS_FLASH_BASE TEXT_BASE
202 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
203 #define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
204 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
207 * For booting Linux, the board info and command line data
208 * have to be in the first 8 MB of memory, since this is
209 * the maximum mapped by the Linux kernel during initialization.
211 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
212 /*-----------------------------------------------------------------------
215 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
216 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
218 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
219 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
221 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
222 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
223 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
225 * The following defines are added for buggy IOP480 byte interface.
226 * All other boards should use the standard values (CPCI405 etc.)
228 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
229 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
230 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
232 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
234 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
235 #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
236 #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
238 #if 1 /* Use NVRAM for environment variables */
239 /*-----------------------------------------------------------------------
242 #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
243 #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
244 #define CONFIG_ENV_ADDR \
245 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
247 #else /* Use EEPROM for environment variables */
249 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
250 #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
251 #define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
252 /* total size of a CAT24WC08 is 1024 bytes */
255 /*-----------------------------------------------------------------------
256 * I2C EEPROM (CAT24WC08) for environment
258 #define CONFIG_HARD_I2C /* I2c with hardware support */
259 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
260 #define CONFIG_SYS_I2C_SLAVE 0x7F
262 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
263 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
264 /* mask of address bits that overflow into the "EEPROM chip address" */
265 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
266 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
267 /* 16 byte page write mode using*/
268 /* last 4 bits of the address */
269 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
272 * Init Memory Controller:
274 * BR0/1 and OR0/1 (FLASH)
277 #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
278 #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
280 /*-----------------------------------------------------------------------
281 * External Bus Controller (EBC) Setup
284 /* Memory Bank 0 (Flash Bank 0) initialization */
285 #define CONFIG_SYS_EBC_PB0AP 0x92015480
286 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
288 /* Memory Bank 1 (Flash Bank 1) initialization */
289 #define CONFIG_SYS_EBC_PB1AP 0x92015480
290 #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
292 /* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */
293 #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
294 #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
296 /* Memory Bank 3 (CompactFlash IDE) initialization */
297 #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
298 #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
300 /* Memory Bank 4 (NVRAM) initialization */
301 #define CONFIG_SYS_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
302 #define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
304 /* Memory Bank 5 (Quart) initialization */
305 #define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
306 #define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
308 /*-----------------------------------------------------------------------
312 /* FPGA program pin configuration */
313 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
314 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
315 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
316 #define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
317 #define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
319 /*-----------------------------------------------------------------------
320 * Definitions for initial stack pointer and data area (in data cache)
322 #if 1 /* test-only */
323 #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
325 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
327 #define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
329 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
330 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
331 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
332 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
336 * Internal Definitions
340 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
341 #define BOOTFLAG_WARM 0x02 /* Software reboot */
343 #endif /* __CONFIG_H */