2 * ueberarbeitet durch Christoph Seyfert
4 * (C) Copyright 2004-2005 DENX Software Engineering,
5 * Wolfgang Grandegger <wg@denx.de>
9 * http://www.dave-tech.it
10 * http://www.wawnet.biz
11 * mailto:info@wawnet.biz
13 * Credits: Stefan Roese, Wolfgang Denk
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * board/config.h - configuration options, board specific
38 #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
39 #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
40 #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
41 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
42 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
45 /* Only one of the following two symbols must be defined (default is 25 MHz)
46 * CONFIG_PPCHAMELEON_CLK_25
47 * CONFIG_PPCHAMELEON_CLK_33
49 #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
50 #define CONFIG_PPCHAMELEON_CLK_25
53 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
54 #error "* Two external frequencies (SysClk) are defined! *"
57 #undef CONFIG_PPCHAMELEON_SMI712
62 #undef __DEBUG_START_FROM_SRAM__
63 #define __DISABLE_MACHINE_EXCEPTION__
65 #ifdef __DEBUG_START_FROM_SRAM__
66 #define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
70 * High Level Configuration Options
74 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
75 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
76 #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
78 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
79 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
81 #ifdef CONFIG_PPCHAMELEON_CLK_25
82 # define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
83 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
84 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
86 # error "* External frequency (SysClk) not defined! *"
89 #define CONFIG_UART1_CONSOLE 1 /* Use second UART */
90 #define CONFIG_BAUDRATE 115200
91 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
93 #define CONFIG_VERSION_VARIABLE 1 /* add version variable */
94 #define CONFIG_IDENT_STRING "1"
96 #undef CONFIG_BOOTARGS
99 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
100 #define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
101 #define CONFIG_HAS_ETH1
102 #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
104 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
105 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
108 #define CONFIG_PPC4xx_EMAC
109 #undef CONFIG_EXT_PHY
110 #define CONFIG_NET_MULTI 1
112 #define CONFIG_MII 1 /* MII PHY management */
113 #ifndef CONFIG_EXT_PHY
114 #define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
115 #define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
117 #define CONFIG_PHY_ADDR 2 /* PHY address */
119 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
121 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
127 #define CONFIG_BOOTP_BOOTFILESIZE
128 #define CONFIG_BOOTP_BOOTPATH
129 #define CONFIG_BOOTP_GATEWAY
130 #define CONFIG_BOOTP_HOSTNAME
134 * Command line configuration.
136 #include <config_cmd_default.h>
138 #define CONFIG_CMD_DHCP
139 #define CONFIG_CMD_ELF
140 #define CONFIG_CMD_EEPROM
141 #define CONFIG_CMD_I2C
142 #define CONFIG_CMD_IRQ
143 #define CONFIG_CMD_JFFS2
144 #define CONFIG_CMD_MII
145 #define CONFIG_CMD_NAND
146 #define CONFIG_CMD_NFS
147 #define CONFIG_CMD_SNTP
150 #define CONFIG_MAC_PARTITION
151 #define CONFIG_DOS_PARTITION
153 #undef CONFIG_WATCHDOG /* watchdog disabled */
155 #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
156 #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
158 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
161 * Miscellaneous configurable options
163 #define CONFIG_SYS_LONGHELP /* undef to save memory */
164 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
166 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
167 #ifdef CONFIG_SYS_HUSH_PARSER
168 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
171 #if defined(CONFIG_CMD_KGDB)
172 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
174 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
176 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
177 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
178 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
180 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
182 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
184 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
185 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
187 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
188 #define CONFIG_SYS_BASE_BAUD 691200
190 /* The following table includes the supported baudrates */
191 #define CONFIG_SYS_BAUDRATE_TABLE \
192 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
193 57600, 115200, 230400, 460800, 921600 }
195 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
196 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
198 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
200 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
202 /*-----------------------------------------------------------------------
204 *-----------------------------------------------------------------------
206 #define CONFIG_SYS_NAND0_BASE 0xFF400000
207 #define CONFIG_SYS_NAND1_BASE 0xFF000000
208 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
209 #define NAND_BIG_DELAY_US 25
211 /* For CATcenter there is only NAND on the module */
212 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
215 #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
216 #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
217 #define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
218 #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
220 #define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
221 #define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
222 #define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
223 #define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
226 #define MACRO_NAND_DISABLE_CE(nandptr) do \
228 switch((unsigned long)nandptr) \
230 case CONFIG_SYS_NAND0_BASE: \
231 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
233 case CONFIG_SYS_NAND1_BASE: \
234 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
239 #define MACRO_NAND_ENABLE_CE(nandptr) do \
241 switch((unsigned long)nandptr) \
243 case CONFIG_SYS_NAND0_BASE: \
244 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
246 case CONFIG_SYS_NAND1_BASE: \
247 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
252 #define MACRO_NAND_CTL_CLRALE(nandptr) do \
254 switch((unsigned long)nandptr) \
256 case CONFIG_SYS_NAND0_BASE: \
257 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
259 case CONFIG_SYS_NAND1_BASE: \
260 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
265 #define MACRO_NAND_CTL_SETALE(nandptr) do \
267 switch((unsigned long)nandptr) \
269 case CONFIG_SYS_NAND0_BASE: \
270 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
272 case CONFIG_SYS_NAND1_BASE: \
273 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
278 #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
280 switch((unsigned long)nandptr) \
282 case CONFIG_SYS_NAND0_BASE: \
283 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
285 case CONFIG_SYS_NAND1_BASE: \
286 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
291 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
292 switch((unsigned long)nandptr) { \
293 case CONFIG_SYS_NAND0_BASE: \
294 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
296 case CONFIG_SYS_NAND1_BASE: \
297 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
303 /* constant delay (see also tR in the datasheet) */
304 #define NAND_WAIT_READY(nand) do { \
308 /* use the R/B pin */
312 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
313 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
314 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
315 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
317 /*-----------------------------------------------------------------------
319 *-----------------------------------------------------------------------
321 #if 0 /* No PCI on CATcenter */
322 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
323 #define PCI_HOST_FORCE 1 /* configure as pci host */
324 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
326 #define CONFIG_PCI /* include pci support */
327 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
328 #undef CONFIG_PCI_PNP /* do pci plug-and-play */
329 /* resource configuration */
331 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
333 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
334 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
335 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
337 #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
338 #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
339 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
340 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
341 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
342 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
345 /*-----------------------------------------------------------------------
346 * Start addresses for the final memory configuration
347 * (Set up by the startup code)
348 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
350 #define CONFIG_SYS_SDRAM_BASE 0x00000000
351 #define CONFIG_SYS_FLASH_BASE 0xFFFC0000
352 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
353 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
354 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
357 * For booting Linux, the board info and command line data
358 * have to be in the first 8 MB of memory, since this is
359 * the maximum mapped by the Linux kernel during initialization.
361 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
362 /*-----------------------------------------------------------------------
365 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
366 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
368 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
369 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
371 #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
372 #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
373 #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
375 * The following defines are added for buggy IOP480 byte interface.
376 * All other boards should use the standard values (CPCI405 etc.)
378 #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
379 #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
380 #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
382 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
384 /*-----------------------------------------------------------------------
385 * Environment Variable setup
387 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
388 #define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
389 #define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
390 #define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
391 #define CONFIG_ENV_SIZE_REDUND 0x2000
393 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
395 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
396 #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
398 /*-----------------------------------------------------------------------
399 * I2C EEPROM (CAT24WC16) for environment
401 #define CONFIG_HARD_I2C /* I2c with hardware support */
402 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
403 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
404 #define CONFIG_SYS_I2C_SLAVE 0x7F
406 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
407 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
408 /* mask of address bits that overflow into the "EEPROM chip address" */
409 /*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
410 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
411 /* 16 byte page write mode using*/
412 /* last 4 bits of the address */
413 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
416 * Init Memory Controller:
418 * BR0/1 and OR0/1 (FLASH)
421 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
423 /*-----------------------------------------------------------------------
424 * External Bus Controller (EBC) Setup
427 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
428 #define CONFIG_SYS_EBC_PB0AP 0x92015480
429 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
431 /* Memory Bank 1 (External SRAM) initialization */
432 /* Since this must replace NOR Flash, we use the same settings for CS0 */
433 #define CONFIG_SYS_EBC_PB1AP 0x92015480
434 #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
436 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
437 #define CONFIG_SYS_EBC_PB2AP 0x92015480
438 #define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
440 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
441 #define CONFIG_SYS_EBC_PB3AP 0x92015480
442 #define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
444 #ifdef CONFIG_PPCHAMELEON_SMI712
446 * Video console (graphic: SMI LynxEM)
449 #define CONFIG_CFB_CONSOLE
450 #define CONFIG_VIDEO_SMI_LYNXEM
451 #define CONFIG_VIDEO_LOGO
452 /*#define CONFIG_VIDEO_BMP_LOGO*/
453 #define CONFIG_CONSOLE_EXTRA_INFO
454 #define CONFIG_VGA_AS_SINGLE_DEVICE
455 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
456 #define CONFIG_SYS_ISA_IO 0xE8000000
457 /* see also drivers/video/videomodes.c */
458 #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
461 /*-----------------------------------------------------------------------
464 /* FPGA internal regs */
465 #define CONFIG_SYS_FPGA_MODE 0x00
466 #define CONFIG_SYS_FPGA_STATUS 0x02
467 #define CONFIG_SYS_FPGA_TS 0x04
468 #define CONFIG_SYS_FPGA_TS_LOW 0x06
469 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
470 #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
471 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
472 #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
473 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
474 #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
475 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
476 #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
479 #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
480 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
481 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
482 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
484 /* FPGA Status Reg */
485 #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
486 #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
487 #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
488 #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
489 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
491 #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
492 #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
494 /* FPGA program pin configuration */
495 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
496 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
497 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
498 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
499 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
501 /*-----------------------------------------------------------------------
502 * Definitions for initial stack pointer and data area (in data cache)
504 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
505 #define CONFIG_SYS_TEMP_STACK_OCM 1
507 /* On Chip Memory location */
508 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
509 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
510 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
511 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
513 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
514 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
515 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
517 /*-----------------------------------------------------------------------
518 * Definitions for GPIO setup (PPC405EP specific)
520 * GPIO0[0] - External Bus Controller BLAST output
521 * GPIO0[1-9] - Instruction trace outputs -> GPIO
522 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
523 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
524 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
525 * GPIO0[24-27] - UART0 control signal inputs/outputs
526 * GPIO0[28-29] - UART1 data signal input/output
527 * GPIO0[30] - EMAC0 input
528 * GPIO0[31] - EMAC1 reject packet as output
530 #define CONFIG_SYS_GPIO0_OSRH 0x40000550
531 #define CONFIG_SYS_GPIO0_OSRL 0x00000110
532 #define CONFIG_SYS_GPIO0_ISR1H 0x00000000
533 /*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/
534 #define CONFIG_SYS_GPIO0_ISR1L 0x15555444
535 #define CONFIG_SYS_GPIO0_TSRH 0x00000000
536 #define CONFIG_SYS_GPIO0_TSRL 0x00000000
537 #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
540 * Internal Definitions
544 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
545 #define BOOTFLAG_WARM 0x02 /* Software reboot */
548 #define CONFIG_NO_SERIAL_EEPROM
550 /*--------------------------------------------------------------------*/
552 #ifdef CONFIG_NO_SERIAL_EEPROM
555 !-----------------------------------------------------------------------
556 ! Defines for entry options.
557 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
558 ! are plugged in the board will be utilized as non-ECC DIMMs.
559 !-----------------------------------------------------------------------
561 #undef AUTO_MEMORY_CONFIG
562 #define DIMM_READ_ADDR 0xAB
563 #define DIMM_WRITE_ADDR 0xAA
565 /* Defines for CPC0_PLLMR1 Register fields */
566 #define PLL_ACTIVE 0x80000000
567 #define CPC0_PLLMR1_SSCS 0x80000000
568 #define PLL_RESET 0x40000000
569 #define CPC0_PLLMR1_PLLR 0x40000000
570 /* Feedback multiplier */
571 #define PLL_FBKDIV 0x00F00000
572 #define CPC0_PLLMR1_FBDV 0x00F00000
573 #define PLL_FBKDIV_16 0x00000000
574 #define PLL_FBKDIV_1 0x00100000
575 #define PLL_FBKDIV_2 0x00200000
576 #define PLL_FBKDIV_3 0x00300000
577 #define PLL_FBKDIV_4 0x00400000
578 #define PLL_FBKDIV_5 0x00500000
579 #define PLL_FBKDIV_6 0x00600000
580 #define PLL_FBKDIV_7 0x00700000
581 #define PLL_FBKDIV_8 0x00800000
582 #define PLL_FBKDIV_9 0x00900000
583 #define PLL_FBKDIV_10 0x00A00000
584 #define PLL_FBKDIV_11 0x00B00000
585 #define PLL_FBKDIV_12 0x00C00000
586 #define PLL_FBKDIV_13 0x00D00000
587 #define PLL_FBKDIV_14 0x00E00000
588 #define PLL_FBKDIV_15 0x00F00000
589 /* Forward A divisor */
590 #define PLL_FWDDIVA 0x00070000
591 #define CPC0_PLLMR1_FWDVA 0x00070000
592 #define PLL_FWDDIVA_8 0x00000000
593 #define PLL_FWDDIVA_7 0x00010000
594 #define PLL_FWDDIVA_6 0x00020000
595 #define PLL_FWDDIVA_5 0x00030000
596 #define PLL_FWDDIVA_4 0x00040000
597 #define PLL_FWDDIVA_3 0x00050000
598 #define PLL_FWDDIVA_2 0x00060000
599 #define PLL_FWDDIVA_1 0x00070000
600 /* Forward B divisor */
601 #define PLL_FWDDIVB 0x00007000
602 #define CPC0_PLLMR1_FWDVB 0x00007000
603 #define PLL_FWDDIVB_8 0x00000000
604 #define PLL_FWDDIVB_7 0x00001000
605 #define PLL_FWDDIVB_6 0x00002000
606 #define PLL_FWDDIVB_5 0x00003000
607 #define PLL_FWDDIVB_4 0x00004000
608 #define PLL_FWDDIVB_3 0x00005000
609 #define PLL_FWDDIVB_2 0x00006000
610 #define PLL_FWDDIVB_1 0x00007000
612 #define PLL_TUNE_MASK 0x000003FF
613 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
614 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
615 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
616 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
617 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
618 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
619 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
621 /* Defines for CPC0_PLLMR0 Register fields */
623 #define PLL_CPUDIV 0x00300000
624 #define CPC0_PLLMR0_CCDV 0x00300000
625 #define PLL_CPUDIV_1 0x00000000
626 #define PLL_CPUDIV_2 0x00100000
627 #define PLL_CPUDIV_3 0x00200000
628 #define PLL_CPUDIV_4 0x00300000
630 #define PLL_PLBDIV 0x00030000
631 #define CPC0_PLLMR0_CBDV 0x00030000
632 #define PLL_PLBDIV_1 0x00000000
633 #define PLL_PLBDIV_2 0x00010000
634 #define PLL_PLBDIV_3 0x00020000
635 #define PLL_PLBDIV_4 0x00030000
637 #define PLL_OPBDIV 0x00003000
638 #define CPC0_PLLMR0_OPDV 0x00003000
639 #define PLL_OPBDIV_1 0x00000000
640 #define PLL_OPBDIV_2 0x00001000
641 #define PLL_OPBDIV_3 0x00002000
642 #define PLL_OPBDIV_4 0x00003000
644 #define PLL_EXTBUSDIV 0x00000300
645 #define CPC0_PLLMR0_EPDV 0x00000300
646 #define PLL_EXTBUSDIV_2 0x00000000
647 #define PLL_EXTBUSDIV_3 0x00000100
648 #define PLL_EXTBUSDIV_4 0x00000200
649 #define PLL_EXTBUSDIV_5 0x00000300
651 #define PLL_MALDIV 0x00000030
652 #define CPC0_PLLMR0_MPDV 0x00000030
653 #define PLL_MALDIV_1 0x00000000
654 #define PLL_MALDIV_2 0x00000010
655 #define PLL_MALDIV_3 0x00000020
656 #define PLL_MALDIV_4 0x00000030
658 #define PLL_PCIDIV 0x00000003
659 #define CPC0_PLLMR0_PPFD 0x00000003
660 #define PLL_PCIDIV_1 0x00000000
661 #define PLL_PCIDIV_2 0x00000001
662 #define PLL_PCIDIV_3 0x00000002
663 #define PLL_PCIDIV_4 0x00000003
665 #ifdef CONFIG_PPCHAMELEON_CLK_25
666 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
667 #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
668 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
669 PLL_MALDIV_1 | PLL_PCIDIV_4)
670 #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
671 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
672 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
674 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
675 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
676 PLL_MALDIV_1 | PLL_PCIDIV_4)
677 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
678 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
679 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
681 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
682 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
683 PLL_MALDIV_1 | PLL_PCIDIV_4)
684 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
685 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
686 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
688 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
689 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
690 PLL_MALDIV_1 | PLL_PCIDIV_2)
691 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
692 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
693 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
695 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
697 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
698 #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
699 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
700 PLL_MALDIV_1 | PLL_PCIDIV_4)
701 #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
702 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
703 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
705 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
706 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
707 PLL_MALDIV_1 | PLL_PCIDIV_4)
708 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
709 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
710 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
712 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
713 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
714 PLL_MALDIV_1 | PLL_PCIDIV_4)
715 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
716 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
717 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
719 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
720 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
721 PLL_MALDIV_1 | PLL_PCIDIV_2)
722 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
723 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
724 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
727 #error "* External frequency (SysClk) not defined! *"
730 #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
732 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
733 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
734 #define CONFIG_SYS_OPB_FREQ 55555555
736 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
737 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
738 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
739 #define CONFIG_SYS_OPB_FREQ 66666666
741 /* Model BA (default) */
742 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
743 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
744 #define CONFIG_SYS_OPB_FREQ 66666666
747 #endif /* CONFIG_NO_SERIAL_EEPROM */
749 #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
750 #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
756 /* No command line, one static partition */
757 #undef CONFIG_CMD_MTDPARTS
758 #define CONFIG_JFFS2_DEV "nand"
759 #define CONFIG_JFFS2_PART_SIZE 0x00200000
760 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
762 /* mtdparts command line support
764 * Note: fake mtd_id used, no linux mtd map file
767 #define CONFIG_CMD_MTDPARTS
768 #define MTDIDS_DEFAULT "nand0=catcenter"
769 #define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
772 #endif /* __CONFIG_H */