1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
7 * BSC9131 RDB board configuration file
13 #define CONFIG_NAND_FSL_IFC
15 #ifdef CONFIG_SPIFLASH
16 #define CONFIG_RAMBOOT_SPIFLASH
17 #define CONFIG_SYS_RAMBOOT
18 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
22 #define CONFIG_SPL_INIT_MINIMAL
23 #define CONFIG_SPL_NAND_BOOT
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
27 #define CONFIG_SPL_MAX_SIZE 8192
28 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
29 #define CONFIG_SPL_RELOC_STACK 0x00100000
30 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
31 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
32 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
33 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
34 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
37 #ifdef CONFIG_SPL_BUILD
38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
40 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
43 /* High Level Configuration Options */
45 #define CONFIG_ENV_OVERWRITE
47 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
48 #if defined(CONFIG_SYS_CLK_100)
49 #define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
51 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
54 #define CONFIG_HWCONFIG
56 * These can be toggled for performance analysis, otherwise use default.
58 #define CONFIG_L2_CACHE /* toggle L2 cache */
59 #define CONFIG_BTB /* enable branch predition */
61 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
62 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
65 #undef CONFIG_SYS_DDR_RAW_TIMING
67 #define CONFIG_SYS_SPD_BUS_NUM 0
68 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
70 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73 extern unsigned long get_sdram_size(void);
75 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
76 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
79 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
80 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
82 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
83 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
84 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
86 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
87 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
88 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
89 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
91 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
92 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
93 #define CONFIG_SYS_DDR_RCW_1 0x00000000
94 #define CONFIG_SYS_DDR_RCW_2 0x00000000
95 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
96 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
97 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
98 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
100 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
101 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
102 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
103 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
104 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
105 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
106 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
107 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
108 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
111 * Base addresses -- Note these are effective addresses where the
112 * actual resources get mapped (not physical addresses)
114 /* relocated CCSRBAR */
115 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
116 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
118 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
119 /* CONFIG_SYS_IMMR */
121 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
122 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
127 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
128 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
129 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
130 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
131 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
132 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
133 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
134 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
135 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
136 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
144 /* NAND Flash on IFC */
145 #define CONFIG_SYS_NAND_BASE 0xff800000
146 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
148 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
149 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
150 | CSPR_MSEL_NAND /* MSEL = NAND */ \
152 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
154 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
155 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
156 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
157 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
158 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
159 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
160 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
162 /* NAND Flash Timing Params */
163 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
164 | FTIM0_NAND_TWP(0x05) \
165 | FTIM0_NAND_TWCHT(0x02) \
166 | FTIM0_NAND_TWH(0x04))
167 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
168 | FTIM1_NAND_TWBE(0x1E) \
169 | FTIM1_NAND_TRR(0x07) \
170 | FTIM1_NAND_TRP(0x05))
171 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
172 | FTIM2_NAND_TREH(0x04) \
173 | FTIM2_NAND_TWHRE(0x11))
174 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
176 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
177 #define CONFIG_SYS_MAX_NAND_DEVICE 1
178 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
180 #define CONFIG_SYS_NAND_DDR_LAW 11
182 /* Set up IFC registers for boot location NAND */
183 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
184 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
185 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
186 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
187 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
188 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
189 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
191 #define CONFIG_SYS_INIT_RAM_LOCK
192 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
193 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
195 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
196 - GENERATED_GBL_DATA_SIZE)
197 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
199 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
200 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
203 #undef CONFIG_SERIAL_SOFTWARE_FIFO
204 #define CONFIG_SYS_NS16550_SERIAL
205 #define CONFIG_SYS_NS16550_REG_SIZE 1
206 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
207 #ifdef CONFIG_SPL_BUILD
208 #define CONFIG_NS16550_MIN_FUNCTIONS
211 #define CONFIG_SYS_BAUDRATE_TABLE \
212 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
214 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
216 #define CONFIG_SYS_I2C
217 #define CONFIG_SYS_I2C_FSL
218 #define CONFIG_SYS_FSL_I2C_SPEED 400000
219 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
220 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
223 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
225 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
227 /* eSPI - Enhanced SPI */
229 #if defined(CONFIG_TSEC_ENET)
231 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
232 #define CONFIG_TSEC1 1
233 #define CONFIG_TSEC1_NAME "eTSEC1"
234 #define CONFIG_TSEC2 1
235 #define CONFIG_TSEC2_NAME "eTSEC2"
237 #define TSEC1_PHY_ADDR 0
238 #define TSEC2_PHY_ADDR 3
240 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
241 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
243 #define TSEC1_PHYIDX 0
245 #define TSEC2_PHYIDX 0
247 #define CONFIG_ETHPRIME "eTSEC1"
249 #endif /* CONFIG_TSEC_ENET */
254 #if defined(CONFIG_RAMBOOT_SPIFLASH)
255 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
256 #define CONFIG_ENV_SECT_SIZE 0x10000
257 #define CONFIG_ENV_SIZE 0x2000
258 #elif defined(CONFIG_NAND)
259 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
260 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
261 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
262 #elif defined(CONFIG_SYS_RAMBOOT)
263 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
264 #define CONFIG_ENV_SIZE 0x2000
267 #define CONFIG_LOADS_ECHO /* echo on for serial download */
268 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
271 * Miscellaneous configurable options
273 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
275 #if defined(CONFIG_CMD_KGDB)
276 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
278 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
280 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
283 * For booting Linux, the board info and command line data
284 * have to be in the first 64 MB of memory, since this is
285 * the maximum mapped by the Linux kernel during initialization.
287 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
288 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
290 #if defined(CONFIG_CMD_KGDB)
291 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
294 #ifdef CONFIG_USB_EHCI_HCD
295 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
296 #define CONFIG_USB_EHCI_FSL
297 #define CONFIG_HAS_FSL_DR_USB
301 * Dynamic MTD Partition support with mtdparts
305 * Environment Configuration
308 #if defined(CONFIG_TSEC_ENET)
309 #define CONFIG_HAS_ETH0
312 #define CONFIG_HOSTNAME "BSC9131rdb"
313 #define CONFIG_ROOTPATH "/opt/nfsroot"
314 #define CONFIG_BOOTFILE "uImage"
315 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
317 #define CONFIG_EXTRA_ENV_SETTINGS \
319 "uboot=" CONFIG_UBOOTPATH "\0" \
320 "loadaddr=1000000\0" \
321 "bootfile=uImage\0" \
322 "consoledev=ttyS0\0" \
323 "ramdiskaddr=2000000\0" \
324 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
325 "fdtaddr=1e00000\0" \
326 "fdtfile=bsc9131rdb.dtb\0" \
328 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
329 "bootm_size=0x37000000\0" \
330 "othbootargs=ramdisk_size=600000 " \
331 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
332 "usbext2boot=setenv bootargs root=/dev/ram rw " \
333 "console=$consoledev,$baudrate $othbootargs; " \
335 "ext2load usb 0:4 $loadaddr $bootfile;" \
336 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
337 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
338 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
340 #define CONFIG_RAMBOOTCOMMAND \
341 "setenv bootargs root=/dev/ram rw " \
342 "console=$consoledev,$baudrate $othbootargs; " \
343 "tftp $ramdiskaddr $ramdiskfile;" \
344 "tftp $loadaddr $bootfile;" \
345 "tftp $fdtaddr $fdtfile;" \
346 "bootm $loadaddr $ramdiskaddr $fdtaddr"
348 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
350 #endif /* __CONFIG_H */