2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 * B4860 QDS board configuration file
13 #define CONFIG_B4860QDS
14 #define CONFIG_PHYS_64BIT
16 #ifdef CONFIG_RAMBOOT_PBL
17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
22 /* Set 1M boot space */
23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
25 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 #define CONFIG_SYS_NO_FLASH
30 /* High Level Configuration Options */
32 #define CONFIG_E500 /* BOOKE e500 family */
33 #define CONFIG_E500MC /* BOOKE e500mc family */
34 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
35 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
36 #define CONFIG_MP /* support multiple processors */
38 #ifndef CONFIG_SYS_TEXT_BASE
39 #define CONFIG_SYS_TEXT_BASE 0xeff80000
42 #ifndef CONFIG_RESET_VECTOR_ADDRESS
43 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
46 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
47 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
48 #define CONFIG_FSL_IFC /* Enable IFC Support */
49 #define CONFIG_PCI /* Enable PCI/PCIE */
50 #define CONFIG_PCIE1 /* PCIE controler 1 */
51 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
52 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
54 #ifndef CONFIG_PPC_B4420
55 #define CONFIG_SYS_SRIO
56 #define CONFIG_SRIO1 /* SRIO port 1 */
57 #define CONFIG_SRIO2 /* SRIO port 2 */
58 #define CONFIG_SRIO_PCIE_BOOT_MASTER
61 #define CONFIG_FSL_LAW /* Use common FSL init code */
63 /* I2C bus multiplexer */
64 #define I2C_MUX_PCA_ADDR 0x77
66 /* VSC Crossbar switches */
67 #define CONFIG_VSC_CROSSBAR
68 #define I2C_CH_DEFAULT 0x8
69 #define I2C_CH_VSC3316 0xc
70 #define I2C_CH_VSC3308 0xd
72 #define VSC3316_TX_ADDRESS 0x70
73 #define VSC3316_RX_ADDRESS 0x71
74 #define VSC3308_TX_ADDRESS 0x02
75 #define VSC3308_RX_ADDRESS 0x03
77 /* IDT clock synthesizers */
78 #define CONFIG_IDT8T49N222A
79 #define I2C_CH_IDT 0x9
81 #define IDT_SERDES1_ADDRESS 0x6E
82 #define IDT_SERDES2_ADDRESS 0x6C
84 #define CONFIG_ENV_OVERWRITE
86 #ifdef CONFIG_SYS_NO_FLASH
87 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
88 #define CONFIG_ENV_IS_NOWHERE
91 #define CONFIG_FLASH_CFI_DRIVER
92 #define CONFIG_SYS_FLASH_CFI
93 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
96 #if defined(CONFIG_SPIFLASH)
97 #define CONFIG_SYS_EXTRA_ENV_RELOC
98 #define CONFIG_ENV_IS_IN_SPI_FLASH
99 #define CONFIG_ENV_SPI_BUS 0
100 #define CONFIG_ENV_SPI_CS 0
101 #define CONFIG_ENV_SPI_MAX_HZ 10000000
102 #define CONFIG_ENV_SPI_MODE 0
103 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
104 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
105 #define CONFIG_ENV_SECT_SIZE 0x10000
106 #elif defined(CONFIG_SDCARD)
107 #define CONFIG_SYS_EXTRA_ENV_RELOC
108 #define CONFIG_ENV_IS_IN_MMC
109 #define CONFIG_SYS_MMC_ENV_DEV 0
110 #define CONFIG_ENV_SIZE 0x2000
111 #define CONFIG_ENV_OFFSET (512 * 1097)
112 #elif defined(CONFIG_NAND)
113 #define CONFIG_SYS_EXTRA_ENV_RELOC
114 #define CONFIG_ENV_IS_IN_NAND
115 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
116 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
117 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
118 #define CONFIG_ENV_IS_IN_REMOTE
119 #define CONFIG_ENV_ADDR 0xffe20000
120 #define CONFIG_ENV_SIZE 0x2000
121 #elif defined(CONFIG_ENV_IS_NOWHERE)
122 #define CONFIG_ENV_SIZE 0x2000
124 #define CONFIG_ENV_IS_IN_FLASH
125 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
126 #define CONFIG_ENV_SIZE 0x2000
127 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
131 unsigned long get_board_sys_clk(void);
132 unsigned long get_board_ddr_clk(void);
134 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
135 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
138 * These can be toggled for performance analysis, otherwise use default.
140 #define CONFIG_SYS_CACHE_STASHING
141 #define CONFIG_BTB /* toggle branch predition */
142 #define CONFIG_DDR_ECC
143 #ifdef CONFIG_DDR_ECC
144 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
145 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
148 #define CONFIG_ENABLE_36BIT_PHYS
150 #ifdef CONFIG_PHYS_64BIT
151 #define CONFIG_ADDR_MAP
152 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
156 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
158 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
159 #define CONFIG_SYS_MEMTEST_END 0x00400000
160 #define CONFIG_SYS_ALT_MEMTEST
161 #define CONFIG_PANIC_HANG /* do not reset board on panic */
164 * Config the L3 Cache as L3 SRAM
166 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
168 #ifdef CONFIG_PHYS_64BIT
169 #define CONFIG_SYS_DCSRBAR 0xf0000000
170 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
174 #define CONFIG_SYS_I2C_EEPROM_NXID
175 #define CONFIG_SYS_EEPROM_BUS_NUM 0
176 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
177 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
178 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
179 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
184 #define CONFIG_VERY_BIG_RAM
185 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
186 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
188 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
189 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
190 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
192 #define CONFIG_DDR_SPD
193 #define CONFIG_SYS_DDR_RAW_TIMING
194 #define CONFIG_FSL_DDR3
195 #define CONFIG_FSL_DDR_INTERACTIVE
197 #define CONFIG_SYS_SPD_BUS_NUM 0
198 #define SPD_EEPROM_ADDRESS1 0x51
199 #define SPD_EEPROM_ADDRESS2 0x53
201 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
202 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
207 #define CONFIG_SYS_FLASH_BASE 0xe0000000
208 #ifdef CONFIG_PHYS_64BIT
209 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
211 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
214 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
215 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
217 CSPR_PORT_SIZE_16 | \
220 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
221 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
222 CSPR_PORT_SIZE_16 | \
225 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
226 /* NOR Flash Timing Params */
227 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
228 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
229 FTIM0_NOR_TEADC(0x04) | \
230 FTIM0_NOR_TEAHC(0x20))
231 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
232 FTIM1_NOR_TRAD_NOR(0x1A) |\
233 FTIM1_NOR_TSEQRAD_NOR(0x13))
234 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
235 FTIM2_NOR_TCH(0x0E) | \
236 FTIM2_NOR_TWPH(0x0E) | \
238 #define CONFIG_SYS_NOR_FTIM3 0x0
240 #define CONFIG_SYS_FLASH_QUIET_TEST
241 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
243 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
244 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
245 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
248 #define CONFIG_SYS_FLASH_EMPTY_INFO
249 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
250 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
252 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
253 #define CONFIG_FSL_QIXIS_V2
254 #define QIXIS_BASE 0xffdf0000
255 #ifdef CONFIG_PHYS_64BIT
256 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
258 #define QIXIS_BASE_PHYS QIXIS_BASE
260 #define QIXIS_LBMAP_SWITCH 0x01
261 #define QIXIS_LBMAP_MASK 0x0f
262 #define QIXIS_LBMAP_SHIFT 0
263 #define QIXIS_LBMAP_DFLTBANK 0x00
264 #define QIXIS_LBMAP_ALTBANK 0x02
265 #define QIXIS_RST_CTL_RESET 0x31
266 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
267 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
268 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
270 #define CONFIG_SYS_CSPR3_EXT (0xf)
271 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
275 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
276 #define CONFIG_SYS_CSOR3 0x0
277 /* QIXIS Timing parameters for IFC CS3 */
278 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
279 FTIM0_GPCM_TEADC(0x0e) | \
280 FTIM0_GPCM_TEAHC(0x0e))
281 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
282 FTIM1_GPCM_TRAD(0x1f))
283 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
284 FTIM2_GPCM_TCH(0x0) | \
285 FTIM2_GPCM_TWP(0x1f))
286 #define CONFIG_SYS_CS3_FTIM3 0x0
288 /* NAND Flash on IFC */
289 #define CONFIG_NAND_FSL_IFC
290 #define CONFIG_SYS_NAND_BASE 0xff800000
291 #ifdef CONFIG_PHYS_64BIT
292 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
294 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
297 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
298 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
299 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
300 | CSPR_MSEL_NAND /* MSEL = NAND */ \
302 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
304 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
305 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
306 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
307 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
308 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
309 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
310 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
312 #define CONFIG_SYS_NAND_ONFI_DETECTION
314 /* ONFI NAND Flash mode0 Timing Params */
315 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
316 FTIM0_NAND_TWP(0x18) | \
317 FTIM0_NAND_TWCHT(0x07) | \
318 FTIM0_NAND_TWH(0x0a))
319 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
320 FTIM1_NAND_TWBE(0x39) | \
321 FTIM1_NAND_TRR(0x0e) | \
322 FTIM1_NAND_TRP(0x18))
323 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
324 FTIM2_NAND_TREH(0x0a) | \
325 FTIM2_NAND_TWHRE(0x1e))
326 #define CONFIG_SYS_NAND_FTIM3 0x0
328 #define CONFIG_SYS_NAND_DDR_LAW 11
330 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
331 #define CONFIG_SYS_MAX_NAND_DEVICE 1
332 #define CONFIG_MTD_NAND_VERIFY_WRITE
333 #define CONFIG_CMD_NAND
335 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
337 #if defined(CONFIG_NAND)
338 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
339 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
340 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
341 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
342 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
343 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
344 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
345 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
346 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
347 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
348 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
349 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
350 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
351 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
352 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
353 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
355 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
356 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
357 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
358 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
359 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
360 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
361 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
362 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
363 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
364 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
365 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
366 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
367 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
368 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
369 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
370 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
372 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
373 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
374 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
375 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
376 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
377 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
378 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
379 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
381 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
383 #if defined(CONFIG_RAMBOOT_PBL)
384 #define CONFIG_SYS_RAMBOOT
387 #define CONFIG_BOARD_EARLY_INIT_R
388 #define CONFIG_MISC_INIT_R
390 #define CONFIG_HWCONFIG
392 /* define to use L1 as initial stack */
393 #define CONFIG_L1_INIT_RAM
394 #define CONFIG_SYS_INIT_RAM_LOCK
395 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
396 #ifdef CONFIG_PHYS_64BIT
397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
399 /* The assembler doesn't like typecast */
400 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
401 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
402 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
404 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
405 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
406 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
408 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
410 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
411 GENERATED_GBL_DATA_SIZE)
412 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
414 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
415 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
417 /* Serial Port - controlled on board with jumper J8
421 #define CONFIG_CONS_INDEX 1
422 #define CONFIG_SYS_NS16550
423 #define CONFIG_SYS_NS16550_SERIAL
424 #define CONFIG_SYS_NS16550_REG_SIZE 1
425 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
427 #define CONFIG_SYS_BAUDRATE_TABLE \
428 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
430 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
431 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
432 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
433 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
434 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
435 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
438 /* Use the HUSH parser */
439 #define CONFIG_SYS_HUSH_PARSER
440 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
442 /* pass open firmware flat tree */
443 #define CONFIG_OF_LIBFDT
444 #define CONFIG_OF_BOARD_SETUP
445 #define CONFIG_OF_STDOUT_VIA_ALIAS
447 /* new uImage format support */
449 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
452 #define CONFIG_SYS_I2C
453 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
454 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
455 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
456 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
457 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
458 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
459 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
465 #define CONFIG_RTC_DS3231 1
466 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
471 #ifdef CONFIG_SYS_SRIO
473 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
474 #ifdef CONFIG_PHYS_64BIT
475 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
477 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
479 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
483 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
484 #ifdef CONFIG_PHYS_64BIT
485 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
487 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
489 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
494 * for slave u-boot IMAGE instored in master memory space,
495 * PHYS must be aligned based on the SIZE
497 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
498 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
499 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
500 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
502 * for slave UCODE and ENV instored in master memory space,
503 * PHYS must be aligned based on the SIZE
505 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
506 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
507 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
509 /* slave core release by master*/
510 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
511 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
514 * SRIO_PCIE_BOOT - SLAVE
516 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
517 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
518 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
519 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
523 * eSPI - Enhanced SPI
525 #define CONFIG_FSL_ESPI
526 #define CONFIG_SPI_FLASH
527 #define CONFIG_SPI_FLASH_SST
528 #define CONFIG_CMD_SF
529 #define CONFIG_SF_DEFAULT_SPEED 10000000
530 #define CONFIG_SF_DEFAULT_MODE 0
535 #ifdef CONFIG_PHYS_64BIT
536 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
538 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
543 * Memory space is mapped 1-1, but I/O space must start from 0.
546 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
547 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
548 #ifdef CONFIG_PHYS_64BIT
549 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
550 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
552 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
553 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
555 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
556 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
557 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
558 #ifdef CONFIG_PHYS_64BIT
559 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
561 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
563 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
566 #ifndef CONFIG_NOBQFMAN
567 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
568 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
569 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
570 #ifdef CONFIG_PHYS_64BIT
571 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
573 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
575 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
576 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
577 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
578 #ifdef CONFIG_PHYS_64BIT
579 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
581 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
583 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
585 #define CONFIG_SYS_DPAA_FMAN
587 /* Default address of microcode for the Linux Fman driver */
588 #if defined(CONFIG_SPIFLASH)
590 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
591 * env, so we got 0x110000.
593 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
594 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
595 #elif defined(CONFIG_SDCARD)
597 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
598 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
599 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
601 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
602 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
603 #elif defined(CONFIG_NAND)
604 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
605 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
606 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
608 * Slave has no ucode locally, it can fetch this from remote. When implementing
609 * in two corenet boards, slave's ucode could be stored in master's memory
610 * space, the address can be mapped from slave TLB->slave LAW->
611 * slave SRIO or PCIE outbound window->master inbound window->
612 * master LAW->the ucode address in master's memory space.
614 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
615 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
617 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
618 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
620 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
621 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
622 #endif /* CONFIG_NOBQFMAN */
624 #ifdef CONFIG_SYS_DPAA_FMAN
625 #define CONFIG_FMAN_ENET
626 #define CONFIG_PHYLIB_10G
627 #define CONFIG_PHY_VITESSE
628 #define CONFIG_PHY_TERANETICS
629 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
630 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
631 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
632 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
636 #define CONFIG_PCI_INDIRECT_BRIDGE
637 #define CONFIG_NET_MULTI
638 #define CONFIG_PCI_PNP /* do pci plug-and-play */
641 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
642 #define CONFIG_DOS_PARTITION
643 #endif /* CONFIG_PCI */
645 #ifdef CONFIG_FMAN_ENET
646 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
647 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
649 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
650 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
651 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
654 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
655 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
656 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
657 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
659 #define CONFIG_MII /* MII PHY management */
660 #define CONFIG_ETHPRIME "FM1@DTSEC1"
661 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
667 #define CONFIG_LOADS_ECHO /* echo on for serial download */
668 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
671 * Command line configuration.
673 #include <config_cmd_default.h>
675 #define CONFIG_CMD_DATE
676 #define CONFIG_CMD_DHCP
677 #define CONFIG_CMD_EEPROM
678 #define CONFIG_CMD_ELF
679 #define CONFIG_CMD_ERRATA
680 #define CONFIG_CMD_GREPENV
681 #define CONFIG_CMD_IRQ
682 #define CONFIG_CMD_I2C
683 #define CONFIG_CMD_MII
684 #define CONFIG_CMD_PING
685 #define CONFIG_CMD_REGINFO
686 #define CONFIG_CMD_SETEXPR
689 #define CONFIG_CMD_PCI
690 #define CONFIG_CMD_NET
696 #define CONFIG_HAS_FSL_DR_USB
698 #ifdef CONFIG_HAS_FSL_DR_USB
699 #define CONFIG_USB_EHCI
701 #ifdef CONFIG_USB_EHCI
702 #define CONFIG_CMD_USB
703 #define CONFIG_USB_STORAGE
704 #define CONFIG_USB_EHCI_FSL
705 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
706 #define CONFIG_CMD_EXT2
711 * Miscellaneous configurable options
713 #define CONFIG_SYS_LONGHELP /* undef to save memory */
714 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
715 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
716 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
717 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
718 #ifdef CONFIG_CMD_KGDB
719 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
721 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
723 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
724 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
725 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
726 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
729 * For booting Linux, the board info and command line data
730 * have to be in the first 64 MB of memory, since this is
731 * the maximum mapped by the Linux kernel during initialization.
733 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
734 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
736 #ifdef CONFIG_CMD_KGDB
737 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
738 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
742 * Environment Configuration
744 #define CONFIG_ROOTPATH "/opt/nfsroot"
745 #define CONFIG_BOOTFILE "uImage"
746 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
748 /* default location for tftp and bootm */
749 #define CONFIG_LOADADDR 1000000
751 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
753 #define CONFIG_BAUDRATE 115200
755 #define __USB_PHY_TYPE ulpi
757 #define CONFIG_EXTRA_ENV_SETTINGS \
758 "hwconfig=fsl_ddr:ctlr_intlv=null," \
759 "bank_intlv=cs0_cs1;" \
760 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
762 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
763 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
764 "tftpflash=tftpboot $loadaddr $uboot && " \
765 "protect off $ubootaddr +$filesize && " \
766 "erase $ubootaddr +$filesize && " \
767 "cp.b $loadaddr $ubootaddr $filesize && " \
768 "protect on $ubootaddr +$filesize && " \
769 "cmp.b $loadaddr $ubootaddr $filesize\0" \
770 "consoledev=ttyS0\0" \
771 "ramdiskaddr=2000000\0" \
772 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
774 "fdtfile=b4860qds/b4860qds.dtb\0" \
778 /* For emulation this causes u-boot to jump to the start of the proof point
779 app code automatically */
780 #define CONFIG_PROOF_POINTS \
781 "setenv bootargs root=/dev/$bdev rw " \
782 "console=$consoledev,$baudrate $othbootargs;" \
783 "cpu 1 release 0x29000000 - - -;" \
784 "cpu 2 release 0x29000000 - - -;" \
785 "cpu 3 release 0x29000000 - - -;" \
786 "cpu 4 release 0x29000000 - - -;" \
787 "cpu 5 release 0x29000000 - - -;" \
788 "cpu 6 release 0x29000000 - - -;" \
789 "cpu 7 release 0x29000000 - - -;" \
792 #define CONFIG_HVBOOT \
793 "setenv bootargs config-addr=0x60000000; " \
794 "bootm 0x01000000 - 0x00f00000"
797 "setenv bootargs root=/dev/$bdev rw " \
798 "console=$consoledev,$baudrate $othbootargs;" \
799 "cpu 1 release 0x01000000 - - -;" \
800 "cpu 2 release 0x01000000 - - -;" \
801 "cpu 3 release 0x01000000 - - -;" \
802 "cpu 4 release 0x01000000 - - -;" \
803 "cpu 5 release 0x01000000 - - -;" \
804 "cpu 6 release 0x01000000 - - -;" \
805 "cpu 7 release 0x01000000 - - -;" \
808 #define CONFIG_LINUX \
809 "setenv bootargs root=/dev/ram rw " \
810 "console=$consoledev,$baudrate $othbootargs;" \
811 "setenv ramdiskaddr 0x02000000;" \
812 "setenv fdtaddr 0x00c00000;" \
813 "setenv loadaddr 0x1000000;" \
814 "bootm $loadaddr $ramdiskaddr $fdtaddr"
816 #define CONFIG_HDBOOT \
817 "setenv bootargs root=/dev/$bdev rw " \
818 "console=$consoledev,$baudrate $othbootargs;" \
819 "tftp $loadaddr $bootfile;" \
820 "tftp $fdtaddr $fdtfile;" \
821 "bootm $loadaddr - $fdtaddr"
823 #define CONFIG_NFSBOOTCOMMAND \
824 "setenv bootargs root=/dev/nfs rw " \
825 "nfsroot=$serverip:$rootpath " \
826 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
827 "console=$consoledev,$baudrate $othbootargs;" \
828 "tftp $loadaddr $bootfile;" \
829 "tftp $fdtaddr $fdtfile;" \
830 "bootm $loadaddr - $fdtaddr"
832 #define CONFIG_RAMBOOTCOMMAND \
833 "setenv bootargs root=/dev/ram rw " \
834 "console=$consoledev,$baudrate $othbootargs;" \
835 "tftp $ramdiskaddr $ramdiskfile;" \
836 "tftp $loadaddr $bootfile;" \
837 "tftp $fdtaddr $fdtfile;" \
838 "bootm $loadaddr $ramdiskaddr $fdtaddr"
840 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
842 #ifdef CONFIG_SECURE_BOOT
843 #include <asm/fsl_secure_boot.h>
846 #endif /* __CONFIG_H */