2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 * B4860 QDS board configuration file
13 #define CONFIG_B4860QDS
14 #define CONFIG_PHYS_64BIT
16 #ifdef CONFIG_RAMBOOT_PBL
17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
20 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
23 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
24 /* Set 1M boot space */
25 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
26 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
27 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
29 #define CONFIG_SYS_NO_FLASH
32 /* High Level Configuration Options */
34 #define CONFIG_E500 /* BOOKE e500 family */
35 #define CONFIG_E500MC /* BOOKE e500mc family */
36 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
37 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
38 #define CONFIG_MP /* support multiple processors */
40 #ifndef CONFIG_SYS_TEXT_BASE
41 #define CONFIG_SYS_TEXT_BASE 0xeff40000
44 #ifndef CONFIG_RESET_VECTOR_ADDRESS
45 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
48 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
49 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
50 #define CONFIG_FSL_IFC /* Enable IFC Support */
51 #define CONFIG_PCI /* Enable PCI/PCIE */
52 #define CONFIG_PCIE1 /* PCIE controler 1 */
53 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
54 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
56 #ifndef CONFIG_PPC_B4420
57 #define CONFIG_SYS_SRIO
58 #define CONFIG_SRIO1 /* SRIO port 1 */
59 #define CONFIG_SRIO2 /* SRIO port 2 */
60 #define CONFIG_SRIO_PCIE_BOOT_MASTER
63 #define CONFIG_FSL_LAW /* Use common FSL init code */
65 /* I2C bus multiplexer */
66 #define I2C_MUX_PCA_ADDR 0x77
68 /* VSC Crossbar switches */
69 #define CONFIG_VSC_CROSSBAR
70 #define I2C_CH_DEFAULT 0x8
71 #define I2C_CH_VSC3316 0xc
72 #define I2C_CH_VSC3308 0xd
74 #define VSC3316_TX_ADDRESS 0x70
75 #define VSC3316_RX_ADDRESS 0x71
76 #define VSC3308_TX_ADDRESS 0x02
77 #define VSC3308_RX_ADDRESS 0x03
79 /* IDT clock synthesizers */
80 #define CONFIG_IDT8T49N222A
81 #define I2C_CH_IDT 0x9
83 #define IDT_SERDES1_ADDRESS 0x6E
84 #define IDT_SERDES2_ADDRESS 0x6C
86 #define CONFIG_ENV_OVERWRITE
88 #ifdef CONFIG_SYS_NO_FLASH
89 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
90 #define CONFIG_ENV_IS_NOWHERE
93 #define CONFIG_FLASH_CFI_DRIVER
94 #define CONFIG_SYS_FLASH_CFI
95 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
98 #if defined(CONFIG_SPIFLASH)
99 #define CONFIG_SYS_EXTRA_ENV_RELOC
100 #define CONFIG_ENV_IS_IN_SPI_FLASH
101 #define CONFIG_ENV_SPI_BUS 0
102 #define CONFIG_ENV_SPI_CS 0
103 #define CONFIG_ENV_SPI_MAX_HZ 10000000
104 #define CONFIG_ENV_SPI_MODE 0
105 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
106 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
107 #define CONFIG_ENV_SECT_SIZE 0x10000
108 #elif defined(CONFIG_SDCARD)
109 #define CONFIG_SYS_EXTRA_ENV_RELOC
110 #define CONFIG_ENV_IS_IN_MMC
111 #define CONFIG_SYS_MMC_ENV_DEV 0
112 #define CONFIG_ENV_SIZE 0x2000
113 #define CONFIG_ENV_OFFSET (512 * 1097)
114 #elif defined(CONFIG_NAND)
115 #define CONFIG_SYS_EXTRA_ENV_RELOC
116 #define CONFIG_ENV_IS_IN_NAND
117 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
118 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
119 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
120 #define CONFIG_ENV_IS_IN_REMOTE
121 #define CONFIG_ENV_ADDR 0xffe20000
122 #define CONFIG_ENV_SIZE 0x2000
123 #elif defined(CONFIG_ENV_IS_NOWHERE)
124 #define CONFIG_ENV_SIZE 0x2000
126 #define CONFIG_ENV_IS_IN_FLASH
127 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
128 #define CONFIG_ENV_SIZE 0x2000
129 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
133 unsigned long get_board_sys_clk(void);
134 unsigned long get_board_ddr_clk(void);
136 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
137 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
140 * These can be toggled for performance analysis, otherwise use default.
142 #define CONFIG_SYS_CACHE_STASHING
143 #define CONFIG_BTB /* toggle branch predition */
144 #define CONFIG_DDR_ECC
145 #ifdef CONFIG_DDR_ECC
146 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
147 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
150 #define CONFIG_ENABLE_36BIT_PHYS
152 #ifdef CONFIG_PHYS_64BIT
153 #define CONFIG_ADDR_MAP
154 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
158 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
160 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
161 #define CONFIG_SYS_MEMTEST_END 0x00400000
162 #define CONFIG_SYS_ALT_MEMTEST
163 #define CONFIG_PANIC_HANG /* do not reset board on panic */
166 * Config the L3 Cache as L3 SRAM
168 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
170 #ifdef CONFIG_PHYS_64BIT
171 #define CONFIG_SYS_DCSRBAR 0xf0000000
172 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
176 #define CONFIG_SYS_I2C_EEPROM_NXID
177 #define CONFIG_SYS_EEPROM_BUS_NUM 0
178 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
186 #define CONFIG_VERY_BIG_RAM
187 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
188 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
190 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
191 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
192 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
194 #define CONFIG_DDR_SPD
195 #define CONFIG_SYS_DDR_RAW_TIMING
196 #define CONFIG_SYS_FSL_DDR3
197 #define CONFIG_FSL_DDR_INTERACTIVE
199 #define CONFIG_SYS_SPD_BUS_NUM 0
200 #define SPD_EEPROM_ADDRESS1 0x51
201 #define SPD_EEPROM_ADDRESS2 0x53
203 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
204 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
209 #define CONFIG_SYS_FLASH_BASE 0xe0000000
210 #ifdef CONFIG_PHYS_64BIT
211 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
213 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
216 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
217 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
219 CSPR_PORT_SIZE_16 | \
222 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
223 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
224 CSPR_PORT_SIZE_16 | \
227 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
228 /* NOR Flash Timing Params */
229 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
230 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
231 FTIM0_NOR_TEADC(0x04) | \
232 FTIM0_NOR_TEAHC(0x20))
233 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
234 FTIM1_NOR_TRAD_NOR(0x1A) |\
235 FTIM1_NOR_TSEQRAD_NOR(0x13))
236 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
237 FTIM2_NOR_TCH(0x0E) | \
238 FTIM2_NOR_TWPH(0x0E) | \
240 #define CONFIG_SYS_NOR_FTIM3 0x0
242 #define CONFIG_SYS_FLASH_QUIET_TEST
243 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
245 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
246 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
247 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
248 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
250 #define CONFIG_SYS_FLASH_EMPTY_INFO
251 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
252 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
254 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
255 #define CONFIG_FSL_QIXIS_V2
256 #define QIXIS_BASE 0xffdf0000
257 #ifdef CONFIG_PHYS_64BIT
258 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
260 #define QIXIS_BASE_PHYS QIXIS_BASE
262 #define QIXIS_LBMAP_SWITCH 0x01
263 #define QIXIS_LBMAP_MASK 0x0f
264 #define QIXIS_LBMAP_SHIFT 0
265 #define QIXIS_LBMAP_DFLTBANK 0x00
266 #define QIXIS_LBMAP_ALTBANK 0x02
267 #define QIXIS_RST_CTL_RESET 0x31
268 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
269 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
270 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
272 #define CONFIG_SYS_CSPR3_EXT (0xf)
273 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
277 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
278 #define CONFIG_SYS_CSOR3 0x0
279 /* QIXIS Timing parameters for IFC CS3 */
280 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
281 FTIM0_GPCM_TEADC(0x0e) | \
282 FTIM0_GPCM_TEAHC(0x0e))
283 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
284 FTIM1_GPCM_TRAD(0x1f))
285 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
286 FTIM2_GPCM_TCH(0x0) | \
287 FTIM2_GPCM_TWP(0x1f))
288 #define CONFIG_SYS_CS3_FTIM3 0x0
290 /* NAND Flash on IFC */
291 #define CONFIG_NAND_FSL_IFC
292 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
293 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
294 #define CONFIG_SYS_NAND_BASE 0xff800000
295 #ifdef CONFIG_PHYS_64BIT
296 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
298 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
301 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
302 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
303 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
304 | CSPR_MSEL_NAND /* MSEL = NAND */ \
306 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
308 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
309 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
310 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
311 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
312 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
313 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
314 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
316 #define CONFIG_SYS_NAND_ONFI_DETECTION
318 /* ONFI NAND Flash mode0 Timing Params */
319 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
320 FTIM0_NAND_TWP(0x18) | \
321 FTIM0_NAND_TWCHT(0x07) | \
322 FTIM0_NAND_TWH(0x0a))
323 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
324 FTIM1_NAND_TWBE(0x39) | \
325 FTIM1_NAND_TRR(0x0e) | \
326 FTIM1_NAND_TRP(0x18))
327 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
328 FTIM2_NAND_TREH(0x0a) | \
329 FTIM2_NAND_TWHRE(0x1e))
330 #define CONFIG_SYS_NAND_FTIM3 0x0
332 #define CONFIG_SYS_NAND_DDR_LAW 11
334 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
335 #define CONFIG_SYS_MAX_NAND_DEVICE 1
336 #define CONFIG_MTD_NAND_VERIFY_WRITE
337 #define CONFIG_CMD_NAND
339 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
341 #if defined(CONFIG_NAND)
342 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
343 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
344 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
345 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
346 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
347 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
348 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
349 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
350 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
351 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
352 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
353 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
354 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
355 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
356 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
357 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
359 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
360 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
361 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
362 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
363 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
364 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
365 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
366 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
367 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
368 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
369 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
370 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
371 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
372 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
373 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
374 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
376 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
377 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
378 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
379 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
380 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
381 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
382 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
383 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
385 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
387 #if defined(CONFIG_RAMBOOT_PBL)
388 #define CONFIG_SYS_RAMBOOT
391 #define CONFIG_BOARD_EARLY_INIT_R
392 #define CONFIG_MISC_INIT_R
394 #define CONFIG_HWCONFIG
396 /* define to use L1 as initial stack */
397 #define CONFIG_L1_INIT_RAM
398 #define CONFIG_SYS_INIT_RAM_LOCK
399 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
400 #ifdef CONFIG_PHYS_64BIT
401 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
403 /* The assembler doesn't like typecast */
404 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
405 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
406 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
408 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
409 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
412 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
414 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
415 GENERATED_GBL_DATA_SIZE)
416 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
418 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
419 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
421 /* Serial Port - controlled on board with jumper J8
425 #define CONFIG_CONS_INDEX 1
426 #define CONFIG_SYS_NS16550
427 #define CONFIG_SYS_NS16550_SERIAL
428 #define CONFIG_SYS_NS16550_REG_SIZE 1
429 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
431 #define CONFIG_SYS_BAUDRATE_TABLE \
432 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
434 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
435 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
436 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
437 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
438 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
439 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
442 /* Use the HUSH parser */
443 #define CONFIG_SYS_HUSH_PARSER
444 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
446 /* pass open firmware flat tree */
447 #define CONFIG_OF_LIBFDT
448 #define CONFIG_OF_BOARD_SETUP
449 #define CONFIG_OF_STDOUT_VIA_ALIAS
451 /* new uImage format support */
453 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
456 #define CONFIG_SYS_I2C
457 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
458 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
459 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
460 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
461 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
462 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
463 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
469 #define CONFIG_RTC_DS3231 1
470 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
475 #ifdef CONFIG_SYS_SRIO
477 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
478 #ifdef CONFIG_PHYS_64BIT
479 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
481 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
483 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
487 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
488 #ifdef CONFIG_PHYS_64BIT
489 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
491 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
493 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
498 * for slave u-boot IMAGE instored in master memory space,
499 * PHYS must be aligned based on the SIZE
501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
504 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
506 * for slave UCODE and ENV instored in master memory space,
507 * PHYS must be aligned based on the SIZE
509 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
510 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
511 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
513 /* slave core release by master*/
514 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
515 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
518 * SRIO_PCIE_BOOT - SLAVE
520 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
521 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
522 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
523 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
527 * eSPI - Enhanced SPI
529 #define CONFIG_FSL_ESPI
530 #define CONFIG_SPI_FLASH
531 #define CONFIG_SPI_FLASH_SST
532 #define CONFIG_CMD_SF
533 #define CONFIG_SF_DEFAULT_SPEED 10000000
534 #define CONFIG_SF_DEFAULT_MODE 0
539 #ifdef CONFIG_PHYS_64BIT
540 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
542 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
547 * Memory space is mapped 1-1, but I/O space must start from 0.
550 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
551 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
552 #ifdef CONFIG_PHYS_64BIT
553 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
554 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
556 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
557 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
559 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
560 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
561 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
562 #ifdef CONFIG_PHYS_64BIT
563 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
565 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
567 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
570 #ifndef CONFIG_NOBQFMAN
571 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
572 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
573 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
574 #ifdef CONFIG_PHYS_64BIT
575 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
577 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
579 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
580 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
581 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
582 #ifdef CONFIG_PHYS_64BIT
583 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
585 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
587 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
589 #define CONFIG_SYS_DPAA_FMAN
591 #define CONFIG_SYS_DPAA_RMAN
593 /* Default address of microcode for the Linux Fman driver */
594 #if defined(CONFIG_SPIFLASH)
596 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
597 * env, so we got 0x110000.
599 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
600 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
601 #elif defined(CONFIG_SDCARD)
603 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
604 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
605 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
607 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
608 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
609 #elif defined(CONFIG_NAND)
610 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
611 #define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
612 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
614 * Slave has no ucode locally, it can fetch this from remote. When implementing
615 * in two corenet boards, slave's ucode could be stored in master's memory
616 * space, the address can be mapped from slave TLB->slave LAW->
617 * slave SRIO or PCIE outbound window->master inbound window->
618 * master LAW->the ucode address in master's memory space.
620 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
621 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
623 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
624 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
626 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
627 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
628 #endif /* CONFIG_NOBQFMAN */
630 #ifdef CONFIG_SYS_DPAA_FMAN
631 #define CONFIG_FMAN_ENET
632 #define CONFIG_PHYLIB_10G
633 #define CONFIG_PHY_VITESSE
634 #define CONFIG_PHY_TERANETICS
635 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
636 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
637 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
638 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
642 #define CONFIG_PCI_INDIRECT_BRIDGE
643 #define CONFIG_NET_MULTI
644 #define CONFIG_PCI_PNP /* do pci plug-and-play */
647 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
648 #define CONFIG_DOS_PARTITION
649 #endif /* CONFIG_PCI */
651 #ifdef CONFIG_FMAN_ENET
652 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
653 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
655 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
656 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
657 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
660 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
661 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
662 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
663 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
665 #define CONFIG_MII /* MII PHY management */
666 #define CONFIG_ETHPRIME "FM1@DTSEC1"
667 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
673 #define CONFIG_LOADS_ECHO /* echo on for serial download */
674 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
677 * Command line configuration.
679 #include <config_cmd_default.h>
681 #define CONFIG_CMD_DATE
682 #define CONFIG_CMD_DHCP
683 #define CONFIG_CMD_EEPROM
684 #define CONFIG_CMD_ELF
685 #define CONFIG_CMD_ERRATA
686 #define CONFIG_CMD_GREPENV
687 #define CONFIG_CMD_IRQ
688 #define CONFIG_CMD_I2C
689 #define CONFIG_CMD_MII
690 #define CONFIG_CMD_PING
691 #define CONFIG_CMD_REGINFO
692 #define CONFIG_CMD_SETEXPR
695 #define CONFIG_CMD_PCI
696 #define CONFIG_CMD_NET
702 #define CONFIG_HAS_FSL_DR_USB
704 #ifdef CONFIG_HAS_FSL_DR_USB
705 #define CONFIG_USB_EHCI
707 #ifdef CONFIG_USB_EHCI
708 #define CONFIG_CMD_USB
709 #define CONFIG_USB_STORAGE
710 #define CONFIG_USB_EHCI_FSL
711 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
712 #define CONFIG_CMD_EXT2
717 * Miscellaneous configurable options
719 #define CONFIG_SYS_LONGHELP /* undef to save memory */
720 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
721 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
722 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
723 #ifdef CONFIG_CMD_KGDB
724 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
726 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
728 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
729 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
730 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
733 * For booting Linux, the board info and command line data
734 * have to be in the first 64 MB of memory, since this is
735 * the maximum mapped by the Linux kernel during initialization.
737 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
738 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
740 #ifdef CONFIG_CMD_KGDB
741 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
745 * Environment Configuration
747 #define CONFIG_ROOTPATH "/opt/nfsroot"
748 #define CONFIG_BOOTFILE "uImage"
749 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
751 /* default location for tftp and bootm */
752 #define CONFIG_LOADADDR 1000000
754 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
756 #define CONFIG_BAUDRATE 115200
758 #define __USB_PHY_TYPE ulpi
760 #define CONFIG_EXTRA_ENV_SETTINGS \
761 "hwconfig=fsl_ddr:ctlr_intlv=null," \
762 "bank_intlv=cs0_cs1;" \
763 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
765 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
766 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
767 "tftpflash=tftpboot $loadaddr $uboot && " \
768 "protect off $ubootaddr +$filesize && " \
769 "erase $ubootaddr +$filesize && " \
770 "cp.b $loadaddr $ubootaddr $filesize && " \
771 "protect on $ubootaddr +$filesize && " \
772 "cmp.b $loadaddr $ubootaddr $filesize\0" \
773 "consoledev=ttyS0\0" \
774 "ramdiskaddr=2000000\0" \
775 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
777 "fdtfile=b4860qds/b4860qds.dtb\0" \
781 /* For emulation this causes u-boot to jump to the start of the proof point
782 app code automatically */
783 #define CONFIG_PROOF_POINTS \
784 "setenv bootargs root=/dev/$bdev rw " \
785 "console=$consoledev,$baudrate $othbootargs;" \
786 "cpu 1 release 0x29000000 - - -;" \
787 "cpu 2 release 0x29000000 - - -;" \
788 "cpu 3 release 0x29000000 - - -;" \
789 "cpu 4 release 0x29000000 - - -;" \
790 "cpu 5 release 0x29000000 - - -;" \
791 "cpu 6 release 0x29000000 - - -;" \
792 "cpu 7 release 0x29000000 - - -;" \
795 #define CONFIG_HVBOOT \
796 "setenv bootargs config-addr=0x60000000; " \
797 "bootm 0x01000000 - 0x00f00000"
800 "setenv bootargs root=/dev/$bdev rw " \
801 "console=$consoledev,$baudrate $othbootargs;" \
802 "cpu 1 release 0x01000000 - - -;" \
803 "cpu 2 release 0x01000000 - - -;" \
804 "cpu 3 release 0x01000000 - - -;" \
805 "cpu 4 release 0x01000000 - - -;" \
806 "cpu 5 release 0x01000000 - - -;" \
807 "cpu 6 release 0x01000000 - - -;" \
808 "cpu 7 release 0x01000000 - - -;" \
811 #define CONFIG_LINUX \
812 "setenv bootargs root=/dev/ram rw " \
813 "console=$consoledev,$baudrate $othbootargs;" \
814 "setenv ramdiskaddr 0x02000000;" \
815 "setenv fdtaddr 0x00c00000;" \
816 "setenv loadaddr 0x1000000;" \
817 "bootm $loadaddr $ramdiskaddr $fdtaddr"
819 #define CONFIG_HDBOOT \
820 "setenv bootargs root=/dev/$bdev rw " \
821 "console=$consoledev,$baudrate $othbootargs;" \
822 "tftp $loadaddr $bootfile;" \
823 "tftp $fdtaddr $fdtfile;" \
824 "bootm $loadaddr - $fdtaddr"
826 #define CONFIG_NFSBOOTCOMMAND \
827 "setenv bootargs root=/dev/nfs rw " \
828 "nfsroot=$serverip:$rootpath " \
829 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
830 "console=$consoledev,$baudrate $othbootargs;" \
831 "tftp $loadaddr $bootfile;" \
832 "tftp $fdtaddr $fdtfile;" \
833 "bootm $loadaddr - $fdtaddr"
835 #define CONFIG_RAMBOOTCOMMAND \
836 "setenv bootargs root=/dev/ram rw " \
837 "console=$consoledev,$baudrate $othbootargs;" \
838 "tftp $ramdiskaddr $ramdiskfile;" \
839 "tftp $loadaddr $bootfile;" \
840 "tftp $fdtaddr $fdtfile;" \
841 "bootm $loadaddr $ramdiskaddr $fdtaddr"
843 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
845 #include <asm/fsl_secure_boot.h>
847 #endif /* __CONFIG_H */