1 /******************************************************************************
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 850T AdderIIF board. Copied from the FADS stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
8 *******************************************************************************
9 * 2003-JUL: The AdderII is using the following physical memorymap:
10 *******************************************************************************
11 * FA200000 -> FA20FFFF : IMAP internal in the cpu
12 * FE000000 -> FE400000 : flash connected to CS0, setup by 8xxrom
13 * 00000000 -> 00800000 : sdram setup by 8xxrom
14 *******************************************************************************/
18 #include <mpc8xx_irq.h>
20 #define CONFIG_MPC860 1
21 #define CONFIG_MPC860T 1
22 #define CONFIG_ADDERII 1
25 #define MPC8XX_FACT 12 /* Multilpy by 12 */
26 #define MPC8XX_XIN 4000000 /* 4MHz */
27 #define MPC8XX_HZ ( MPC8XX_FACT * MPC8XX_XIN )
29 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
30 #define CONFIG_SDRAM_50MHZ 1
33 /* Default Serial Console, baudrate */
34 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
35 #define CONFIG_BAUDRATE 38400
36 #define CONFIG_LOADS_ECHO 1
38 /* FEC Ethernet controller configurations */
39 #define CONFIG_FEC_ETH 1
40 #define CONFIG_NET_MULTI 1
43 /* Interrupt level assignments.
45 #define FEC_INTERRUPT SIU_LEVEL3 /* FEC interrupt */
47 /* Older kernels need clock in MHz newer in Hz */
48 #define CONFIG_CLOCKS_IN_MHZ 1
50 /* Monitor Functions */
51 #define CONFIG_COMMANDS ( CFG_CMD_ENV | \
58 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
59 #include <cmd_confdefs.h>
61 /* Configuration Settings */
62 #define CFG_PROMPT "=>" /* Monitor Command Prompt */
64 #if ( CONFIG_COMMANDS & CFG_CMD_KGDB )
65 #define CFG_CBSIZE 1024 /* Console I/P buffer size */
67 #define CFG_CBSIZE 256
70 #define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 )
71 /* Print buffer size */
73 #define CFG_MAXARGS 16 /* Max number of cmd args */
74 #define CFG_BARGSIZE CFG_CBSIZE /* Boot args buffer size */
76 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
78 #define CFG_MEMTEST_START 0x00100000 /* Mem test works on */
79 #define CFG_MEMTEST_END 0x00800000 /* 1 ... 8MB in SDRAM */
81 #define CFG_LOAD_ADDR 0x00100000
84 /******************************************************************************
85 ** Low level configuration settings.
86 ** ( adderss mappings, register init values, etc. )
87 ** You should know what you are doing if you make changes here.
88 ******************************************************************************/
89 /* Start address for the final memory configuration set up by startup code
90 ** Please note that CFG_SDRAM_BASE must start at 0
93 #define CFG_SDRAM_BASE 0x00000000
95 #define CFG_FLASH_BASE 0xFE000000
96 #define CFG_FLASH_SIZE (( uint ) ( 4 * 1024 * 1024 )) /* 4MB */
97 #define CFG_MONITOR_BASE CFG_FLASH_BASE
98 #define CFG_MONITOR_LEN ( 256 << 10 ) /* 256 KByte */
99 #define CFG_MALLOC_LEN ( 384 << 10 ) /* 384 KByte SDRAM rsvd */
102 ** For booting Linux, the board info and command line data
103 ** have to be in the first 8 MB of memory, since this is
104 ** the maximum mapped by the Linux kernel during initialization.
106 #define CFG_BOOTMAPSZ ( 8 << 20 ) /* Initial Memory map for Linux */
108 /******************************************************************************
109 ** Flash Organization
110 ******************************************************************************/
112 #define CFG_MAX_FLASH_BANKS 1 /* Max no of flash mem banks */
113 #define CFG_MAX_FLASH_SECT 71 /* Max no of sec on 1 chip */
115 #define CFG_FLASH_ERASE_TOUT 120000 /* Erase flash timeout (ms) */
116 #define CFG_FLASH_WRITE_TOUT 500 /* Write flash timeout (ms) */
118 /******************************************************************************
119 ** U-BOOT Environment variables in Flash
120 ******************************************************************************/
121 #define CFG_ENV_IS_IN_FLASH 1
122 #define CFG_ENV_OFFSET 0x00040000
123 #define CFG_ENV_SIZE 0x10000 /* 64KBytes env space */
124 #define CFG_ENV_SECT_SIZE 0x10000
126 /******************************************************************************
127 ** Cache Configuration
128 ******************************************************************************/
129 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
130 #if ( CONFIG_COMMANDS & CFG_CMD_KGDB )
131 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
134 /******************************************************************************
135 ** Internal memory mapped register
136 ******************************************************************************/
137 #define CFG_IMMR 0xFA200000
138 #define CFG_IMMR_SIZE (( uint) ( 62 * 1024 )) /* 64 KByte res */
140 /* Definitions for initial stack pointer and data area ( in DPRAM ) */
142 #define CFG_INIT_RAM_ADDR CFG_IMMR
143 #define CFG_INIT_RAM_END 0x2F00 /* end of used area in DPRAM */
144 #define CFG_GBL_DATA_SIZE 64
145 #define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE )
146 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
149 /* SIU Module Configuration Register */
150 #define CFG_SIUMCR ( SIUMCR_AEME | SIUMCR_MLRC01 | SIUMCR_DBGC10 )
152 /******************************************************************************
153 ** SYPCR - System protection and control
154 ** SYPCR - can be written only once after reset
155 ******************************************************************************/
156 #if defined( CONFIG_WATCHDOG )
157 #define CFG_SYPCR ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
158 SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
161 #define CFG_SYPCR ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
162 SYPCR_SWF | SYPCR_SWP )
165 /* TBSCR - Time Base Status and Control Register */
166 #define CFG_TBSCR ( TBSCR_REFA | TBSCR_REFB | TBSCR_TBE )
168 /* PISCR - Periodic Interrupt Status and Control */
169 #define CFG_PISCR ( PISCR_PS | PISCR_PITF )
171 /* PLPRCR - PLL, Low-Power, and Reset Control Register */
172 #define CFG_PLPRCR ((( MPC8XX_FACT - 1 ) << PLPRCR_MF_SHIFT ) | \
173 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST )
175 /* SCCR - System Clock and reset Control Register */
176 #define SCCR_MASK SCCR_EBDF11
177 #define CFG_SCCR ( SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
178 SCCR_DFBRG00 | SCCR_DFNL000| SCCR_DFNH000 | \
179 SCCR_DFLCD000 | SCCR_DFALCD00 )
182 /******************************************************************************
183 ** Because of the way the 860 starts up and assigns CS0 the
184 ** entire address space, we have to set the memory controller
185 ** differently. Normally, you write the option register
186 ** first, and then enable the chip select by writing the
187 ** base register. For CS0, you must write the base register
188 ** first, followed by the option register.
189 ******************************************************************************/
191 ** Memory Controller Definitions
192 ** BR0/1/2... and OR0/1/2...
194 /* For AdderII BR0 FLASH */
196 #define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
197 #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
199 /* Flash Timings: ACS = 11, TRLX = 1, CSNT = 0, SCY = 7 */
200 #define CFG_OR_TIMING_FLASH ( OR_ACS_DIV2 | OR_BI | OR_SCY_7_CLK | OR_TRLX )
202 #define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH )
204 #define CFG_OR0_PRELIM CFG_OR0_REMAP
205 #define CFG_BR0_PRELIM (( CFG_FLASH_BASE & BR_BA_MSK ) | \
208 /* For AdderII BR1 SDRAM */
210 #define CFG_PRELIM_OR1_AM 0xFF800000
211 #define CFG_OR1_REMAP ( CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_ACS_DIV2 )
212 #define CFG_OR1_PRELIM ( CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_ACS_DIV2 )
213 #define CFG_BR1_PRELIM ( CFG_SDRAM_BASE | BR_MS_UPMA | BR_V )
216 /*******************************************************************************
217 * Internal Definitions Boot Flags
218 *******************************************************************************/
219 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
220 #define BOOTFLAG_WARM 0x02 /* Software reboot */