3 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
5 * Copyright 2004, 2007 Freescale Semiconductor.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * atum8548 board configuration file
29 * Please refer to doc/README.atum8548 for more info.
35 /* Debug Options, Disable in production
37 #define CONFIG_PANIC_HANG 1
41 /* CPLD Configuration Options */
42 #define MPC85xx_ATUM_CLKOCR 0x80000002
44 /* High Level Configuration Options */
45 #define CONFIG_BOOKE 1 /* BOOKE */
46 #define CONFIG_E500 1 /* BOOKE e500 family */
47 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
48 #define CONFIG_MPC8548 1 /* MPC8548 specific */
50 #define CONFIG_PCI 1 /* enable any pci type devices */
51 #define CONFIG_PCI1 1 /* PCI controller 1 */
52 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
53 #define CONFIG_PCI2 1 /* PCI controller 2 */
54 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
56 #define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
57 #define CONFIG_ENV_OVERWRITE
58 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
59 #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
61 #define CONFIG_DDR_ECC /* only for ECC DDR module */
62 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
63 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
64 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
66 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
68 #define CONFIG_SYS_CLK_FREQ 33000000
71 * These can be toggled for performance analysis, otherwise use default.
73 #define CONFIG_L2_CACHE /* toggle L2 cache */
74 #define CONFIG_BTB /* toggle branch predition */
75 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
76 #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
79 * Only possible on E500 Version 2 or newer cores.
81 #define CONFIG_ENABLE_36BIT_PHYS 1
83 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
85 #define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
86 #define CONFIG_ENABLE_36BIT_PHYS 1
88 #define CFG_MEMTEST_START 0x00200000 /* memtest works on */
89 #define CFG_MEMTEST_END 0x00400000
92 * Base addresses -- Note these are effective addresses where the
93 * actual resources get mapped (not physical addresses)
95 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
96 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
97 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
99 #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
100 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
101 #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
102 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
107 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
108 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
110 #if defined(CONFIG_SPD_EEPROM)
112 * Determine DDR configuration from I2C interface.
114 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
118 * Manually set up DDR parameters
120 #define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */
121 #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
122 #define CFG_DDR_CS0_CONFIG 0x80000102
123 #define CFG_DDR_TIMING_0 0x00260802
124 #define CFG_DDR_TIMING_1 0x38355322
125 #define CFG_DDR_TIMING_2 0x039048c7
126 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
127 #define CFG_DDR_MODE 0x00000432
128 #define CFG_DDR_INTERVAL 0x05150100
129 #define DDR_SDRAM_CFG 0x43000000
132 #undef CONFIG_CLOCKS_IN_MHZ
135 * Local Bus Definitions
139 * FLASH on the Local Bus
140 * based on flash chip S29GL01GP
141 * One bank, 128M, using the CFI driver.
142 * Boot from BR0 bank at 0xf800_0000
145 * Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
146 * Port Size = 16 bits = BRx[19:20] = 10
147 * Use GPCM = BRx[24:26] = 000
148 * Valid = BRx[31] = 1
150 * 0 4 8 12 16 20 24 28
151 * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
154 * Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
155 * Reserved ORx[17:18] = 00
157 * ACS = half cycle delay = ORx[21:22] = 11
158 * SCY = 6 = ORx[24:27] = 0110
159 * TRLX = use relaxed timing = ORx[29] = 1
160 * EAD = use external address latch delay = OR[31] = 1
162 * 0 4 8 12 16 20 24 28
163 * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
166 #define CFG_BOOT_BLOCK 0xf8000000 /* boot TLB block */
167 #define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 128M */
169 #define CFG_BR0_PRELIM 0xf8001001
171 #define CFG_OR0_PRELIM 0xf8000E65
173 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
174 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
175 #undef CFG_FLASH_CHECKSUM
176 #define CFG_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
177 #define CFG_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
180 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
182 #define CFG_FLASH_CFI_DRIVER 1
183 #define CFG_FLASH_CFI 1
184 #define CFG_FLASH_EMPTY_INFO
187 * Flash on the LocalBus
189 #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
192 #define CFG_INIT_RAM_LOCK 1
193 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
194 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
196 #define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
198 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
199 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
200 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
202 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
203 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
206 #define CONFIG_CONS_INDEX 1
207 #undef CONFIG_SERIAL_SOFTWARE_FIFO
209 #define CFG_NS16550_SERIAL
210 #define CFG_NS16550_REG_SIZE 1
211 #define CFG_NS16550_CLK get_bus_freq(0)
213 #define CFG_BAUDRATE_TABLE \
214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
216 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
217 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
219 /* Use the HUSH parser */
220 #define CFG_HUSH_PARSER
221 #ifdef CFG_HUSH_PARSER
222 #define CFG_PROMPT_HUSH_PS2 "> "
225 /* pass open firmware flat tree */
226 #define CONFIG_OF_LIBFDT 1
227 #define CONFIG_OF_BOARD_SETUP 1
232 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
233 #define CONFIG_HARD_I2C /* I2C with hardware support*/
234 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
235 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
236 #define CFG_I2C_EEPROM_ADDR 0x57
237 #define CFG_I2C_SLAVE 0x7F
238 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
239 #define CFG_I2C_OFFSET 0x3000
243 * Memory space is mapped 1-1, but I/O space must start from 0.
245 #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
247 #define CFG_PCI1_MEM_BASE 0x80000000
248 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
249 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
250 #define CFG_PCI1_IO_BASE 0x00000000
251 #define CFG_PCI1_IO_PHYS 0xe2000000
252 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
255 #define CFG_PCI2_MEM_BASE 0xC0000000
256 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
257 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
258 #define CFG_PCI2_IO_BASE 0x00000000
259 #define CFG_PCI2_IO_PHYS 0xe2800000
260 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
264 #define CFG_PCIE1_MEM_BASE 0xa0000000
265 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
266 #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
267 #define CFG_PCIE1_IO_BASE 0x00000000
268 #define CFG_PCIE1_IO_PHYS 0xe3000000
269 #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
273 #if !defined(CONFIG_PCI_PNP)
274 #define PCI_ENET0_IOADDR 0xe0000000
275 #define PCI_ENET0_MEMADDR 0xe0000000
276 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
279 #if defined(CONFIG_PCI)
281 #define CONFIG_NET_MULTI
282 #define CONFIG_PCI_PNP /* do pci plug-and-play */
284 #undef CONFIG_EEPRO100
287 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
289 /* PCI view of System Memory */
290 #define CFG_PCI_MEMORY_BUS 0x00000000
291 #define CFG_PCI_MEMORY_PHYS 0x00000000
292 #define CFG_PCI_MEMORY_SIZE 0x80000000
294 #endif /* CONFIG_PCI */
296 #if defined(CONFIG_TSEC_ENET)
298 #ifndef CONFIG_NET_MULTI
299 #define CONFIG_NET_MULTI 1
302 #define CONFIG_MII 1 /* MII PHY management */
303 #define CONFIG_TSEC1 1
304 #define CONFIG_TSEC1_NAME "eTSEC0"
305 #define CONFIG_TSEC2 1
306 #define CONFIG_TSEC2_NAME "eTSEC1"
307 #define CONFIG_TSEC3 1
308 #define CONFIG_TSEC3_NAME "eTSEC2"
309 #define CONFIG_TSEC4 1
310 #define CONFIG_TSEC4_NAME "eTSEC3"
311 #undef CONFIG_MPC85XX_FEC
313 #define TSEC1_PHY_ADDR 0
314 #define TSEC2_PHY_ADDR 1
315 #define TSEC3_PHY_ADDR 2
316 #define TSEC4_PHY_ADDR 3
318 #define TSEC1_PHYIDX 0
319 #define TSEC2_PHYIDX 0
320 #define TSEC3_PHYIDX 0
321 #define TSEC4_PHYIDX 0
322 #define TSEC1_FLAGS TSEC_GIGABIT
323 #define TSEC2_FLAGS TSEC_GIGABIT
324 #define TSEC3_FLAGS TSEC_GIGABIT
325 #define TSEC4_FLAGS TSEC_GIGABIT
327 /* Options are: eTSEC[0-3] */
328 #define CONFIG_ETHPRIME "eTSEC2"
329 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
330 #endif /* CONFIG_TSEC_ENET */
335 #define CFG_ENV_IS_IN_FLASH 1
336 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
337 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
338 #define CFG_ENV_SIZE 0x2000
340 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
341 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
346 #define CONFIG_BOOTP_BOOTFILESIZE
347 #define CONFIG_BOOTP_BOOTPATH
348 #define CONFIG_BOOTP_GATEWAY
349 #define CONFIG_BOOTP_HOSTNAME
353 * Command line configuration.
355 #include <config_cmd_default.h>
357 #define CONFIG_CMD_PING
358 #define CONFIG_CMD_I2C
359 #define CONFIG_CMD_MII
361 #if defined(CONFIG_PCI)
362 #define CONFIG_CMD_PCI
366 #undef CONFIG_WATCHDOG /* watchdog disabled */
369 * Miscellaneous configurable options
371 #define CFG_LONGHELP /* undef to save memory */
372 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
373 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
374 #if defined(CONFIG_CMD_KGDB)
375 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
377 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
379 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
380 #define CFG_MAXARGS 16 /* max number of command args */
381 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
382 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
385 * For booting Linux, the board info and command line data
386 * have to be in the first 8 MB of memory, since this is
387 * the maximum mapped by the Linux kernel during initialization.
389 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
391 /* Cache Configuration */
392 #define CFG_DCACHE_SIZE 32768
393 #define CFG_CACHELINE_SIZE 32
394 #if defined(CONFIG_CMD_KGDB)
395 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
399 * Internal Definitions
403 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
404 #define BOOTFLAG_WARM 0x02 /* Software reboot */
406 #if defined(CONFIG_CMD_KGDB)
407 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
408 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
412 * Environment Configuration
415 /* The mac addresses for all ethernet interface */
416 #if defined(CONFIG_TSEC_ENET)
417 #define CONFIG_HAS_ETH0
418 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
419 #define CONFIG_HAS_ETH1
420 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
421 #define CONFIG_HAS_ETH2
422 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
423 #define CONFIG_HAS_ETH3
424 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
427 #define CONFIG_IPADDR 10.101.43.142
429 #define CONFIG_HOSTNAME atum
430 #define CONFIG_ROOTPATH /nfsroot
431 #define CONFIG_BOOTFILE /tftpboot/uImage.atum
432 #define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
434 #define CONFIG_SERVERIP 10.101.43.10
435 #define CONFIG_GATEWAYIP 10.101.45.1
436 #define CONFIG_NETMASK 255.255.248.0
438 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
440 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
441 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
443 #define CONFIG_BAUDRATE 115200
445 #define CONFIG_NFSBOOTCOMMAND \
446 "setenv bootargs root=/dev/nfs rw " \
447 "nfsroot=$serverip:$rootpath " \
448 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
449 "console=$consoledev,$baudrate $othbootargs;" \
450 "tftp $loadaddr $bootfile;" \
451 "tftp $dtbaddr $dtbfile;" \
452 "bootm $loadaddr - $dtbaddr"
455 #define CONFIG_RAMBOOTCOMMAND \
456 "setenv bootargs root=/dev/ram rw " \
457 "console=$consoledev,$baudrate $othbootargs;" \
458 "tftp $ramdiskaddr $ramdiskfile;" \
459 "tftp $loadaddr $bootfile;" \
460 "tftp $dtbaddr $dtbfile;" \
461 "bootm $loadaddr $ramdiskaddr $dtbaddr"
463 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
465 #endif /* __CONFIG_H */