2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * (C) Copyright 2000-2004
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * This file contains structures and information for the communication
9 * processor channels. Some CPM control and status is available
10 * throught the MPC8xx internal memory map. See immap.h for details.
11 * This file only contains what I need for the moment, not the total
12 * CPM capabilities. I (or someone else) will add definitions as they
15 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
16 * bytes of the DP RAM and relocates the I2C parameter area to the
17 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
23 #include <linux/config.h>
24 #include <asm/8xx_immap.h>
26 /* CPM Command register.
28 #define CPM_CR_RST ((ushort)0x8000)
29 #define CPM_CR_OPCODE ((ushort)0x0f00)
30 #define CPM_CR_CHAN ((ushort)0x00f0)
31 #define CPM_CR_FLG ((ushort)0x0001)
33 /* Some commands (there are more...later)
35 #define CPM_CR_INIT_TRX ((ushort)0x0000)
36 #define CPM_CR_INIT_RX ((ushort)0x0001)
37 #define CPM_CR_INIT_TX ((ushort)0x0002)
38 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
39 #define CPM_CR_STOP_TX ((ushort)0x0004)
40 #define CPM_CR_RESTART_TX ((ushort)0x0006)
41 #define CPM_CR_SET_GADDR ((ushort)0x0008)
45 #define CPM_CR_CH_SCC1 ((ushort)0x0000)
46 #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
47 #define CPM_CR_CH_SCC2 ((ushort)0x0004)
48 #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
49 #define CPM_CR_CH_SCC3 ((ushort)0x0008)
50 #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
51 #define CPM_CR_CH_SCC4 ((ushort)0x000c)
52 #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
54 #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
57 * DPRAM defines and allocation functions
60 /* The dual ported RAM is multi-functional. Some areas can be (and are
61 * being) used for microcode. There is an area that can only be used
62 * as data ram for buffer descriptors, which is all we use right now.
63 * Currently the first 512 and last 256 bytes are used for microcode.
65 #ifdef CFG_ALLOC_DPRAM
67 #define CPM_DATAONLY_BASE ((uint)0x0800)
68 #define CPM_DATAONLY_SIZE ((uint)0x0700)
69 #define CPM_DP_NOSPACE ((uint)0x7fffffff)
73 #define CPM_SERIAL_BASE 0x0800
74 #define CPM_I2C_BASE 0x0820
75 #define CPM_SPI_BASE 0x0840
76 #define CPM_FEC_BASE 0x0860
77 #define CPM_WLKBD_BASE 0x0880
78 #define CPM_SCC_BASE 0x0900
79 #define CPM_POST_BASE 0x0980
83 #ifndef CFG_CPM_POST_WORD_ADDR
84 #define CPM_POST_WORD_ADDR 0x07FC
86 #define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
89 #ifndef CFG_CPM_BOOTCOUNT_ADDR
90 #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
92 #define CPM_BOOTCOUNT_ADDR CFG_CPM_BOOTCOUNT_ADDR
95 #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
97 /* Export the base address of the communication processor registers
100 extern cpm8xx_t *cpmp; /* Pointer to comm processor */
102 /* Buffer descriptors used by many of the CPM protocols.
104 typedef struct cpm_buf_desc {
105 ushort cbd_sc; /* Status and Control */
106 ushort cbd_datlen; /* Data length in buffer */
107 uint cbd_bufaddr; /* Buffer address in host memory */
110 #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
111 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
112 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
113 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
114 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
115 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
116 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
117 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
118 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
119 #define BD_SC_BR ((ushort)0x0020) /* Break received */
120 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
121 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
122 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
123 #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
125 /* Parameter RAM offsets.
127 #define PROFF_SCC1 ((uint)0x0000)
128 #define PROFF_IIC ((uint)0x0080)
129 #define PROFF_SCC2 ((uint)0x0100)
130 #define PROFF_SPI ((uint)0x0180)
131 #define PROFF_SCC3 ((uint)0x0200)
132 #define PROFF_SMC1 ((uint)0x0280)
133 #define PROFF_SCC4 ((uint)0x0300)
134 #define PROFF_SMC2 ((uint)0x0380)
136 /* Define enough so I can at least use the serial port as a UART.
137 * The MBX uses SMC1 as the host serial port.
139 typedef struct smc_uart {
140 ushort smc_rbase; /* Rx Buffer descriptor base address */
141 ushort smc_tbase; /* Tx Buffer descriptor base address */
142 u_char smc_rfcr; /* Rx function code */
143 u_char smc_tfcr; /* Tx function code */
144 ushort smc_mrblr; /* Max receive buffer length */
145 uint smc_rstate; /* Internal */
146 uint smc_idp; /* Internal */
147 ushort smc_rbptr; /* Internal */
148 ushort smc_ibc; /* Internal */
149 uint smc_rxtmp; /* Internal */
150 uint smc_tstate; /* Internal */
151 uint smc_tdp; /* Internal */
152 ushort smc_tbptr; /* Internal */
153 ushort smc_tbc; /* Internal */
154 uint smc_txtmp; /* Internal */
155 ushort smc_maxidl; /* Maximum idle characters */
156 ushort smc_tmpidl; /* Temporary idle counter */
157 ushort smc_brklen; /* Last received break length */
158 ushort smc_brkec; /* rcv'd break condition counter */
159 ushort smc_brkcr; /* xmt break count register */
160 ushort smc_rmask; /* Temporary bit mask */
163 /* Function code bits.
165 #define SMC_EB ((u_char)0x10) /* Set big endian byte order */
167 /* SMC uart mode register.
169 #define SMCMR_REN ((ushort)0x0001)
170 #define SMCMR_TEN ((ushort)0x0002)
171 #define SMCMR_DM ((ushort)0x000c)
172 #define SMCMR_SM_GCI ((ushort)0x0000)
173 #define SMCMR_SM_UART ((ushort)0x0020)
174 #define SMCMR_SM_TRANS ((ushort)0x0030)
175 #define SMCMR_SM_MASK ((ushort)0x0030)
176 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
177 #define SMCMR_REVD SMCMR_PM_EVEN
178 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
179 #define SMCMR_BS SMCMR_PEN
180 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
181 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
182 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
184 /* SMC2 as Centronics parallel printer. It is half duplex, in that
185 * it can only receive or transmit. The parameter ram values for
186 * each direction are either unique or properly overlap, so we can
187 * include them in one structure.
189 typedef struct smc_centronics {
207 ushort scent_character1;
208 ushort scent_character2;
209 ushort scent_character3;
210 ushort scent_character4;
211 ushort scent_character5;
212 ushort scent_character6;
213 ushort scent_character7;
214 ushort scent_character8;
219 /* Centronics Status Mask Register.
221 #define SMC_CENT_F ((u_char)0x08)
222 #define SMC_CENT_PE ((u_char)0x04)
223 #define SMC_CENT_S ((u_char)0x02)
225 /* SMC Event and Mask register.
227 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
228 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
229 #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
230 #define SMCM_BSY ((unsigned char)0x04)
231 #define SMCM_TX ((unsigned char)0x02)
232 #define SMCM_RX ((unsigned char)0x01)
234 /* Baud rate generators.
236 #define CPM_BRG_RST ((uint)0x00020000)
237 #define CPM_BRG_EN ((uint)0x00010000)
238 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
239 #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
240 #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
241 #define CPM_BRG_ATB ((uint)0x00002000)
242 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
243 #define CPM_BRG_DIV16 ((uint)0x00000001)
245 /* SI Clock Route Register
247 #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
248 #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
249 #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
250 #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
251 #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
252 #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
253 #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
254 #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
258 #define SCC_GSMRH_IRP ((uint)0x00040000)
259 #define SCC_GSMRH_GDE ((uint)0x00010000)
260 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
261 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
262 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
263 #define SCC_GSMRH_REVD ((uint)0x00002000)
264 #define SCC_GSMRH_TRX ((uint)0x00001000)
265 #define SCC_GSMRH_TTX ((uint)0x00000800)
266 #define SCC_GSMRH_CDP ((uint)0x00000400)
267 #define SCC_GSMRH_CTSP ((uint)0x00000200)
268 #define SCC_GSMRH_CDS ((uint)0x00000100)
269 #define SCC_GSMRH_CTSS ((uint)0x00000080)
270 #define SCC_GSMRH_TFL ((uint)0x00000040)
271 #define SCC_GSMRH_RFW ((uint)0x00000020)
272 #define SCC_GSMRH_TXSY ((uint)0x00000010)
273 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
274 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
275 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
276 #define SCC_GSMRH_RTSM ((uint)0x00000002)
277 #define SCC_GSMRH_RSYN ((uint)0x00000001)
279 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
280 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
281 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
282 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
283 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
284 #define SCC_GSMRL_TCI ((uint)0x10000000)
285 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
286 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
287 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
288 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
289 #define SCC_GSMRL_RINV ((uint)0x02000000)
290 #define SCC_GSMRL_TINV ((uint)0x01000000)
291 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
292 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
293 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
294 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
295 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
296 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
297 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
298 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
299 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
300 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
301 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
302 #define SCC_GSMRL_TEND ((uint)0x00040000)
303 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
304 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
305 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
306 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
307 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
308 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
309 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
310 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
311 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
312 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
313 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
314 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
315 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
316 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
317 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
318 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
319 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
320 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
321 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
322 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
323 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
324 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
325 #define SCC_GSMRL_ENR ((uint)0x00000020)
326 #define SCC_GSMRL_ENT ((uint)0x00000010)
327 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
328 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
329 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
330 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
331 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
332 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
333 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
334 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
335 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
336 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
338 #define SCC_TODR_TOD ((ushort)0x8000)
340 /* SCC Event and Mask register.
342 #define SCCM_TXE ((unsigned char)0x10)
343 #define SCCM_BSY ((unsigned char)0x04)
344 #define SCCM_TX ((unsigned char)0x02)
345 #define SCCM_RX ((unsigned char)0x01)
347 typedef struct scc_param {
348 ushort scc_rbase; /* Rx Buffer descriptor base address */
349 ushort scc_tbase; /* Tx Buffer descriptor base address */
350 u_char scc_rfcr; /* Rx function code */
351 u_char scc_tfcr; /* Tx function code */
352 ushort scc_mrblr; /* Max receive buffer length */
353 uint scc_rstate; /* Internal */
354 uint scc_idp; /* Internal */
355 ushort scc_rbptr; /* Internal */
356 ushort scc_ibc; /* Internal */
357 uint scc_rxtmp; /* Internal */
358 uint scc_tstate; /* Internal */
359 uint scc_tdp; /* Internal */
360 ushort scc_tbptr; /* Internal */
361 ushort scc_tbc; /* Internal */
362 uint scc_txtmp; /* Internal */
363 uint scc_rcrc; /* Internal */
364 uint scc_tcrc; /* Internal */
367 /* Function code bits.
369 #define SCC_EB ((u_char)0x10) /* Set big endian byte order */
371 /* CPM Ethernet through SCCx.
373 typedef struct scc_enet {
375 uint sen_cpres; /* Preset CRC */
376 uint sen_cmask; /* Constant mask for CRC */
377 uint sen_crcec; /* CRC Error counter */
378 uint sen_alec; /* alignment error counter */
379 uint sen_disfc; /* discard frame counter */
380 ushort sen_pads; /* Tx short frame pad character */
381 ushort sen_retlim; /* Retry limit threshold */
382 ushort sen_retcnt; /* Retry limit counter */
383 ushort sen_maxflr; /* maximum frame length register */
384 ushort sen_minflr; /* minimum frame length register */
385 ushort sen_maxd1; /* maximum DMA1 length */
386 ushort sen_maxd2; /* maximum DMA2 length */
387 ushort sen_maxd; /* Rx max DMA */
388 ushort sen_dmacnt; /* Rx DMA counter */
389 ushort sen_maxb; /* Max BD byte count */
390 ushort sen_gaddr1; /* Group address filter */
394 uint sen_tbuf0data0; /* Save area 0 - current frame */
395 uint sen_tbuf0data1; /* Save area 1 - current frame */
396 uint sen_tbuf0rba; /* Internal */
397 uint sen_tbuf0crc; /* Internal */
398 ushort sen_tbuf0bcnt; /* Internal */
399 ushort sen_paddrh; /* physical address (MSB) */
401 ushort sen_paddrl; /* physical address (LSB) */
402 ushort sen_pper; /* persistence */
403 ushort sen_rfbdptr; /* Rx first BD pointer */
404 ushort sen_tfbdptr; /* Tx first BD pointer */
405 ushort sen_tlbdptr; /* Tx last BD pointer */
406 uint sen_tbuf1data0; /* Save area 0 - current frame */
407 uint sen_tbuf1data1; /* Save area 1 - current frame */
408 uint sen_tbuf1rba; /* Internal */
409 uint sen_tbuf1crc; /* Internal */
410 ushort sen_tbuf1bcnt; /* Internal */
411 ushort sen_txlen; /* Tx Frame length counter */
412 ushort sen_iaddr1; /* Individual address filter */
416 ushort sen_boffcnt; /* Backoff counter */
418 /* NOTE: Some versions of the manual have the following items
419 * incorrectly documented. Below is the proper order.
421 ushort sen_taddrh; /* temp address (MSB) */
423 ushort sen_taddrl; /* temp address (LSB) */
426 /**********************************************************************
428 * Board specific configuration settings.
430 * Please note that we use the presence of a #define SCC_ENET and/or
431 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
432 **********************************************************************/
435 /*** ADS *************************************************************/
437 #if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
438 /* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
441 #define PROFF_ENET PROFF_SCC1
442 #define CPM_CR_ENET CPM_CR_CH_SCC1
445 #define PA_ENET_RXD ((ushort)0x0001)
446 #define PA_ENET_TXD ((ushort)0x0002)
447 #define PA_ENET_TCLK ((ushort)0x0100)
448 #define PA_ENET_RCLK ((ushort)0x0200)
450 #define PB_ENET_TENA ((uint)0x00001000)
452 #define PC_ENET_CLSN ((ushort)0x0010)
453 #define PC_ENET_RENA ((ushort)0x0020)
455 #define SICR_ENET_MASK ((uint)0x000000ff)
456 #define SICR_ENET_CLKRT ((uint)0x0000002c)
458 /* 68160 PHY control */
460 #define PC_ENET_ETHLOOP ((ushort)0x0800)
461 #define PC_ENET_TPFLDL ((ushort)0x0400)
462 #define PC_ENET_TPSQEL ((ushort)0x0200)
464 #endif /* MPC860ADS */
466 /*** AMX860 **********************************************/
468 #if defined(CONFIG_AMX860)
470 /* This ENET stuff is for the AMX860 with ethernet on SCC1.
473 #define PROFF_ENET PROFF_SCC1
474 #define CPM_CR_ENET CPM_CR_CH_SCC1
477 #define PA_ENET_RXD ((ushort)0x0001)
478 #define PA_ENET_TXD ((ushort)0x0002)
479 #define PA_ENET_TCLK ((ushort)0x0400)
480 #define PA_ENET_RCLK ((ushort)0x0800)
482 #define PB_ENET_TENA ((uint)0x00001000)
484 #define PC_ENET_CLSN ((ushort)0x0010)
485 #define PC_ENET_RENA ((ushort)0x0020)
487 #define SICR_ENET_MASK ((uint)0x000000ff)
488 #define SICR_ENET_CLKRT ((uint)0x0000003e)
490 /* 68160 PHY control */
492 #define PB_ENET_ETHLOOP ((uint)0x00020000)
493 #define PB_ENET_TPFLDL ((uint)0x00010000)
494 #define PB_ENET_TPSQEL ((uint)0x00008000)
495 #define PD_ENET_ETH_EN ((ushort)0x0004)
497 #endif /* CONFIG_AMX860 */
499 /*** BSEIP **********************************************************/
502 /* This ENET stuff is for the MPC823 with ethernet on SCC2.
503 * This is unique to the BSE ip-Engine board.
505 #define PROFF_ENET PROFF_SCC2
506 #define CPM_CR_ENET CPM_CR_CH_SCC2
508 #define PA_ENET_RXD ((ushort)0x0004)
509 #define PA_ENET_TXD ((ushort)0x0008)
510 #define PA_ENET_TCLK ((ushort)0x0100)
511 #define PA_ENET_RCLK ((ushort)0x0200)
512 #define PB_ENET_TENA ((uint)0x00002000)
513 #define PC_ENET_CLSN ((ushort)0x0040)
514 #define PC_ENET_RENA ((ushort)0x0080)
516 /* BSE uses port B and C bits for PHY control also.
518 #define PB_BSE_POWERUP ((uint)0x00000004)
519 #define PB_BSE_FDXDIS ((uint)0x00008000)
520 #define PC_BSE_LOOPBACK ((ushort)0x0800)
522 #define SICR_ENET_MASK ((uint)0x0000ff00)
523 #define SICR_ENET_CLKRT ((uint)0x00002c00)
524 #endif /* CONFIG_BSEIP */
526 /*** BSEIP **********************************************************/
528 #ifdef CONFIG_FLAGADM
529 /* Enet configuration for the FLAGADM */
532 #define PROFF_ENET PROFF_SCC2
533 #define CPM_CR_ENET CPM_CR_CH_SCC2
535 #define PA_ENET_RXD ((ushort)0x0004)
536 #define PA_ENET_TXD ((ushort)0x0008)
537 #define PA_ENET_TCLK ((ushort)0x0100)
538 #define PA_ENET_RCLK ((ushort)0x0400)
539 #define PB_ENET_TENA ((uint)0x00002000)
540 #define PC_ENET_CLSN ((ushort)0x0040)
541 #define PC_ENET_RENA ((ushort)0x0080)
543 #define SICR_ENET_MASK ((uint)0x0000ff00)
544 #define SICR_ENET_CLKRT ((uint)0x00003400)
545 #endif /* CONFIG_FLAGADM */
547 /*** C2MON **********************************************************/
551 # ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */
552 # error "Ethernet on SCC not supported on C2MON Board!"
553 # else /* Use FEC for Fast Ethernet */
558 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
559 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
560 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
561 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
562 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
563 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
564 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
565 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
566 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
567 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
568 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
569 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
570 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
572 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
574 # endif /* CONFIG_FEC_ENET */
575 #endif /* CONFIG_C2MON */
577 /*********************************************************************/
580 /*** CCM and PCU E ***********************************************/
582 /* The PCU E and CCM use the FEC on a MPC860T for Ethernet */
584 #if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
586 #define FEC_ENET /* use FEC for EThernet */
589 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
590 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
591 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
592 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
593 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
594 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
595 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
596 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
597 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
598 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
599 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
600 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
601 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
603 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
605 #endif /* CONFIG_PCU_E, CONFIG_CCM */
607 /*** ELPT860 *********************************************************/
609 #ifdef CONFIG_ELPT860
610 /* Bits in parallel I/O port registers that have to be set/cleared
611 * to configure the pins for SCC1 use.
613 # define PROFF_ENET PROFF_SCC1
614 # define CPM_CR_ENET CPM_CR_CH_SCC1
617 # define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
618 # define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
619 # define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
620 # define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
622 # define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
623 # define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
624 # define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
626 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
627 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
629 # define SICR_ENET_MASK ((uint)0x000000FF)
630 # define SICR_ENET_CLKRT ((uint)0x00000025)
631 #endif /* CONFIG_ELPT860 */
633 /*** ESTEEM 192E **************************************************/
634 #ifdef CONFIG_ESTEEM192E
636 * This ENET stuff is for the MPC850 with ethernet on SCC2. This
637 * is very similar to the RPX-Lite configuration.
638 * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
641 #define PROFF_ENET PROFF_SCC2
642 #define CPM_CR_ENET CPM_CR_CH_SCC2
645 #define PA_ENET_RXD ((ushort)0x0004)
646 #define PA_ENET_TXD ((ushort)0x0008)
647 #define PA_ENET_TCLK ((ushort)0x0200)
648 #define PA_ENET_RCLK ((ushort)0x0800)
649 #define PB_ENET_TENA ((uint)0x00002000)
650 #define PC_ENET_CLSN ((ushort)0x0040)
651 #define PC_ENET_RENA ((ushort)0x0080)
653 #define SICR_ENET_MASK ((uint)0x0000ff00)
654 #define SICR_ENET_CLKRT ((uint)0x00003d00)
656 #define PB_ENET_LOOPBACK ((uint)0x00004000)
657 #define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
661 /*** FADS823 ********************************************************/
663 #if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
664 /* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
666 #ifdef CONFIG_SCC2_ENET
667 #define PROFF_ENET PROFF_SCC2
668 #define CPM_CR_ENET CPM_CR_CH_SCC2
670 #define CPMVEC_ENET CPMVEC_SCC2
673 #ifdef CONFIG_SCC1_ENET
674 #define PROFF_ENET PROFF_SCC1
675 #define CPM_CR_ENET CPM_CR_CH_SCC1
677 #define CPMVEC_ENET CPMVEC_SCC1
680 #define PA_ENET_RXD ((ushort)0x0004)
681 #define PA_ENET_TXD ((ushort)0x0008)
682 #define PA_ENET_TCLK ((ushort)0x0400)
683 #define PA_ENET_RCLK ((ushort)0x0200)
685 #define PB_ENET_TENA ((uint)0x00002000)
687 #define PC_ENET_CLSN ((ushort)0x0040)
688 #define PC_ENET_RENA ((ushort)0x0080)
690 #define SICR_ENET_MASK ((uint)0x0000ff00)
691 #define SICR_ENET_CLKRT ((uint)0x00002e00)
693 #endif /* CONFIG_FADS823FADS */
695 /*** FADS850SAR ********************************************************/
697 #if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
698 /* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of
699 * this may be unique to the FADS850SAR configuration.
700 * Note TENA is on Port B.
702 #define PROFF_ENET PROFF_SCC2
703 #define CPM_CR_ENET CPM_CR_CH_SCC2
705 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
706 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
707 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
708 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
709 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
710 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
711 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
713 #define SICR_ENET_MASK ((uint)0x0000ff00)
714 #define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */
715 #endif /* CONFIG_FADS850SAR */
717 /*** FADS860T********************************************************/
719 #if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
721 * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
723 #ifdef CONFIG_SCC1_ENET
727 #define PROFF_ENET PROFF_SCC1
728 #define CPM_CR_ENET CPM_CR_CH_SCC1
730 #define PA_ENET_RXD ((ushort)0x0001)
731 #define PA_ENET_TXD ((ushort)0x0002)
732 #define PA_ENET_TCLK ((ushort)0x0100)
733 #define PA_ENET_RCLK ((ushort)0x0200)
735 #define PB_ENET_TENA ((uint)0x00001000)
737 #define PC_ENET_CLSN ((ushort)0x0010)
738 #define PC_ENET_RENA ((ushort)0x0020)
740 #define SICR_ENET_MASK ((uint)0x000000ff)
741 #define SICR_ENET_CLKRT ((uint)0x0000002c)
743 #endif /* CONFIG_SCC1_ETHERNET */
746 * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
747 * with ethernet on FEC.
750 #ifdef CONFIG_FEC_ENET
751 #define FEC_ENET /* Use FEC for Ethernet */
752 #endif /* CONFIG_FEC_ENET */
754 #endif /* CONFIG_FADS && CONFIG_MPC86x */
756 /*** FPS850L, FPS860L ************************************************/
758 #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
759 /* Bits in parallel I/O port registers that have to be set/cleared
760 * to configure the pins for SCC2 use.
762 #define PROFF_ENET PROFF_SCC2
763 #define CPM_CR_ENET CPM_CR_CH_SCC2
765 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
766 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
767 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
768 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
770 #define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
771 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
772 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
774 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
775 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
777 #define SICR_ENET_MASK ((uint)0x0000ff00)
778 #define SICR_ENET_CLKRT ((uint)0x00002600)
779 #endif /* CONFIG_FPS850L, CONFIG_FPS860L */
781 /*** GEN860T **********************************************************/
782 #if defined(CONFIG_GEN860T)
786 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
787 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
788 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
789 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
790 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
791 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
792 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
793 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
794 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
795 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
796 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
797 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
798 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
799 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
800 #endif /* CONFIG_GEN860T */
802 /*** GENIETV ********************************************************/
804 #if defined(CONFIG_GENIETV)
805 /* Ethernet is only on SCC2 */
807 #define CONFIG_SCC2_ENET
808 #define PROFF_ENET PROFF_SCC2
809 #define CPM_CR_ENET CPM_CR_CH_SCC2
811 #define CPMVEC_ENET CPMVEC_SCC2
813 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
814 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
815 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
816 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
818 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
820 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
821 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
823 #define SICR_ENET_MASK ((uint)0x0000ff00)
824 #define SICR_ENET_CLKRT ((uint)0x00002e00)
826 #endif /* CONFIG_GENIETV */
828 /*** GTH ******************************************************/
831 #ifdef CONFIG_FEC_ENET
832 #define FEC_ENET /* use FEC for EThernet */
833 #endif /* CONFIG_FEC_ETHERNET */
835 /* This ENET stuff is for GTH 10 Mbit ( SCC ) */
836 #define PROFF_ENET PROFF_SCC1
837 #define CPM_CR_ENET CPM_CR_CH_SCC1
840 #define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
841 #define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
842 #define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
843 #define PA_ENET_RCLK ((ushort)0x0400) /* PA5 */
845 #define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
847 #define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
848 #define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
850 /* NOTE. This is reset for 10Mbit port only */
851 #define PC_ENET_RESET ((ushort)0x0100) /* PC 7 */
853 #define SICR_ENET_MASK ((uint)0x000000ff)
855 /* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
856 #define SICR_ENET_CLKRT ((uint)0x00000037)
858 #endif /* CONFIG_GTH */
860 /*** HERMES-PRO ******************************************************/
862 /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
866 #define FEC_ENET /* use FEC for EThernet */
870 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
871 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
872 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
873 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
874 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
875 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
876 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
877 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
878 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
879 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
880 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
881 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
882 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
884 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
886 #endif /* CONFIG_HERMES */
888 /*** IAD210 **********************************************************/
890 /* The IAD210 uses the FEC on a MPC860P for Ethernet */
892 #if defined(CONFIG_IAD210)
894 # define FEC_ENET /* use FEC for Ethernet */
897 # define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */
898 # define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */
899 # define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */
900 # define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */
901 # define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */
902 # define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */
903 # define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */
904 # define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */
905 # define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */
906 # define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */
907 # define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */
908 # define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */
909 # define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */
911 # define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */
913 #endif /* CONFIG_IAD210 */
915 /*** ICU862 **********************************************************/
917 #if defined(CONFIG_ICU862)
919 #ifdef CONFIG_FEC_ENET
920 #define FEC_ENET /* use FEC for EThernet */
921 #endif /* CONFIG_FEC_ETHERNET */
923 #endif /* CONFIG_ICU862 */
925 /*** IP860 **********************************************************/
927 #if defined(CONFIG_IP860)
928 /* Bits in parallel I/O port registers that have to be set/cleared
929 * to configure the pins for SCC1 use.
931 #define PROFF_ENET PROFF_SCC1
932 #define CPM_CR_ENET CPM_CR_CH_SCC1
934 #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
935 #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
936 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
937 #define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
939 #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
940 #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
941 #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
943 #define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
944 #define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
946 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
947 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
949 #define SICR_ENET_MASK ((uint)0x000000ff)
950 #define SICR_ENET_CLKRT ((uint)0x0000002C)
951 #endif /* CONFIG_IP860 */
953 /*** IVMS8 **********************************************************/
955 /* The IVMS8 uses the FEC on a MPC860T for Ethernet */
957 #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
959 #define FEC_ENET /* use FEC for EThernet */
962 #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
964 #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
966 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
967 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
968 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
969 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
970 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
971 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
972 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
973 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
974 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
975 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
976 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
977 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
978 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
980 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
982 #endif /* CONFIG_IVMS8, CONFIG_IVML24 */
984 /*** KUP4K, KUP4X ****************************************************/
985 /* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
987 #if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
989 #define FEC_ENET /* use FEC for EThernet */
992 #define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
994 #define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
996 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
997 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
998 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
999 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1000 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
1001 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
1002 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
1003 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
1004 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
1005 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
1006 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
1007 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
1008 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
1010 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
1012 #endif /* CONFIG_KUP4K */
1015 /*** LANTEC *********************************************************/
1017 #if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
1018 /* Bits in parallel I/O port registers that have to be set/cleared
1019 * to configure the pins for SCC2 use.
1021 #define PROFF_ENET PROFF_SCC2
1022 #define CPM_CR_ENET CPM_CR_CH_SCC2
1024 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1025 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1026 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1027 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1029 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1031 #define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */
1032 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1033 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1035 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1036 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1038 #define SICR_ENET_MASK ((uint)0x0000FF00)
1039 #define SICR_ENET_CLKRT ((uint)0x00002E00)
1040 #endif /* CONFIG_LANTEC v2 */
1042 /*** LWMON **********************************************************/
1044 #if defined(CONFIG_LWMON) && !defined(CONFIG_8xx_CONS_SCC2)
1045 /* Bits in parallel I/O port registers that have to be set/cleared
1046 * to configure the pins for SCC2 use.
1048 #define PROFF_ENET PROFF_SCC2
1049 #define CPM_CR_ENET CPM_CR_CH_SCC2
1051 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1052 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1053 #define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
1054 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1056 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1058 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1059 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1061 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
1062 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1064 #define SICR_ENET_MASK ((uint)0x0000ff00)
1065 #define SICR_ENET_CLKRT ((uint)0x00003E00)
1066 #endif /* CONFIG_LWMON */
1068 /*** NX823 ***********************************************/
1070 #if defined(CONFIG_NX823)
1071 /* Bits in parallel I/O port registers that have to be set/cleared
1072 * to configure the pins for SCC1 use.
1074 #define PROFF_ENET PROFF_SCC2
1075 #define CPM_CR_ENET CPM_CR_CH_SCC2
1077 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1078 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1079 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1080 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
1082 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1084 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1085 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1087 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1088 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1090 #define SICR_ENET_MASK ((uint)0x0000ff00)
1091 #define SICR_ENET_CLKRT ((uint)0x00002f00)
1093 #endif /* CONFIG_NX823 */
1095 /*** MBX ************************************************************/
1098 /* Bits in parallel I/O port registers that have to be set/cleared
1099 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
1100 * to the MBX860 board. Any two of the four available clocks could be
1101 * used, and the MPC860 cookbook manual has an example using different
1104 #define PROFF_ENET PROFF_SCC1
1105 #define CPM_CR_ENET CPM_CR_CH_SCC1
1107 #define PA_ENET_RXD ((ushort)0x0001)
1108 #define PA_ENET_TXD ((ushort)0x0002)
1109 #define PA_ENET_TCLK ((ushort)0x0200)
1110 #define PA_ENET_RCLK ((ushort)0x0800)
1111 #define PC_ENET_TENA ((ushort)0x0001)
1112 #define PC_ENET_CLSN ((ushort)0x0010)
1113 #define PC_ENET_RENA ((ushort)0x0020)
1115 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1116 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1118 #define SICR_ENET_MASK ((uint)0x000000ff)
1119 #define SICR_ENET_CLKRT ((uint)0x0000003d)
1120 #endif /* CONFIG_MBX */
1122 /*** MHPC ********************************************************/
1124 #if defined(CONFIG_MHPC)
1125 /* This ENET stuff is for the MHPC with ethernet on SCC2.
1126 * Note TENA is on Port B.
1128 #define PROFF_ENET PROFF_SCC2
1129 #define CPM_CR_ENET CPM_CR_CH_SCC2
1131 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1132 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1133 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1134 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1135 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1136 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1137 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1139 #define SICR_ENET_MASK ((uint)0x0000ff00)
1140 #define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
1141 #endif /* CONFIG_MHPC */
1143 /*** NETVIA *******************************************************/
1145 /* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
1146 #if ( defined CONFIG_SVM_SC8xx )
1147 # ifndef CONFIG_FEC_ENET
1149 #define PROFF_ENET PROFF_SCC2
1150 #define CPM_CR_ENET CPM_CR_CH_SCC2
1153 /* Bits in parallel I/O port registers that have to be set/cleared
1154 * * * * to configure the pins for SCC2 use.
1156 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1157 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1158 #define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
1159 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
1161 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1163 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1164 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1165 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1166 * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1168 #define SICR_ENET_MASK ((uint)0x0000ff00)
1169 #define SICR_ENET_CLKRT ((uint)0x00003700)
1171 # else /* Use FEC for Fast Ethernet */
1176 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
1177 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
1178 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
1179 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1180 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
1181 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
1182 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
1183 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
1184 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
1185 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
1186 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
1187 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
1188 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
1190 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
1192 # endif /* CONFIG_FEC_ENET */
1193 #endif /* CONFIG_SVM_SC8xx */
1196 #if defined(CONFIG_NETVIA)
1197 /* Bits in parallel I/O port registers that have to be set/cleared
1198 * to configure the pins for SCC2 use.
1200 #define PROFF_ENET PROFF_SCC2
1201 #define CPM_CR_ENET CPM_CR_CH_SCC2
1203 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1204 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1205 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1206 #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
1208 #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
1209 # define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
1210 #elif CONFIG_NETVIA_VERSION >= 2
1211 # define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
1214 #define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
1216 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1217 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1219 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1220 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1222 #define SICR_ENET_MASK ((uint)0x0000ff00)
1223 #define SICR_ENET_CLKRT ((uint)0x00002f00)
1225 #endif /* CONFIG_NETVIA */
1227 /*** QS850/QS823 ***************************************************/
1229 #if defined(CONFIG_QS850) || defined(CONFIG_QS823)
1230 #undef FEC_ENET /* Don't use FEC for EThernet */
1232 #define PROFF_ENET PROFF_SCC2
1233 #define CPM_CR_ENET CPM_CR_CH_SCC2
1236 #define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */
1237 #define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */
1238 #define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */
1239 #define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */
1240 #define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */
1241 #define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */
1242 #define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */
1243 #define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */
1244 #define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */
1245 #define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */
1247 /* SCC2 TXCLK from CLK2
1248 * SCC2 RXCLK from CLK4
1249 * SCC2 Connected to NMSI */
1250 #define SICR_ENET_MASK ((uint)0x00007F00)
1251 #define SICR_ENET_CLKRT ((uint)0x00003D00)
1253 #endif /* CONFIG_QS850/QS823 */
1255 /*** QS860T ***************************************************/
1257 #ifdef CONFIG_QS860T
1258 #ifdef CONFIG_FEC_ENET
1259 #define FEC_ENET /* use FEC for EThernet */
1260 #endif /* CONFIG_FEC_ETHERNET */
1262 /* This ENET stuff is for GTH 10 Mbit ( SCC ) */
1263 #define PROFF_ENET PROFF_SCC1
1264 #define CPM_CR_ENET CPM_CR_CH_SCC1
1267 #define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
1268 #define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
1269 #define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
1270 #define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */
1271 #define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
1272 #define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
1273 #define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
1275 #define SICR_ENET_MASK ((uint)0x000000ff)
1276 /* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
1277 #define SICR_ENET_CLKRT ((uint)0x0000003D)
1279 #endif /* CONFIG_QS860T */
1281 /*** RPXCLASSIC *****************************************************/
1283 #ifdef CONFIG_RPXCLASSIC
1285 #ifdef CONFIG_FEC_ENET
1287 # define FEC_ENET /* use FEC for EThernet */
1290 #else /* ! CONFIG_FEC_ENET */
1292 /* Bits in parallel I/O port registers that have to be set/cleared
1293 * to configure the pins for SCC1 use.
1295 #define PROFF_ENET PROFF_SCC1
1296 #define CPM_CR_ENET CPM_CR_CH_SCC1
1298 #define PA_ENET_RXD ((ushort)0x0001)
1299 #define PA_ENET_TXD ((ushort)0x0002)
1300 #define PA_ENET_TCLK ((ushort)0x0200)
1301 #define PA_ENET_RCLK ((ushort)0x0800)
1302 #define PB_ENET_TENA ((uint)0x00001000)
1303 #define PC_ENET_CLSN ((ushort)0x0010)
1304 #define PC_ENET_RENA ((ushort)0x0020)
1306 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1307 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1309 #define SICR_ENET_MASK ((uint)0x000000ff)
1310 #define SICR_ENET_CLKRT ((uint)0x0000003d)
1312 #endif /* CONFIG_FEC_ENET */
1314 #endif /* CONFIG_RPXCLASSIC */
1316 /*** RPXLITE ********************************************************/
1318 #ifdef CONFIG_RPXLITE
1319 /* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
1320 * this may be unique to the RPX-Lite configuration.
1321 * Note TENA is on Port B.
1323 #define PROFF_ENET PROFF_SCC2
1324 #define CPM_CR_ENET CPM_CR_CH_SCC2
1326 #define PA_ENET_RXD ((ushort)0x0004)
1327 #define PA_ENET_TXD ((ushort)0x0008)
1328 #define PA_ENET_TCLK ((ushort)0x0200)
1329 #define PA_ENET_RCLK ((ushort)0x0800)
1330 #if defined(CONFIG_RMU)
1331 #define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
1333 #define PB_ENET_TENA ((uint)0x00002000)
1335 #define PC_ENET_CLSN ((ushort)0x0040)
1336 #define PC_ENET_RENA ((ushort)0x0080)
1338 #define SICR_ENET_MASK ((uint)0x0000ff00)
1339 #define SICR_ENET_CLKRT ((uint)0x00003d00)
1340 #endif /* CONFIG_RPXLITE */
1342 /*** SM850 *********************************************************/
1344 /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
1347 #define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
1348 #define CPM_CR_ENET CPM_CR_CH_SCC3
1350 #define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
1351 #define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
1352 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1353 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1355 #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1356 #define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
1358 #define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
1359 #define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
1361 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1362 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
1364 #define SICR_ENET_MASK ((uint)0x00FF0000)
1365 #define SICR_ENET_CLKRT ((uint)0x00260000)
1366 #endif /* CONFIG_SM850 */
1368 /*** SPD823TS ******************************************************/
1370 #ifdef CONFIG_SPD823TS
1371 /* Bits in parallel I/O port registers that have to be set/cleared
1372 * to configure the pins for SCC2 use.
1374 #define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
1375 #define CPM_CR_ENET CPM_CR_CH_SCC2
1377 #define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
1378 #define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
1379 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1380 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1381 #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1382 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1384 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1386 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1387 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1388 #define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
1390 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1391 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1393 #define SICR_ENET_MASK ((uint)0x0000ff00)
1394 #define SICR_ENET_CLKRT ((uint)0x00002E00)
1395 #endif /* CONFIG_SPD823TS */
1397 /*** SXNI855T ******************************************************/
1399 #if defined(CONFIG_SXNI855T)
1401 #ifdef CONFIG_FEC_ENET
1402 #define FEC_ENET /* use FEC for Ethernet */
1403 #endif /* CONFIG_FEC_ETHERNET */
1405 #endif /* CONFIG_SXNI855T */
1407 /*** MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI *******************/
1409 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
1410 defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
1411 defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
1412 defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
1413 defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \
1414 (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
1415 /* Bits in parallel I/O port registers that have to be set/cleared
1416 * to configure the pins for SCC2 use.
1418 #define PROFF_ENET PROFF_SCC2
1419 #define CPM_CR_ENET CPM_CR_CH_SCC2
1421 #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1422 #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1423 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1424 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1426 #define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1428 #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1429 #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1430 #if defined(CONFIG_R360MPI)
1431 #define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
1432 #endif /* CONFIG_R360MPI */
1434 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1435 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1437 #define SICR_ENET_MASK ((uint)0x0000ff00)
1438 #define SICR_ENET_CLKRT ((uint)0x00002600)
1439 #endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
1441 /*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
1443 #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
1444 defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
1445 defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
1446 defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
1448 # ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
1450 /* Bits in parallel I/O port registers that have to be set/cleared
1451 * to configure the pins for SCC1 use.
1453 #define PROFF_ENET PROFF_SCC1
1454 #define CPM_CR_ENET CPM_CR_CH_SCC1
1456 #define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
1457 #define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
1458 #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
1459 #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
1461 #define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
1462 #define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
1463 #define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
1465 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1466 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1468 #define SICR_ENET_MASK ((uint)0x000000ff)
1469 #define SICR_ENET_CLKRT ((uint)0x00000026)
1471 # endif /* CONFIG_SCC1_ENET */
1473 # ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
1477 #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
1478 #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
1479 #define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
1480 #define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
1481 #define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
1482 #define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
1483 #define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
1484 #define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
1485 #define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
1486 #define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
1487 #define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
1488 #define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
1489 #define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
1491 #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
1493 # endif /* CONFIG_FEC_ENET */
1494 #endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
1496 /*** V37 **********************************************************/
1499 /* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
1500 * this may be unique to the Marel V37 configuration.
1501 * Note TENA is on Port B.
1503 #define PROFF_ENET PROFF_SCC2
1504 #define CPM_CR_ENET CPM_CR_CH_SCC2
1506 #define PA_ENET_RXD ((ushort)0x0004)
1507 #define PA_ENET_TXD ((ushort)0x0008)
1508 #define PA_ENET_TCLK ((ushort)0x0400)
1509 #define PA_ENET_RCLK ((ushort)0x0200)
1510 #define PB_ENET_TENA ((uint)0x00002000)
1511 #define PC_ENET_CLSN ((ushort)0x0040)
1512 #define PC_ENET_RENA ((ushort)0x0080)
1514 #define SICR_ENET_MASK ((uint)0x0000ff00)
1515 #define SICR_ENET_CLKRT ((uint)0x00002e00)
1516 #endif /* CONFIG_V37 */
1519 /*********************************************************************/
1521 /* SCC Event register as used by Ethernet.
1523 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
1524 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
1525 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
1526 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
1527 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
1528 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
1530 /* SCC Mode Register (PSMR) as used by Ethernet.
1532 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
1533 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
1534 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
1535 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
1536 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
1537 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
1538 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
1539 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
1540 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
1541 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
1542 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
1543 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
1544 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
1546 /* Buffer descriptor control/status used by Ethernet receive.
1548 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
1549 #define BD_ENET_RX_WRAP ((ushort)0x2000)
1550 #define BD_ENET_RX_INTR ((ushort)0x1000)
1551 #define BD_ENET_RX_LAST ((ushort)0x0800)
1552 #define BD_ENET_RX_FIRST ((ushort)0x0400)
1553 #define BD_ENET_RX_MISS ((ushort)0x0100)
1554 #define BD_ENET_RX_LG ((ushort)0x0020)
1555 #define BD_ENET_RX_NO ((ushort)0x0010)
1556 #define BD_ENET_RX_SH ((ushort)0x0008)
1557 #define BD_ENET_RX_CR ((ushort)0x0004)
1558 #define BD_ENET_RX_OV ((ushort)0x0002)
1559 #define BD_ENET_RX_CL ((ushort)0x0001)
1560 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
1562 /* Buffer descriptor control/status used by Ethernet transmit.
1564 #define BD_ENET_TX_READY ((ushort)0x8000)
1565 #define BD_ENET_TX_PAD ((ushort)0x4000)
1566 #define BD_ENET_TX_WRAP ((ushort)0x2000)
1567 #define BD_ENET_TX_INTR ((ushort)0x1000)
1568 #define BD_ENET_TX_LAST ((ushort)0x0800)
1569 #define BD_ENET_TX_TC ((ushort)0x0400)
1570 #define BD_ENET_TX_DEF ((ushort)0x0200)
1571 #define BD_ENET_TX_HB ((ushort)0x0100)
1572 #define BD_ENET_TX_LC ((ushort)0x0080)
1573 #define BD_ENET_TX_RL ((ushort)0x0040)
1574 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
1575 #define BD_ENET_TX_UN ((ushort)0x0002)
1576 #define BD_ENET_TX_CSL ((ushort)0x0001)
1577 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
1581 typedef struct scc_uart {
1583 uint scc_res1; /* Reserved */
1584 uint scc_res2; /* Reserved */
1585 ushort scc_maxidl; /* Maximum idle chars */
1586 ushort scc_idlc; /* temp idle counter */
1587 ushort scc_brkcr; /* Break count register */
1588 ushort scc_parec; /* receive parity error counter */
1589 ushort scc_frmec; /* receive framing error counter */
1590 ushort scc_nosec; /* receive noise counter */
1591 ushort scc_brkec; /* receive break condition counter */
1592 ushort scc_brkln; /* last received break length */
1593 ushort scc_uaddr1; /* UART address character 1 */
1594 ushort scc_uaddr2; /* UART address character 2 */
1595 ushort scc_rtemp; /* Temp storage */
1596 ushort scc_toseq; /* Transmit out of sequence char */
1597 ushort scc_char1; /* control character 1 */
1598 ushort scc_char2; /* control character 2 */
1599 ushort scc_char3; /* control character 3 */
1600 ushort scc_char4; /* control character 4 */
1601 ushort scc_char5; /* control character 5 */
1602 ushort scc_char6; /* control character 6 */
1603 ushort scc_char7; /* control character 7 */
1604 ushort scc_char8; /* control character 8 */
1605 ushort scc_rccm; /* receive control character mask */
1606 ushort scc_rccr; /* receive control character register */
1607 ushort scc_rlbc; /* receive last break character */
1610 /* SCC Event and Mask registers when it is used as a UART.
1612 #define UART_SCCM_GLR ((ushort)0x1000)
1613 #define UART_SCCM_GLT ((ushort)0x0800)
1614 #define UART_SCCM_AB ((ushort)0x0200)
1615 #define UART_SCCM_IDL ((ushort)0x0100)
1616 #define UART_SCCM_GRA ((ushort)0x0080)
1617 #define UART_SCCM_BRKE ((ushort)0x0040)
1618 #define UART_SCCM_BRKS ((ushort)0x0020)
1619 #define UART_SCCM_CCR ((ushort)0x0008)
1620 #define UART_SCCM_BSY ((ushort)0x0004)
1621 #define UART_SCCM_TX ((ushort)0x0002)
1622 #define UART_SCCM_RX ((ushort)0x0001)
1624 /* The SCC PSMR when used as a UART.
1626 #define SCU_PSMR_FLC ((ushort)0x8000)
1627 #define SCU_PSMR_SL ((ushort)0x4000)
1628 #define SCU_PSMR_CL ((ushort)0x3000)
1629 #define SCU_PSMR_UM ((ushort)0x0c00)
1630 #define SCU_PSMR_FRZ ((ushort)0x0200)
1631 #define SCU_PSMR_RZS ((ushort)0x0100)
1632 #define SCU_PSMR_SYN ((ushort)0x0080)
1633 #define SCU_PSMR_DRT ((ushort)0x0040)
1634 #define SCU_PSMR_PEN ((ushort)0x0010)
1635 #define SCU_PSMR_RPM ((ushort)0x000c)
1636 #define SCU_PSMR_REVP ((ushort)0x0008)
1637 #define SCU_PSMR_TPM ((ushort)0x0003)
1638 #define SCU_PSMR_TEVP ((ushort)0x0003)
1640 /* CPM Transparent mode SCC.
1642 typedef struct scc_trans {
1644 uint st_cpres; /* Preset CRC */
1645 uint st_cmask; /* Constant mask for CRC */
1648 #define BD_SCC_TX_LAST ((ushort)0x0800)
1650 /* IIC parameter RAM.
1652 typedef struct iic {
1653 ushort iic_rbase; /* Rx Buffer descriptor base address */
1654 ushort iic_tbase; /* Tx Buffer descriptor base address */
1655 u_char iic_rfcr; /* Rx function code */
1656 u_char iic_tfcr; /* Tx function code */
1657 ushort iic_mrblr; /* Max receive buffer length */
1658 uint iic_rstate; /* Internal */
1659 uint iic_rdp; /* Internal */
1660 ushort iic_rbptr; /* Internal */
1661 ushort iic_rbc; /* Internal */
1662 uint iic_rxtmp; /* Internal */
1663 uint iic_tstate; /* Internal */
1664 uint iic_tdp; /* Internal */
1665 ushort iic_tbptr; /* Internal */
1666 ushort iic_tbc; /* Internal */
1667 uint iic_txtmp; /* Internal */
1668 uint iic_res; /* reserved */
1669 ushort iic_rpbase; /* Relocation pointer */
1670 ushort iic_res2; /* reserved */
1673 /* SPI parameter RAM.
1675 typedef struct spi {
1676 ushort spi_rbase; /* Rx Buffer descriptor base address */
1677 ushort spi_tbase; /* Tx Buffer descriptor base address */
1678 u_char spi_rfcr; /* Rx function code */
1679 u_char spi_tfcr; /* Tx function code */
1680 ushort spi_mrblr; /* Max receive buffer length */
1681 uint spi_rstate; /* Internal */
1682 uint spi_rdp; /* Internal */
1683 ushort spi_rbptr; /* Internal */
1684 ushort spi_rbc; /* Internal */
1685 uint spi_rxtmp; /* Internal */
1686 uint spi_tstate; /* Internal */
1687 uint spi_tdp; /* Internal */
1688 ushort spi_tbptr; /* Internal */
1689 ushort spi_tbc; /* Internal */
1690 uint spi_txtmp; /* Internal */
1692 ushort spi_rpbase; /* Relocation pointer */
1696 /* SPI Mode register.
1698 #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
1699 #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
1700 #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
1701 #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
1702 #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
1703 #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
1704 #define SPMODE_EN ((ushort)0x0100) /* Enable */
1705 #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
1706 #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
1708 #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
1709 #define SPMODE_PM(x) ((x) &0xF)
1711 /* HDLC parameter RAM.
1714 typedef struct hdlc_pram_s {
1718 ushort rbase; /* Rx Buffer descriptor base address */
1719 ushort tbase; /* Tx Buffer descriptor base address */
1720 uchar rfcr; /* Rx function code */
1721 uchar tfcr; /* Tx function code */
1722 ushort mrblr; /* Rx buffer length */
1723 ulong rstate; /* Rx internal state */
1724 ulong rptr; /* Rx internal data pointer */
1725 ushort rbptr; /* rb BD Pointer */
1726 ushort rcount; /* Rx internal byte count */
1727 ulong rtemp; /* Rx temp */
1728 ulong tstate; /* Tx internal state */
1729 ulong tptr; /* Tx internal data pointer */
1730 ushort tbptr; /* Tx BD pointer */
1731 ushort tcount; /* Tx byte count */
1732 ulong ttemp; /* Tx temp */
1733 ulong rcrc; /* temp receive CRC */
1734 ulong tcrc; /* temp transmit CRC */
1736 * HDLC specific parameter RAM
1738 uchar res[4]; /* reserved */
1739 ulong c_mask; /* CRC constant */
1740 ulong c_pres; /* CRC preset */
1741 ushort disfc; /* discarded frame counter */
1742 ushort crcec; /* CRC error counter */
1743 ushort abtsc; /* abort sequence counter */
1744 ushort nmarc; /* nonmatching address rx cnt */
1745 ushort retrc; /* frame retransmission cnt */
1746 ushort mflr; /* maximum frame length reg */
1747 ushort max_cnt; /* maximum length counter */
1748 ushort rfthr; /* received frames threshold */
1749 ushort rfcnt; /* received frames count */
1750 ushort hmask; /* user defined frm addr mask */
1751 ushort haddr1; /* user defined frm address 1 */
1752 ushort haddr2; /* user defined frm address 2 */
1753 ushort haddr3; /* user defined frm address 3 */
1754 ushort haddr4; /* user defined frm address 4 */
1755 ushort tmp; /* temp */
1756 ushort tmp_mb; /* temp */
1759 /* CPM interrupts. There are nearly 32 interrupts generated by CPM
1760 * channels or devices. All of these are presented to the PPC core
1761 * as a single interrupt. The CPM interrupt handler dispatches its
1762 * own handlers, in a similar fashion to the PPC core handler. We
1763 * use the table as defined in the manuals (i.e. no special high
1764 * priority and SCC1 == SCCa, etc...).
1766 #define CPMVEC_NR 32
1767 #define CPMVEC_OFFSET 0x00010000
1768 #define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
1769 #define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
1770 #define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
1771 #define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
1772 #define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
1773 #define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
1774 #define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
1775 #define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
1776 #define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
1777 #define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
1778 #define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
1779 #define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
1780 #define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
1781 #define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
1782 #define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
1783 #define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
1784 #define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
1785 #define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
1786 #define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
1787 #define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
1788 #define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
1789 #define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
1790 #define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
1791 #define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
1792 #define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
1793 #define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
1794 #define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
1795 #define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
1796 #define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
1798 extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1800 /* CPM interrupt configuration vector.
1802 #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
1803 #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
1804 #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
1805 #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
1806 #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
1807 #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
1808 #define CICR_IEN ((uint)0x00000080) /* Int. enable */
1809 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */
1810 #endif /* __CPM_8XX__ */