1 #ifndef _ASM_CPU_SH7750_H_
2 #define _ASM_CPU_SH7750_H_
4 #define PTEH 0xFF000000
5 #define PTEL 0xFF000004
8 #define MMUCR 0xFF000010
9 #define BASRA 0xFF000014
10 #define BASRB 0xFF000018
11 #define CCR 0xFF00001C
12 #define TRA 0xFF000020
13 #define EXPEVT 0xFF000024
14 #define INTEVT 0xFF000028
15 #define PTEA 0xFF000034
16 #define QACR0 0xFF000038
17 #define QACR1 0xFF00003C
18 #define BARA 0xFF200000
19 #define BAMRA 0xFF200004
20 #define BBRA 0xFF200008
21 #define BARB 0xFF20000C
22 #define BAMRB 0xFF200010
23 #define BBRB 0xFF200014
24 #define BDRB 0xFF200018
25 #define BDMRB 0xFF20001C
26 #define BRCR 0xFF200020
28 #define BCR1 0xFF800000
29 #define BCR2 0xFF800004
30 #define BCR3 0xFF800050
31 #define BCR4 0xFE0A00F0
32 #define WCR1 0xFF800008
33 #define WCR2 0xFF80000C
34 #define WCR3 0xFF800010
35 #define MCR 0xFF800014
36 #define PCR 0xFF800018
37 #define RTCSR 0xFF80001C
38 #define RTCNT 0xFF800020
39 #define RTCOR 0xFF800024
40 #define RFCR 0xFF800028
41 #define PCTRA 0xFF80002C
42 #define PDTRA 0xFF800030
43 #define PCTRB 0xFF800040
44 #define PDTRB 0xFF800044
45 #define GPIOIC 0xFF800048
46 #define SAR0 0xFFA00000
47 #define DAR0 0xFFA00004
48 #define DMATCR0 0xFFA00008
49 #define CHCR0 0xFFA0000C
50 #define SAR1 0xFFA00010
51 #define DAR1 0xFFA00014
52 #define DMATCR1 0xFFA00018
53 #define CHCR1 0xFFA0001C
54 #define SAR2 0xFFA00020
55 #define DAR2 0xFFA00024
56 #define DMATCR2 0xFFA00028
57 #define CHCR2 0xFFA0002C
58 #define SAR3 0xFFA00030
59 #define DAR3 0xFFA00034
60 #define DMATCR3 0xFFA00038
61 #define CHCR3 0xFFA0003C
62 #define DMAOR 0xFFA00040
63 #define SAR4 0xFFA00050
64 #define DAR4 0xFFA00054
65 #define DMATCR4 0xFFA00058
67 #define FRQCR 0xFFC00000
68 #define STBCR 0xFFC00004
69 #define WTCNT 0xFFC00008
70 #define WTCSR 0xFFC0000C
71 #define STBCR2 0xFFC00010
72 #define R64CNT 0xFFC80000
73 #define RSECCNT 0xFFC80004
74 #define RMINCNT 0xFFC80008
75 #define RHRCNT 0xFFC8000C
76 #define RWKCNT 0xFFC80010
77 #define RDAYCNT 0xFFC80014
78 #define RMONCNT 0xFFC80018
79 #define RYRCNT 0xFFC8001C
80 #define RSECAR 0xFFC80020
81 #define RMINAR 0xFFC80024
82 #define RHRAR 0xFFC80028
83 #define RWKAR 0xFFC8002C
84 #define RDAYAR 0xFFC80030
85 #define RMONAR 0xFFC80034
86 #define RCR1 0xFFC80038
87 #define RCR2 0xFFC8003C
88 #define RCR3 0xFFC80050
89 #define RYRAR 0xFFC80054
90 #define ICR 0xFFD00000
91 #define IPRA 0xFFD00004
92 #define IPRB 0xFFD00008
93 #define IPRC 0xFFD0000C
94 #define IPRD 0xFFD00010
95 #define INTPRI 0xFE080000
96 #define INTREQ 0xFE080020
97 #define INTMSK 0xFE080040
98 #define INTMSKCL 0xFE080060
99 #define CLKSTP 0xFE0A0000
100 #define CLKSTPCLR 0xFE0A0008
101 #define TSTR2 0xFE100004
102 #define TCOR3 0xFE100008
103 #define TCNT3 0xFE10000C
104 #define TCR3 0xFE100010
105 #define TCOR4 0xFE100014
106 #define TCNT4 0xFE100018
107 #define TCR4 0xFE10001C
108 #define TOCR 0xFFD80000
109 #define TSTR0 0xFFD80004
110 #define TCOR0 0xFFD80008
111 #define TCNT0 0xFFD8000C
112 #define TCR0 0xFFD80010
113 #define TCOR1 0xFFD80014
114 #define TCNT1 0xFFD80018
115 #define TCR1 0xFFD8001C
116 #define TCOR2 0xFFD80020
117 #define TCNT2 0xFFD80024
118 #define TCR2 0xFFD80028
119 #define TCPR2 0xFFD8002C
120 #define SCSMR1 0xFFE00000
121 #define SCBRR1 0xFFE00004
122 #define SCSCR1 0xFFE00008
123 #define SCTDR1 0xFFE0000C
124 #define SCSSR1 0xFFE00010
125 #define SCRDR1 0xFFE00014
126 #define SCSCMR1 0xFFE00018
127 #define SCSPTR1 0xFFE0001C
128 #define SCF0_BASE SCSMR1
129 #define SCSMR2 0xFFE80000
130 #define SCBRR2 0xFFE80004
131 #define SCSCR2 0xFFE80008
132 #define SCFTDR2 0xFFE8000C
133 #define SCFSR2 0xFFE80010
134 #define SCFRDR2 0xFFE80014
135 #define SCFCR2 0xFFE80018
136 #define SCFDR2 0xFFE8001C
137 #define SCSPTR2 0xFFE80020
138 #define SCLSR2 0xFFE80024
139 #define SCIF1_BASE SCSMR2
140 #define SDIR 0xFFF00000
141 #define SDDR 0xFFF00008
142 #define SDINT 0xFFF00014
144 #endif /* _ASM_CPU_SH7750_H_ */