2 * MPC85xx Internal Memory Map
4 * Copyright(c) 2002,2003 Motorola Inc.
5 * Xianghua Xiao (x.xiao@motorola.com)
10 #define __IMMAP_85xx__
13 /* Local-Access Registers and ECM Registers(0x0000-0x2000) */
15 typedef struct ccsr_local_ecm {
16 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
18 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
20 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
22 uint bptr; /* 0x20 - Boot Page Translation Register */
24 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
26 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
28 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
30 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
32 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
34 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
36 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
38 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
40 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
42 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
44 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
46 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
48 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
50 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
52 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
54 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
56 uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
58 uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
60 uint eedr; /* 0x1e00 - ECM Error Detect Register */
62 uint eeer; /* 0x1e08 - ECM Error Enable Register */
63 uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */
64 uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */
69 /* DDR memory controller registers(0x2000-0x3000) */
71 typedef struct ccsr_ddr {
72 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
74 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
76 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
78 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
80 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
81 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
82 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
83 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
85 uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */
86 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
87 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
88 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
89 uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
90 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
91 uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
92 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/
93 uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */
94 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
95 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */
97 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
99 uint init_address; /* 0x2148 - DDR training initialization address */
100 uint init_ext_address; /* 0x214C - DDR training initialization extended address */
102 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
103 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
105 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
106 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
107 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
109 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
110 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
111 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
113 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
114 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
115 uint err_int_en; /* 0x2e48 - DDR */
116 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
117 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
118 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
119 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
121 uint debug_1; /* 0x2f00 */
131 /* I2C Registers(0x3000-0x4000) */
133 typedef struct ccsr_i2c {
134 u_char i2cadr; /* 0x3000 - I2C Address Register */
135 #define MPC85xx_I2CADR_MASK 0xFE
137 u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */
138 #define MPC85xx_I2CFDR_MASK 0x3F
140 u_char i2ccr; /* 0x3008 - I2C Control Register */
141 #define MPC85xx_I2CCR_MEN 0x80
142 #define MPC85xx_I2CCR_MIEN 0x40
143 #define MPC85xx_I2CCR_MSTA 0x20
144 #define MPC85xx_I2CCR_MTX 0x10
145 #define MPC85xx_I2CCR_TXAK 0x08
146 #define MPC85xx_I2CCR_RSTA 0x04
147 #define MPC85xx_I2CCR_BCST 0x01
149 u_char i2csr; /* 0x300c - I2C Status Register */
150 #define MPC85xx_I2CSR_MCF 0x80
151 #define MPC85xx_I2CSR_MAAS 0x40
152 #define MPC85xx_I2CSR_MBB 0x20
153 #define MPC85xx_I2CSR_MAL 0x10
154 #define MPC85xx_I2CSR_BCSTM 0x08
155 #define MPC85xx_I2CSR_SRW 0x04
156 #define MPC85xx_I2CSR_MIF 0x02
157 #define MPC85xx_I2CSR_RXAK 0x01
159 u_char i2cdr; /* 0x3010 - I2C Data Register */
160 #define MPC85xx_I2CDR_DATA 0xFF
162 u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */
163 #define MPC85xx_I2CDFSRR 0x3F
167 #if defined(CONFIG_MPC8540) \
168 || defined(CONFIG_MPC8541) \
169 || defined(CONFIG_MPC8548) \
170 || defined(CONFIG_MPC8555)
171 /* DUART Registers(0x4000-0x5000) */
172 typedef struct ccsr_duart {
174 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
175 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
176 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
177 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
178 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
179 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
180 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
181 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
183 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
185 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
186 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
187 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
188 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
189 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
190 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
191 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
192 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
194 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
197 #else /* MPC8560 uses UART on its CPM */
198 typedef struct ccsr_duart {
203 /* Local Bus Controller Registers(0x5000-0x6000) */
204 /* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
206 typedef struct ccsr_lbc {
207 uint br0; /* 0x5000 - LBC Base Register 0 */
208 uint or0; /* 0x5004 - LBC Options Register 0 */
209 uint br1; /* 0x5008 - LBC Base Register 1 */
210 uint or1; /* 0x500c - LBC Options Register 1 */
211 uint br2; /* 0x5010 - LBC Base Register 2 */
212 uint or2; /* 0x5014 - LBC Options Register 2 */
213 uint br3; /* 0x5018 - LBC Base Register 3 */
214 uint or3; /* 0x501c - LBC Options Register 3 */
215 uint br4; /* 0x5020 - LBC Base Register 4 */
216 uint or4; /* 0x5024 - LBC Options Register 4 */
217 uint br5; /* 0x5028 - LBC Base Register 5 */
218 uint or5; /* 0x502c - LBC Options Register 5 */
219 uint br6; /* 0x5030 - LBC Base Register 6 */
220 uint or6; /* 0x5034 - LBC Options Register 6 */
221 uint br7; /* 0x5038 - LBC Base Register 7 */
222 uint or7; /* 0x503c - LBC Options Register 7 */
224 uint mar; /* 0x5068 - LBC UPM Address Register */
226 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
227 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
228 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
230 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
231 uint mdr; /* 0x5088 - LBC UPM Data Register */
233 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
235 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
236 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
238 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
239 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
240 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
241 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
242 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
244 uint lbcr; /* 0x50d0 - LBC Configuration Register */
245 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
250 /* PCI Registers(0x8000-0x9000) */
251 /* Omitting Reserved(0x9000-0x2_0000) */
253 typedef struct ccsr_pcix {
254 uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
255 uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
256 uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */
258 uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
259 uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
260 uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
261 uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
262 uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
264 uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
265 uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
266 uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
267 uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
268 uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
270 uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
271 uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
272 uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
273 uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
274 uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
276 uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
277 uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
278 uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
279 uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
280 uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
282 uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
283 uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
284 uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
285 uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
286 uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
288 uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */
289 uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
290 uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
291 uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
292 uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
294 uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */
295 uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
296 uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
297 uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
298 uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
300 uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */
301 uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
302 uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
304 uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
306 uint pedr; /* 0x8e00 - PCIX Error Detect Register */
307 uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */
308 uint peer; /* 0x8e08 - PCIX Error Enable Register */
309 uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */
310 uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */
311 uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
312 uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
313 uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
318 /* L2 Cache Registers(0x2_0000-0x2_1000) */
320 typedef struct ccsr_l2cache {
321 uint l2ctl; /* 0x20000 - L2 configuration register 0 */
323 uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */
325 uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */
327 uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */
329 uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */
331 uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */
333 uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */
335 uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */
337 uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */
339 uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */
341 uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */
343 uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */
344 uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */
345 uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */
347 uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */
348 uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */
349 uint l2captecc; /* 0x20e28 - L2 error ECC capture register */
351 uint l2errdet; /* 0x20e40 - L2 error detect register */
352 uint l2errdis; /* 0x20e44 - L2 error disable register */
353 uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */
354 uint l2errattr; /* 0x20e4c - L2 error attributes capture register */
355 uint l2erraddr; /* 0x20e50 - L2 error address capture register */
357 uint l2errctl; /* 0x20e58 - L2 error control register */
362 /* DMA Registers(0x2_1000-0x2_2000) */
364 typedef struct ccsr_dma {
366 uint mr0; /* 0x21100 - DMA 0 Mode Register */
367 uint sr0; /* 0x21104 - DMA 0 Status Register */
369 uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
370 uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
371 uint sar0; /* 0x21114 - DMA 0 Source Address Register */
372 uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
373 uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
374 uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
376 uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
378 uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
380 uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
381 uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
382 uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
384 uint mr1; /* 0x21180 - DMA 1 Mode Register */
385 uint sr1; /* 0x21184 - DMA 1 Status Register */
387 uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
388 uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
389 uint sar1; /* 0x21194 - DMA 1 Source Address Register */
390 uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
391 uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
392 uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
394 uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
396 uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
398 uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
399 uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
400 uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
402 uint mr2; /* 0x21200 - DMA 2 Mode Register */
403 uint sr2; /* 0x21204 - DMA 2 Status Register */
405 uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
406 uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
407 uint sar2; /* 0x21214 - DMA 2 Source Address Register */
408 uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
409 uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
410 uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
412 uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
414 uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
416 uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
417 uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
418 uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
420 uint mr3; /* 0x21280 - DMA 3 Mode Register */
421 uint sr3; /* 0x21284 - DMA 3 Status Register */
423 uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
424 uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
425 uint sar3; /* 0x21294 - DMA 3 Source Address Register */
426 uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
427 uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
428 uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
430 uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
432 uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
434 uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
435 uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
436 uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
438 uint dgsr; /* 0x21300 - DMA General Status Register */
442 /* tsec1 tsec2: 24000-26000 */
443 typedef struct ccsr_tsec {
445 uint ievent; /* 0x24010 - Interrupt Event Register */
446 uint imask; /* 0x24014 - Interrupt Mask Register */
447 uint edis; /* 0x24018 - Error Disabled Register */
449 uint ecntrl; /* 0x24020 - Ethernet Control Register */
450 uint minflr; /* 0x24024 - Minimum Frame Length Register */
451 uint ptv; /* 0x24028 - Pause Time Value Register */
452 uint dmactrl; /* 0x2402c - DMA Control Register */
453 uint tbipa; /* 0x24030 - TBI PHY Address Register */
455 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
457 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
458 uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
460 uint tctrl; /* 0x24100 - Transmit Control Register */
461 uint tstat; /* 0x24104 - Transmit Status Register */
463 uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
465 uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
466 uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
468 uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
469 uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
471 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
472 uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
474 uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
475 uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
476 uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
477 uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
478 uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
479 uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
480 uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
482 uint rctrl; /* 0x24300 - Receive Control Register */
483 uint rstat; /* 0x24304 - Receive Status Register */
485 uint rbdlen; /* 0x2430c - RxBD Data Length Register */
487 uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
488 uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
490 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
491 uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
493 uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
494 uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
495 uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
496 uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
497 uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
498 uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
499 uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
500 uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
502 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
503 uint rbase; /* 0x24404 - Receive Descriptor Base Address */
504 uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
505 uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
506 uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
507 uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
508 uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
509 uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
511 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
512 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
513 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
514 uint hafdup; /* 0x2450c - Half Duplex Register */
515 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
517 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
518 uint miimcom; /* 0x24524 - MII Management Command Register */
519 uint miimadd; /* 0x24528 - MII Management Address Register */
520 uint miimcon; /* 0x2452c - MII Management Control Register */
521 uint miimstat; /* 0x24530 - MII Management Status Register */
522 uint miimind; /* 0x24534 - MII Management Indicator Register */
524 uint ifstat; /* 0x2453c - Interface Status Register */
525 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
526 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
528 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
529 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
530 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
531 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
532 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
533 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
534 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
535 uint rbyt; /* 0x2469c - Receive Byte Counter */
536 uint rpkt; /* 0x246a0 - Receive Packet Counter */
537 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
538 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
539 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
540 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
541 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
542 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
543 uint raln; /* 0x246bc - Receive Alignment Error Counter */
544 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
545 uint rcde; /* 0x246c4 - Receive Code Error Counter */
546 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
547 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
548 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
549 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
550 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
551 uint rdrp; /* 0x246dc - Receive Drop Counter */
552 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
553 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
554 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
555 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
556 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
557 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
558 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
559 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
560 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
561 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
562 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
563 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
565 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
566 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
567 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
568 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
569 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
570 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
571 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
572 uint car1; /* 0x24730 - Carry Register One */
573 uint car2; /* 0x24734 - Carry Register Two */
574 uint cam1; /* 0x24738 - Carry Mask Register One */
575 uint cam2; /* 0x2473c - Carry Mask Register Two */
577 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
578 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
579 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
580 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
581 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
582 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
583 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
584 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
586 uint gaddr0; /* 0x24880 - Global address register 0 */
587 uint gaddr1; /* 0x24884 - Global address register 1 */
588 uint gaddr2; /* 0x24888 - Global address register 2 */
589 uint gaddr3; /* 0x2488c - Global address register 3 */
590 uint gaddr4; /* 0x24890 - Global address register 4 */
591 uint gaddr5; /* 0x24894 - Global address register 5 */
592 uint gaddr6; /* 0x24898 - Global address register 6 */
593 uint gaddr7; /* 0x2489c - Global address register 7 */
595 uint pmd0; /* 0x24900 - Pattern Match Data Register */
597 uint pmask0; /* 0x24908 - Pattern Mask Register */
599 uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
601 uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
602 uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
603 uint pmd1; /* 0x24920 - Pattern Match Data Register */
605 uint pmask1; /* 0x24928 - Pattern Mask Register */
607 uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
609 uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
610 uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
611 uint pmd2; /* 0x24940 - Pattern Match Data Register */
613 uint pmask2; /* 0x24948 - Pattern Mask Register */
615 uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
617 uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
618 uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
619 uint pmd3; /* 0x24960 - Pattern Match Data Register */
621 uint pmask3; /* 0x24968 - Pattern Mask Register */
623 uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
625 uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
626 uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
627 uint pmd4; /* 0x24980 - Pattern Match Data Register */
629 uint pmask4; /* 0x24988 - Pattern Mask Register */
631 uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
633 uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
634 uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
635 uint pmd5; /* 0x249a0 - Pattern Match Data Register */
637 uint pmask5; /* 0x249a8 - Pattern Mask Register */
639 uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
641 uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
642 uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
643 uint pmd6; /* 0x249c0 - Pattern Match Data Register */
645 uint pmask6; /* 0x249c8 - Pattern Mask Register */
647 uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
649 uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
650 uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
651 uint pmd7; /* 0x249e0 - Pattern Match Data Register */
653 uint pmask7; /* 0x249e8 - Pattern Mask Register */
655 uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
657 uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
658 uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
659 uint pmd8; /* 0x24a00 - Pattern Match Data Register */
661 uint pmask8; /* 0x24a08 - Pattern Mask Register */
663 uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
665 uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
666 uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
667 uint pmd9; /* 0x24a20 - Pattern Match Data Register */
669 uint pmask9; /* 0x24a28 - Pattern Mask Register */
671 uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
673 uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
674 uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
675 uint pmd10; /* 0x24a40 - Pattern Match Data Register */
677 uint pmask10; /* 0x24a48 - Pattern Mask Register */
679 uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
681 uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
682 uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
683 uint pmd11; /* 0x24a60 - Pattern Match Data Register */
685 uint pmask11; /* 0x24a68 - Pattern Mask Register */
687 uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
689 uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
690 uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
691 uint pmd12; /* 0x24a80 - Pattern Match Data Register */
693 uint pmask12; /* 0x24a88 - Pattern Mask Register */
695 uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
697 uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
698 uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
699 uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
701 uint pmask13; /* 0x24aa8 - Pattern Mask Register */
703 uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
705 uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
706 uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
707 uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
709 uint pmask14; /* 0x24ac8 - Pattern Mask Register */
711 uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
713 uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
714 uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
715 uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
717 uint pmask15; /* 0x24ae8 - Pattern Mask Register */
719 uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
721 uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
722 uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
724 uint attr; /* 0x24bf8 - Attributes Register */
725 uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
729 /* PIC Registers(0x2_6000-0x4_0000-0x8_0000) */
731 typedef struct ccsr_pic {
732 char res0[106496]; /* 0x26000-0x40000 */
734 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
736 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
738 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
740 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
742 uint ctpr; /* 0x40080 - Current Task Priority Register */
744 uint whoami; /* 0x40090 - Who Am I Register */
746 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
748 uint eoi; /* 0x400b0 - End Of Interrupt Register */
750 uint frr; /* 0x41000 - Feature Reporting Register */
752 uint gcr; /* 0x41020 - Global Configuration Register */
753 #define MPC85xx_PICGCR_RST 0x80000000
754 #define MPC85xx_PICGCR_M 0x20000000
756 uint vir; /* 0x41080 - Vendor Identification Register */
758 uint pir; /* 0x41090 - Processor Initialization Register */
760 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
762 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
764 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
766 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
768 uint svr; /* 0x410e0 - Spurious Vector Register */
770 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
772 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
774 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
776 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
778 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
780 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
782 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
784 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
786 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
788 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
790 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
792 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
794 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
796 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
798 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
800 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
802 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
804 uint tcr; /* 0x41300 - Timer Control Register */
806 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
808 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
810 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
812 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
814 uint msgr0; /* 0x41400 - Message Register 0 */
816 uint msgr1; /* 0x41410 - Message Register 1 */
818 uint msgr2; /* 0x41420 - Message Register 2 */
820 uint msgr3; /* 0x41430 - Message Register 3 */
822 uint mer; /* 0x41500 - Message Enable Register */
824 uint msr; /* 0x41510 - Message Status Register */
826 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
828 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
830 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
832 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
834 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
836 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
838 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
840 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
842 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
844 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
846 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
848 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
850 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
852 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
854 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
856 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
858 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
860 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
862 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
864 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
866 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
868 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
870 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
872 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
874 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
876 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
878 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
880 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
882 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
884 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
886 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
888 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
890 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
892 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
894 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
896 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
898 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
900 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
902 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
904 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
906 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
908 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
910 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
912 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
914 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
916 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
918 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
920 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
922 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
924 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
926 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
928 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
930 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
932 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
934 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
936 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
938 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
940 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
942 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
944 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
946 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
948 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
950 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
952 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
954 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
956 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
958 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
960 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
962 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
964 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
966 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
968 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
970 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
972 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
974 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
976 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
978 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
980 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
982 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
984 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
986 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
988 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
990 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
992 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
994 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
996 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
998 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
1000 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
1002 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
1004 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
1006 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
1008 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
1010 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
1012 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
1014 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
1016 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
1018 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
1020 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
1022 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
1024 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
1026 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
1028 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
1030 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
1032 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
1033 char res150[130892];
1036 /* CPM Block(0x8_0000-0xc_0000) */
1038 typedef struct ccsr_cpm {
1042 /* 0x8000-0x8ffff:DPARM */
1044 /* 0x9000-0x90bff: General SIU */
1045 typedef struct ccsr_cpm_siu {
1057 /* 0x90c00-0x90cff: Interrupt Controller */
1058 typedef struct ccsr_cpm_intctl {
1073 } ccsr_cpm_intctl_t;
1075 /* 0x90d00-0x90d7f: input/output port */
1076 typedef struct ccsr_cpm_iop {
1103 /* 0x90d80-0x91017: CPM timers */
1104 typedef struct ccsr_cpm_timer {
1132 /* 0x91018-0x912ff: SDMA */
1133 typedef struct ccsr_cpm_sdma {
1140 /* 0x91300-0x9131f: FCC1 */
1141 typedef struct ccsr_cpm_fcc1 {
1154 u_char ftirr_phy[4];
1157 /* 0x91320-0x9133f: FCC2 */
1158 typedef struct ccsr_cpm_fcc2 {
1171 u_char ftirr_phy[4];
1174 /* 0x91340-0x9137f: FCC3 */
1175 typedef struct ccsr_cpm_fcc3 {
1191 /* 0x91380-0x9139f: FCC1 extended */
1192 typedef struct ccsr_cpm_fcc1_ext {
1200 } ccsr_cpm_fcc1_ext_t;
1202 /* 0x913a0-0x913cf: FCC2 extended */
1203 typedef struct ccsr_cpm_fcc2_ext {
1210 } ccsr_cpm_fcc2_ext_t;
1212 /* 0x913d0-0x913ff: FCC3 extended */
1213 typedef struct ccsr_cpm_fcc3_ext {
1216 } ccsr_cpm_fcc3_ext_t;
1218 /* 0x91400-0x915ef: TC layers */
1219 typedef struct ccsr_cpm_tmp1 {
1223 /* 0x915f0-0x9185f: BRGs:5,6,7,8 */
1224 typedef struct ccsr_cpm_brg2 {
1232 /* 0x91860-0x919bf: I2C */
1233 typedef struct ccsr_cpm_i2c {
1248 /* 0x919c0-0x919ef: CPM core */
1249 typedef struct ccsr_cpm_cp {
1262 /* 0x919f0-0x919ff: BRGs:1,2,3,4 */
1263 typedef struct ccsr_cpm_brg1 {
1270 /* 0x91a00-0x91a9f: SCC1-SCC4 */
1271 typedef struct ccsr_cpm_scc {
1286 /* 0x91a80-0x91a9f */
1287 typedef struct ccsr_cpm_tmp2 {
1291 /* 0x91aa0-0x91aff: SPI */
1292 typedef struct ccsr_cpm_spi {
1303 /* 0x91b00-0x91b1f: CPM MUX */
1304 typedef struct ccsr_cpm_mux {
1316 /* 0x91b20-0xbffff: SI,MCC,etc */
1317 typedef struct ccsr_cpm_tmp3 {
1321 typedef struct ccsr_cpm_iram {
1322 unsigned long iram[8192];
1326 typedef struct ccsr_cpm {
1327 /* Some references are into the unique and known dpram spaces,
1328 * others are from the generic base.
1330 #define im_dprambase im_dpram1
1331 u_char im_dpram1[16*1024];
1333 u_char im_dpram2[16*1024];
1336 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1337 ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
1338 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1339 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1340 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
1341 ccsr_cpm_fcc1_t im_cpm_fcc1;
1342 ccsr_cpm_fcc2_t im_cpm_fcc2;
1343 ccsr_cpm_fcc3_t im_cpm_fcc3;
1344 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1345 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1346 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1347 ccsr_cpm_tmp1_t im_cpm_tmp1;
1348 ccsr_cpm_brg2_t im_cpm_brg2;
1349 ccsr_cpm_i2c_t im_cpm_i2c;
1350 ccsr_cpm_cp_t im_cpm_cp;
1351 ccsr_cpm_brg1_t im_cpm_brg1;
1352 ccsr_cpm_scc_t im_cpm_scc[4];
1353 ccsr_cpm_tmp2_t im_cpm_tmp2;
1354 ccsr_cpm_spi_t im_cpm_spi;
1355 ccsr_cpm_mux_t im_cpm_mux;
1356 ccsr_cpm_tmp3_t im_cpm_tmp3;
1357 ccsr_cpm_iram_t im_cpm_iram;
1360 /* RapidIO Registers(0xc_0000-0xe_0000) */
1362 typedef struct ccsr_rio {
1363 uint didcar; /* 0xc0000 - Device Identity Capability Register */
1364 uint dicar; /* 0xc0004 - Device Information Capability Register */
1365 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
1366 uint aicar; /* 0xc000c - Assembly Information Capability Register */
1367 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
1368 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
1369 uint socar; /* 0xc0018 - Source Operations Capability Register */
1370 uint docar; /* 0xc001c - Destination Operations Capability Register */
1372 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
1373 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
1375 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
1377 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
1378 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
1380 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
1381 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
1383 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
1385 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
1386 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
1388 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
1389 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
1390 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
1391 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
1393 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
1394 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
1396 uint cr; /* 0xd0000 - Port Control Command and Status Register */
1398 uint pcr; /* 0xd0010 - Port Configuration Register */
1399 uint peir; /* 0xd0014 - Port Error Injection Register */
1401 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1403 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1405 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1407 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1409 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1411 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1413 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1415 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1417 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1419 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1421 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1423 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1425 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1427 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1429 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1431 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1433 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1435 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1437 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1439 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1441 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1443 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1445 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1447 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1449 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1451 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1453 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1455 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1457 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1459 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1461 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1463 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1465 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1467 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1469 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1471 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1473 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1475 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1477 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1479 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1481 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1482 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1483 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1484 uint pecr; /* 0xd0e0c - Port Error Control Register */
1485 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1486 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1487 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1489 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1491 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1492 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1494 uint omr; /* 0xd1000 - Outbound Mode Register */
1495 uint osr; /* 0xd1004 - Outbound Status Register */
1496 uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1497 uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
1498 uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */
1499 uint osar; /* 0xd1014 - Outbound Unit Source Address Register */
1500 uint odpr; /* 0xd1018 - Outbound Destination Port Register */
1501 uint odatr; /* 0xd101c - Outbound Destination Attributes Register */
1502 uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */
1503 uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1504 uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
1506 uint imr; /* 0xd1060 - Outbound Mode Register */
1507 uint isr; /* 0xd1064 - Inbound Status Register */
1508 uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1509 uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
1510 uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
1511 uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
1513 uint dmr; /* 0xd1460 - Doorbell Mode Register */
1514 uint dsr; /* 0xd1464 - Doorbell Status Register */
1515 uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
1516 uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */
1517 uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
1518 uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */
1520 uint pwmr; /* 0xd14e0 - Port-Write Mode Register */
1521 uint pwsr; /* 0xd14e4 - Port-Write Status Register */
1522 uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */
1523 uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */
1527 /* Global Utilities Register Block(0xe_0000-0xf_ffff) */
1528 typedef struct ccsr_gur {
1529 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
1530 uint porbmsr; /* 0xe0004 - POR boot mode status register */
1531 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1532 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
1533 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
1535 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1537 uint gpiocr; /* 0xe0030 - GPIO control register */
1539 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1541 uint gpindr; /* 0xe0050 - General-purpose input data register */
1543 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1545 uint devdisr; /* 0xe0070 - Device disable control */
1547 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1549 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1551 uint pvr; /* 0xe00a0 - Processor version register */
1552 uint svr; /* 0xe00a4 - System version register */
1554 uint clkocr; /* 0xe0e00 - Clock out select register */
1556 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1558 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
1560 uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
1561 uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
1562 uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
1563 uint res14; /* 0xe0f28 */
1564 uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
1568 typedef struct immap {
1569 ccsr_local_ecm_t im_local_ecm;
1572 ccsr_duart_t im_duart;
1574 ccsr_pcix_t im_pcix;
1575 ccsr_l2cache_t im_l2cache;
1577 ccsr_tsec_t im_tsec1;
1578 ccsr_tsec_t im_tsec2;
1585 extern immap_t *immr;
1587 #endif /*__IMMAP_85xx__*/