2 * (C) Copyright 2004-2006 Freescale Semiconductor, Inc.
4 * MPC83xx Internal Memory Map
7 * 20060601: Daveliu (daveliu@freescale.com)
8 * TanyaJiang (tanya.jiang@freescale.com)
9 * Unified variable names for mpc83xx
10 * 2005 : Mandy Lavi (mandy.lavi@freescale.com)
11 * support for mpc8360e
12 * 2004 : Eran Liberty (liberty@freescale.com)
13 * Initialized for mpc8349
15 * MPC8260 Internal Memory Map
16 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
17 * MPC85xx Internal Memory Map
18 * Copyright(c) 2002,2003 Motorola Inc.
19 * Xianghua Xiao (x.xiao@motorola.com)
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #ifndef __IMMAP_83xx__
38 #define __IMMAP_83xx__
41 #include <asm/types.h>
45 * Local Access Window.
47 typedef struct law83xx {
48 u32 bar; /* LBIU local access window base address register */
49 /* Identifies the 20 most-significant address bits of the base of local
50 * access window n. The specified base address should be aligned to the
51 * window size, as defined by LBLAWARn[SIZE].
53 #define LAWBAR_BAR 0xFFFFF000
54 #define LAWBAR_RES ~(LAWBAR_BAR)
55 u32 ar; /* LBIU local access window attribute register */
59 * System configuration registers.
61 typedef struct sysconf83xx {
62 u32 immrbar; /* Internal memory map base address register */
64 u32 altcbar; /* Alternate configuration base address register */
65 /* Identifies the12 most significant address bits of an alternate base
66 * address used for boot sequencer configuration accesses.
68 #define ALTCBAR_BASE_ADDR 0xFFF00000
69 #define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
71 law83xx_t lblaw[4]; /* LBIU local access window */
73 law83xx_t pcilaw[2]; /* PCI local access window */
75 law83xx_t ddrlaw[2]; /* DDR local access window */
77 u32 sgprl; /* System General Purpose Register Low */
78 u32 sgprh; /* System General Purpose Register High */
79 u32 spridr; /* System Part and Revision ID Register */
80 #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */
81 #define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */
83 u32 spcr; /* System Priority Configuration Register */
84 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */
85 #define SPCR_PCIHPE_SHIFT (31-3)
86 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */
87 #define SPCR_PCIPR_SHIFT (31-7)
88 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */
89 #define SPCR_TBEN_SHIFT (31-9)
90 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */
91 #define SPCR_COREPR_SHIFT (31-11)
92 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */
93 #define SPCR_TSEC1DP_SHIFT (31-19)
94 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
95 #define SPCR_TSEC1BDP_SHIFT (31-21)
96 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */
97 #define SPCR_TSEC1EP_SHIFT (31-23)
98 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */
99 #define SPCR_TSEC2DP_SHIFT (31-27)
100 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
101 #define SPCR_TSEC2BDP_SHIFT (31-29)
102 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */
103 #define SPCR_TSEC2EP_SHIFT (31-31)
104 #define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
105 | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
106 | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
107 u32 sicrl; /* System General Purpose Register Low */
108 #define SICRL_LDP_A 0x80000000
109 #define SICRL_USB1 0x40000000
110 #define SICRL_USB0 0x20000000
111 #define SICRL_UART 0x0C000000
112 #define SICRL_GPIO1_A 0x02000000
113 #define SICRL_GPIO1_B 0x01000000
114 #define SICRL_GPIO1_C 0x00800000
115 #define SICRL_GPIO1_D 0x00400000
116 #define SICRL_GPIO1_E 0x00200000
117 #define SICRL_GPIO1_F 0x00180000
118 #define SICRL_GPIO1_G 0x00040000
119 #define SICRL_GPIO1_H 0x00020000
120 #define SICRL_GPIO1_I 0x00010000
121 #define SICRL_GPIO1_J 0x00008000
122 #define SICRL_GPIO1_K 0x00004000
123 #define SICRL_GPIO1_L 0x00003000
124 #define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
125 | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
126 | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
127 | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
128 | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
129 u32 sicrh; /* System General Purpose Register High */
130 #define SICRH_DDR 0x80000000
131 #define SICRH_TSEC1_A 0x10000000
132 #define SICRH_TSEC1_B 0x08000000
133 #define SICRH_TSEC1_C 0x04000000
134 #define SICRH_TSEC1_D 0x02000000
135 #define SICRH_TSEC1_E 0x01000000
136 #define SICRH_TSEC1_F 0x00800000
137 #define SICRH_TSEC2_A 0x00400000
138 #define SICRH_TSEC2_B 0x00200000
139 #define SICRH_TSEC2_C 0x00100000
140 #define SICRH_TSEC2_D 0x00080000
141 #define SICRH_TSEC2_E 0x00040000
142 #define SICRH_TSEC2_F 0x00020000
143 #define SICRH_TSEC2_G 0x00010000
144 #define SICRH_TSEC2_H 0x00008000
145 #define SICRH_GPIO2_A 0x00004000
146 #define SICRH_GPIO2_B 0x00002000
147 #define SICRH_GPIO2_C 0x00001000
148 #define SICRH_GPIO2_D 0x00000800
149 #define SICRH_GPIO2_E 0x00000400
150 #define SICRH_GPIO2_F 0x00000200
151 #define SICRH_GPIO2_G 0x00000180
152 #define SICRH_GPIO2_H 0x00000060
153 #define SICRH_TSOBI1 0x00000002
154 #define SICRH_TSOBI2 0x00000001
155 #define SICRH_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
156 | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
157 | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
158 | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
159 | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
160 | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
161 | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
162 | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
168 * Watch Dog Timer (WDT) Registers
170 typedef struct wdt83xx {
172 u32 swcrr; /* System watchdog control register */
173 u32 swcnr; /* System watchdog count register */
174 #define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
175 #define SWCNR_RES ~(SWCNR_SWCN)
177 u16 swsrr; /* System watchdog service register */
178 #define SWSRR_WS 0x0000FFFF /* Software Watchdog Service Field.*/
183 * RTC/PIT Module Registers
185 typedef struct rtclk83xx {
186 u32 cnr; /* control register */
187 #define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */
188 #define CNR_CLIN 0x00000040 /* Input Clock Control Bit */
189 #define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */
190 #define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */
191 #define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
192 u32 ldr; /* load register */
193 #define LDR_CLDV 0xFFFFFFFF /* Contains the 32-bit value to be
194 * loaded in a 32-bit RTC counter.*/
195 u32 psr; /* prescale register */
196 #define PSR_PRSC 0xFFFFFFFF /* RTC Prescaler bits.*/
197 u32 ctr; /* Counter value field register */
198 #define CRT_CNTV 0xFFFFFFFF /* RTC Counter value field.*/
199 u32 evr; /* event register */
200 #define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */
201 #define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */
202 #define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF)
203 #define PTEVR_PIF 0x00000001 /* Periodic interrupt flag bit.*/
204 #define PTEVR_RES ~(PTEVR_PIF)
205 u32 alr; /* alarm register */
210 * Global timper module
213 typedef struct gtm83xx {
214 u8 cfr1; /* Timer1/2 Configuration */
215 #define CFR1_PCAS 0x80 /* Pair Cascade mode */
216 #define CFR1_BCM 0x40 /* Backward compatible mode */
217 #define CFR1_STP2 0x20 /* Stop timer */
218 #define CFR1_RST2 0x10 /* Reset timer */
219 #define CFR1_GM2 0x08 /* Gate mode for pin 2 */
220 #define CFR1_GM1 0x04 /* Gate mode for pin 1 */
221 #define CFR1_STP1 0x02 /* Stop timer */
222 #define CFR1_RST1 0x01 /* Reset timer */
223 #define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\
224 CFR1_GM1 | CFR1_STP1 | CFR1_RST1)
226 u8 cfr2; /* Timer3/4 Configuration */
227 #define CFR2_PCAS 0x80 /* Pair Cascade mode */
228 #define CFR2_SCAS 0x40 /* Super Cascade mode */
229 #define CFR2_STP4 0x20 /* Stop timer */
230 #define CFR2_RST4 0x10 /* Reset timer */
231 #define CFR2_GM4 0x08 /* Gate mode for pin 4 */
232 #define CFR2_GM3 0x04 /* Gate mode for pin 3 */
233 #define CFR2_STP3 0x02 /* Stop timer */
234 #define CFR2_RST3 0x01 /* Reset timer */
236 u16 mdr1; /* Timer1 Mode Register */
237 #define MDR_SPS 0xff00 /* Secondary Prescaler value */
238 #define MDR_CE 0x00c0 /* Capture edge and enable interrupt */
239 #define MDR_OM 0x0020 /* Output mode */
240 #define MDR_ORI 0x0010 /* Output reference interrupt enable */
241 #define MDR_FRR 0x0008 /* Free run/restart */
242 #define MDR_ICLK 0x0006 /* Input clock source for the timer */
243 #define MDR_GE 0x0001 /* Gate enable */
244 u16 mdr2; /* Timer2 Mode Register */
245 u16 rfr1; /* Timer1 Reference Register */
246 u16 rfr2; /* Timer2 Reference Register */
247 u16 cpr1; /* Timer1 Capture Register */
248 u16 cpr2; /* Timer2 Capture Register */
249 u16 cnr1; /* Timer1 Counter Register */
250 u16 cnr2; /* Timer2 Counter Register */
251 u16 mdr3; /* Timer3 Mode Register */
252 u16 mdr4; /* Timer4 Mode Register */
253 u16 rfr3; /* Timer3 Reference Register */
254 u16 rfr4; /* Timer4 Reference Register */
255 u16 cpr3; /* Timer3 Capture Register */
256 u16 cpr4; /* Timer4 Capture Register */
257 u16 cnr3; /* Timer3 Counter Register */
258 u16 cnr4; /* Timer4 Counter Register */
259 u16 evr1; /* Timer1 Event Register */
260 u16 evr2; /* Timer2 Event Register */
261 u16 evr3; /* Timer3 Event Register */
262 u16 evr4; /* Timer4 Event Register */
263 #define GTEVR_REF 0x0002 /* Output reference event */
264 #define GTEVR_CAP 0x0001 /* Counter Capture event */
265 #define GTEVR_RES ~(EVR_CAP|EVR_REF)
266 u16 psr1; /* Timer1 Prescaler Register */
267 u16 psr2; /* Timer2 Prescaler Register */
268 u16 psr3; /* Timer3 Prescaler Register */
269 u16 psr4; /* Timer4 Prescaler Register */
270 #define GTPSR_PPS 0x00FF /* Primary Prescaler Bits. */
271 #define GTPSR_RES ~(GTPSR_PPS)
276 * Integrated Programmable Interrupt Controller
278 typedef struct ipic83xx {
279 u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */
280 #define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */
281 #define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */
282 #define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */
283 #define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */
284 #define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */
285 #define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */
286 #define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
287 u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */
288 #define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */
289 #define SICVR_IVEC 0x0000007f /* Interrupt vector */
290 #define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
291 u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */
292 #define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */
293 #define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */
294 #define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */
295 #define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */
296 #define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */
297 #define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */
298 #define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */
299 #define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */
300 #define SIIH_UART1 0x00000080 /* UART1 interrupt */
301 #define SIIH_UART2 0x00000040 /* UART2 interrupt */
302 #define SIIH_SEC 0x00000020 /* SEC interrupt */
303 #define SIIH_I2C1 0x00000004 /* I2C1 interrupt */
304 #define SIIH_I2C2 0x00000002 /* I2C2 interrupt */
305 #define SIIH_SPI 0x00000001 /* SPI interrupt */
306 #define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
307 | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
308 | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
309 | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
310 | SIIH_I2C2 | SIIH_SPI)
311 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */
312 #define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */
313 #define SIIL_PIT 0x40000000 /* PIT interrupt */
314 #define SIIL_PCI1 0x20000000 /* PCI1 interrupt */
315 #define SIIL_PCI2 0x10000000 /* PCI2 interrupt */
316 #define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */
317 #define SIIL_MU 0x04000000 /* Message Unit interrupt */
318 #define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */
319 #define SIIL_DMA 0x01000000 /* DMA interrupt */
320 #define SIIL_GTM4 0x00800000 /* GTM4 interrupt */
321 #define SIIL_GTM8 0x00400000 /* GTM8 interrupt */
322 #define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */
323 #define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */
324 #define SIIL_DDR 0x00080000 /* DDR interrupt */
325 #define SIIL_LBC 0x00040000 /* LBC interrupt */
326 #define SIIL_GTM2 0x00020000 /* GTM2 interrupt */
327 #define SIIL_GTM6 0x00010000 /* GTM6 interrupt */
328 #define SIIL_PMC 0x00008000 /* PMC interrupt */
329 #define SIIL_GTM3 0x00000800 /* GTM3 interrupt */
330 #define SIIL_GTM7 0x00000400 /* GTM7 interrupt */
331 #define SIIL_GTM1 0x00000020 /* GTM1 interrupt */
332 #define SIIL_GTM5 0x00000010 /* GTM5 interrupt */
333 #define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */
334 #define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
335 | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
336 | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
337 | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
338 | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
339 | SIIL_GTM5 |SIIL_DPTC )
340 u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */
342 u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */
343 u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */
344 u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */
346 u32 sepnr; /* System External Interrupt Pending Register (SEI) */
347 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */
348 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */
349 #define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
350 #define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
351 #define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
352 #define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
353 #define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
354 #define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
355 #define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
356 #define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
357 #define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
358 u32 semsr; /* System External Interrupt Mask Register (SEI) */
359 #define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */
360 #define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */
361 #define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */
362 #define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */
363 #define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */
364 #define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */
365 #define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */
366 #define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */
367 #define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */
368 #define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
369 | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
371 u32 secnr; /* System External Interrupt Control Register (SECNR) */
372 #define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */
373 #define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */
374 #define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */
375 #define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */
376 #define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */
377 #define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */
378 #define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */
379 #define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */
380 #define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */
381 #define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */
382 #define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */
383 #define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */
384 #define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
385 | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
386 | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
387 | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
388 u32 sersr; /* System Error Status Register (SERR) */
389 u32 sermr; /* System Error Mask Register (SERR) */
390 #define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */
391 #define SERR_WDT 0x40000000 /* WDT MCP request */
392 #define SERR_SBA 0x20000000 /* SBA MCP request */
393 #define SERR_DDR 0x10000000 /* DDR MCP request */
394 #define SERR_LBC 0x08000000 /* LBC MCP request */
395 #define SERR_PCI1 0x04000000 /* PCI1 MCP request */
396 #define SERR_PCI2 0x02000000 /* PCI2 MCP request */
397 #define SERR_MU 0x01000000 /* MU MCP request */
398 #define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */
399 #define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
400 |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
402 u32 sercr; /* System Error Control Register (SERCR) */
403 #define SERCR_MCPR 0x00000001 /* MCP Route */
404 #define SERCR_RES ~(SERCR_MCPR)
406 u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */
407 u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */
408 u32 sefcr; /* System External Interrupt Force Register (SEI) */
409 u32 serfr; /* System Error Force Register (SERR) */
410 u32 scvcr; /* System Critical Interrupt Vector Register */
411 #define SCVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible
412 critical interrupt vector. */
413 #define SCVCR_CVEC 0x0000007F /* Critical interrupt vector */
414 #define SCVCR_RES ~(SCVCR_CVECX|SCVCR_CVEC)
415 u32 smvcr; /* System Management Interrupt Vector Register */
416 #define SMVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible
417 critical interrupt vector. */
418 #define SMVCR_CVEC 0x0000007F /* Critical interrupt vector */
419 #define SMVCR_RES ~(SMVCR_CVECX|SMVCR_CVEC)
424 * System Arbiter Registers
426 typedef struct arbiter83xx {
427 u32 acr; /* Arbiter Configuration Register */
428 #define ACR_COREDIS 0x10000000 /* Core disable. */
429 #define ACR_COREDIS_SHIFT (31-7)
430 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */
431 #define ACR_PIPE_DEP_SHIFT (31-15)
432 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
433 #define ACR_PCI_RPTCNT_SHIFT (31-19)
434 #define ACR_RPTCNT 0x00000700 /* Repeat count. */
435 #define ACR_RPTCNT_SHIFT (31-23)
436 #define ACR_APARK 0x00000030 /* Address parking. */
437 #define ACR_APARK_SHIFT (31-27)
438 #define ACR_PARKM 0x0000000F /* Parking master. */
439 #define ACR_PARKM_SHIFT (31-31)
440 #define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
441 u32 atr; /* Arbiter Timers Register */
442 #define ATR_DTO 0x00FF0000 /* Data time out. */
443 #define ATR_ATO 0x000000FF /* Address time out. */
444 #define ATR_RES ~(ATR_DTO|ATR_ATO)
446 u32 aer; /* Arbiter Event Register (AE)*/
447 u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
448 u32 amr; /* Arbiter Mask Register (AE) */
449 u32 aeatr; /* Arbiter Event Attributes Register */
450 #define AEATR_EVENT 0x07000000 /* Event type. */
451 #define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
452 #define AEATR_TBST 0x00000800 /* Transfer burst. */
453 #define AEATR_TSIZE 0x00000700 /* Transfer Size. */
454 #define AEATR_TTYPE 0x0000001F /* Transfer Type. */
455 #define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
456 u32 aeadr; /* Arbiter Event Address Register */
457 u32 aerr; /* Arbiter Event Response Register (AE)*/
458 #define AE_ETEA 0x00000020 /* Transfer error. */
459 #define AE_RES_ 0x00000010 /* Reserved transfer type. */
460 #define AE_ECW 0x00000008 /* External control word transfer type. */
461 #define AE_AO 0x00000004 /* Address Only transfer type. */
462 #define AE_DTO 0x00000002 /* Data time out. */
463 #define AE_ATO 0x00000001 /* Address time out. */
464 #define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
471 typedef struct reset83xx {
472 u32 rcwl; /* RCWL Register */
473 #define RCWL_LBIUCM 0x80000000 /* LBIUCM */
474 #define RCWL_LBIUCM_SHIFT 31
475 #define RCWL_DDRCM 0x40000000 /* DDRCM */
476 #define RCWL_DDRCM_SHIFT 30
477 #define RCWL_SVCOD 0x30000000 /* SVCOD */
478 #define RCWL_SPMF 0x0f000000 /* SPMF */
479 #define RCWL_SPMF_SHIFT 24
480 #define RCWL_COREPLL 0x007F0000 /* COREPLL */
481 #define RCWL_COREPLL_SHIFT 16
482 #define RCWL_CEVCOD 0x000000C0 /* CEVCOD */
483 #define RCWL_CEPDF 0x00000020 /* CEPDF */
484 #define RCWL_CEPMF 0x0000001F /* CEPMF */
485 #define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
486 u32 rcwh; /* RCHL Register */
487 #define RCWH_PCIHOST 0x80000000 /* PCIHOST */
488 #define RCWH_PCIHOST_SHIFT 31
489 #define RCWH_PCI64 0x40000000 /* PCI64 */
490 #define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */
491 #define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */
492 #define RCWH_COREDIS 0x08000000 /* COREDIS */
493 #define RCWH_BMS 0x04000000 /* BMS */
494 #define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */
495 #define RCWH_SWEN 0x00800000 /* SWEN */
496 #define RCWH_ROMLOC 0x00700000 /* ROMLOC */
497 #define RCWH_TSEC1M 0x0000c000 /* TSEC1M */
498 #define RCWH_TSEC2M 0x00003000 /* TSEC2M */
499 #define RCWH_TPR 0x00000100 /* TPR */
500 #define RCWH_TLE 0x00000008 /* TLE */
501 #define RCWH_LALE 0x00000004 /* LALE */
502 #define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
503 | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
504 | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
505 | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
506 | RCWH_TLE | RCWH_LALE)
508 u32 rsr; /* Reset status Register */
509 #define RSR_RSTSRC 0xE0000000 /* Reset source */
510 #define RSR_RSTSRC_SHIFT 29
511 #define RSR_BSF 0x00010000 /* Boot seq. fail */
512 #define RSR_BSF_SHIFT 16
513 #define RSR_SWSR 0x00002000 /* software soft reset */
514 #define RSR_SWSR_SHIFT 13
515 #define RSR_SWHR 0x00001000 /* software hard reset */
516 #define RSR_SWHR_SHIFT 12
517 #define RSR_JHRS 0x00000200 /* jtag hreset */
518 #define RSR_JHRS_SHIFT 9
519 #define RSR_JSRS 0x00000100 /* jtag sreset status */
520 #define RSR_JSRS_SHIFT 8
521 #define RSR_CSHR 0x00000010 /* checkstop reset status */
522 #define RSR_CSHR_SHIFT 4
523 #define RSR_SWRS 0x00000008 /* software watchdog reset status */
524 #define RSR_SWRS_SHIFT 3
525 #define RSR_BMRS 0x00000004 /* bus monitop reset status */
526 #define RSR_BMRS_SHIFT 2
527 #define RSR_SRS 0x00000002 /* soft reset status */
528 #define RSR_SRS_SHIFT 1
529 #define RSR_HRS 0x00000001 /* hard reset status */
530 #define RSR_HRS_SHIFT 0
531 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
532 u32 rmr; /* Reset mode Register */
533 #define RMR_CSRE 0x00000001 /* checkstop reset enable */
534 #define RMR_CSRE_SHIFT 0
535 #define RMR_RES ~(RMR_CSRE)
536 u32 rpr; /* Reset protection Register */
537 u32 rcr; /* Reset Control Register */
538 #define RCR_SWHR 0x00000002 /* software hard reset */
539 #define RCR_SWSR 0x00000001 /* software soft reset */
540 #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
541 u32 rcer; /* Reset Control Enable Register */
542 #define RCER_CRE 0x00000001 /* software hard reset */
543 #define RCER_RES ~(RCER_CRE)
547 typedef struct clk83xx {
548 u32 spmr; /* system PLL mode Register */
549 #define SPMR_LBIUCM 0x80000000 /* LBIUCM */
550 #define SPMR_DDRCM 0x40000000 /* DDRCM */
551 #define SPMR_SVCOD 0x30000000 /* SVCOD */
552 #define SPMR_SPMF 0x0F000000 /* SPMF */
553 #define SPMR_CKID 0x00800000 /* CKID */
554 #define SPMR_CKID_SHIFT 23
555 #define SPMR_COREPLL 0x007F0000 /* COREPLL */
556 #define SPMR_CEVCOD 0x000000C0 /* CEVCOD */
557 #define SPMR_CEPDF 0x00000020 /* CEPDF */
558 #define SPMR_CEPMF 0x0000001F /* CEPMF */
559 #define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
560 | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
561 | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
562 u32 occr; /* output clock control Register */
563 #define OCCR_PCICOE0 0x80000000 /* PCICOE0 */
564 #define OCCR_PCICOE1 0x40000000 /* PCICOE1 */
565 #define OCCR_PCICOE2 0x20000000 /* PCICOE2 */
566 #define OCCR_PCICOE3 0x10000000 /* PCICOE3 */
567 #define OCCR_PCICOE4 0x08000000 /* PCICOE4 */
568 #define OCCR_PCICOE5 0x04000000 /* PCICOE5 */
569 #define OCCR_PCICOE6 0x02000000 /* PCICOE6 */
570 #define OCCR_PCICOE7 0x01000000 /* PCICOE7 */
571 #define OCCR_PCICD0 0x00800000 /* PCICD0 */
572 #define OCCR_PCICD1 0x00400000 /* PCICD1 */
573 #define OCCR_PCICD2 0x00200000 /* PCICD2 */
574 #define OCCR_PCICD3 0x00100000 /* PCICD3 */
575 #define OCCR_PCICD4 0x00080000 /* PCICD4 */
576 #define OCCR_PCICD5 0x00040000 /* PCICD5 */
577 #define OCCR_PCICD6 0x00020000 /* PCICD6 */
578 #define OCCR_PCICD7 0x00010000 /* PCICD7 */
579 #define OCCR_PCI1CR 0x00000002 /* PCI1CR */
580 #define OCCR_PCI2CR 0x00000001 /* PCI2CR */
581 #define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
582 | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
583 | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
584 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \
585 | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \
586 | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR )
587 u32 sccr; /* system clock control Register */
588 #define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */
589 #define SCCR_TSEC1CM_SHIFT 30
590 #define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */
591 #define SCCR_TSEC2CM_SHIFT 28
592 #define SCCR_ENCCM 0x03000000 /* ENCCM */
593 #define SCCR_ENCCM_SHIFT 24
594 #define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */
595 #define SCCR_USBMPHCM_SHIFT 22
596 #define SCCR_USBDRCM 0x00300000 /* USBDRCM */
597 #define SCCR_USBDRCM_SHIFT 20
598 #define SCCR_PCICM 0x00010000 /* PCICM */
599 #define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
600 | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
605 * Power Management Control Module
607 typedef struct pmc83xx {
608 u32 pmccr; /* PMC Configuration Register */
609 #define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */
610 #define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */
611 #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
612 u32 pmcer; /* PMC Event Register */
613 #define PMCER_PMCI 0x00000001 /* PMC Interrupt */
614 #define PMCER_RES ~(PMCER_PMCI)
615 u32 pmcmr; /* PMC Mask Register */
616 #define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */
617 #define PMCMR_RES ~(PMCMR_PMCIE)
622 * general purpose I/O module
624 typedef struct gpio83xx {
625 u32 dir; /* direction register */
626 u32 odr; /* open drain register */
627 u32 dat; /* data register */
628 u32 ier; /* interrupt event register */
629 u32 imr; /* interrupt mask register */
630 u32 icr; /* external interrupt control register */
635 * DDR Memory Controller Memory Map
637 typedef struct ddr_cs_bnds{
639 #define CSBNDS_SA 0x00FF0000
640 #define CSBNDS_SA_SHIFT 8
641 #define CSBNDS_EA 0x000000FF
642 #define CSBNDS_EA_SHIFT 24
646 typedef struct ddr83xx {
647 ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */
649 u32 cs_config[4]; /**< Chip Select x Configuration */
650 #define CSCONFIG_EN 0x80000000
651 #define CSCONFIG_AP 0x00800000
652 #define CSCONFIG_ROW_BIT 0x00000700
653 #define CSCONFIG_ROW_BIT_12 0x00000000
654 #define CSCONFIG_ROW_BIT_13 0x00000100
655 #define CSCONFIG_ROW_BIT_14 0x00000200
656 #define CSCONFIG_COL_BIT 0x00000007
657 #define CSCONFIG_COL_BIT_8 0x00000000
658 #define CSCONFIG_COL_BIT_9 0x00000001
659 #define CSCONFIG_COL_BIT_10 0x00000002
660 #define CSCONFIG_COL_BIT_11 0x00000003
662 u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */
663 #define TIMING_CFG1_PRETOACT 0x70000000
664 #define TIMING_CFG1_PRETOACT_SHIFT 28
665 #define TIMING_CFG1_ACTTOPRE 0x0F000000
666 #define TIMING_CFG1_ACTTOPRE_SHIFT 24
667 #define TIMING_CFG1_ACTTORW 0x00700000
668 #define TIMING_CFG1_ACTTORW_SHIFT 20
669 #define TIMING_CFG1_CASLAT 0x00070000
670 #define TIMING_CFG1_CASLAT_SHIFT 16
671 #define TIMING_CFG1_REFREC 0x0000F000
672 #define TIMING_CFG1_REFREC_SHIFT 12
673 #define TIMING_CFG1_WRREC 0x00000700
674 #define TIMING_CFG1_WRREC_SHIFT 8
675 #define TIMING_CFG1_ACTTOACT 0x00000070
676 #define TIMING_CFG1_ACTTOACT_SHIFT 4
677 #define TIMING_CFG1_WRTORD 0x00000007
678 #define TIMING_CFG1_WRTORD_SHIFT 0
679 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
680 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
682 u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
683 #define TIMING_CFG2_CPO 0x0F000000
684 #define TIMING_CFG2_CPO_SHIFT 24
685 #define TIMING_CFG2_ACSM 0x00080000
686 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
687 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
688 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */
690 u32 sdram_cfg; /**< SDRAM Control Configuration */
691 #define SDRAM_CFG_MEM_EN 0x80000000
692 #define SDRAM_CFG_SREN 0x40000000
693 #define SDRAM_CFG_ECC_EN 0x20000000
694 #define SDRAM_CFG_RD_EN 0x10000000
695 #define SDRAM_CFG_SDRAM_TYPE 0x03000000
696 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
697 #define SDRAM_CFG_DYN_PWR 0x00200000
698 #define SDRAM_CFG_32_BE 0x00080000
699 #define SDRAM_CFG_8_BE 0x00040000
700 #define SDRAM_CFG_NCAP 0x00020000
701 #define SDRAM_CFG_2T_EN 0x00008000
702 #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
705 u32 sdram_mode; /**< SDRAM Mode Configuration */
706 #define SDRAM_MODE_ESD 0xFFFF0000
707 #define SDRAM_MODE_ESD_SHIFT 16
708 #define SDRAM_MODE_SD 0x0000FFFF
709 #define SDRAM_MODE_SD_SHIFT 0
710 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */
711 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */
712 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
713 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */
714 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */
715 #define DDR_MODE_WEAK 0x0002 /* weak drivers */
716 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */
717 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */
718 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
719 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
720 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
721 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
722 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */
723 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */
724 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
725 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
726 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */
727 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */
728 #define DDR_MODE_MODEREG 0x0000 /* select mode register */
731 u32 sdram_interval; /**< SDRAM Interval Configuration */
732 #define SDRAM_INTERVAL_REFINT 0x3FFF0000
733 #define SDRAM_INTERVAL_REFINT_SHIFT 16
734 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
735 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
738 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
739 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
740 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
741 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
742 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
745 u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
746 u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
747 u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */
748 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */
749 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */
750 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */
751 #define ECC_ERR_INJECT_EEIM_SHIFT 0
753 u32 capture_data_hi; /**< Memory Data Path Read Capture High */
754 u32 capture_data_lo; /**< Memory Data Path Read Capture Low */
755 u32 capture_ecc; /**< Memory Data Path Read Capture ECC */
756 #define CAPTURE_ECC_ECE (0xff000000>>24)
757 #define CAPTURE_ECC_ECE_SHIFT 0
759 u32 err_detect; /**< Memory Error Detect */
760 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */
761 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */
762 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */
763 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */
764 u32 err_disable; /**< Memory Error Disable */
765 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */
766 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */
767 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */
768 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED)
769 u32 err_int_en; /**< Memory Error Interrupt Enable */
770 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */
771 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */
772 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */
773 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE)
774 u32 capture_attributes; /**< Memory Error Attributes Capture */
775 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */
776 #define ECC_CAPT_ATTR_BNUM_SHIFT 28
777 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */
778 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
779 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
780 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
781 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
782 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24
783 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */
784 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
785 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
786 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
787 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
788 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
789 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
790 #define ECC_CAPT_ATTR_TSRC_I2C 0x9
791 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA
792 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD
793 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE
794 #define ECC_CAPT_ATTR_TSRC_DMA 0xF
795 #define ECC_CAPT_ATTR_TSRC_SHIFT 16
796 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */
797 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1
798 #define ECC_CAPT_ATTR_TTYP_READ 0x2
799 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
800 #define ECC_CAPT_ATTR_TTYP_SHIFT 12
801 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */
802 u32 capture_address; /**< Memory Error Address Capture */
803 u32 capture_ext_address;/**< Memory Error Extended Address Capture */
804 u32 err_sbe; /**< Memory Single-Bit ECC Error Management */
805 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255*/
806 #define ECC_ERROR_MAN_SBET_SHIFT 16
807 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255*/
808 #define ECC_ERROR_MAN_SBEC_SHIFT 0
822 typedef struct duart83xx{
823 u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
824 u8 uier_udmb; /**< combined register for UIER and UDMB */
825 u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
826 u8 ulcr; /**< line control register */
827 u8 umcr; /**< MODEM control register */
828 u8 ulsr; /**< line status register */
829 u8 umsr; /**< MODEM status register */
830 u8 uscr; /**< scratch register */
832 u8 udsr; /**< DMA status register */
838 * Local Bus Controller Registers
840 typedef struct lbus_bank{
841 u32 br; /**< Base Register */
842 u32 or; /**< Base Register */
845 typedef struct lbus83xx {
848 u32 mar; /**< UPM Address Register */
850 u32 mamr; /**< UPMA Mode Register */
851 u32 mbmr; /**< UPMB Mode Register */
852 u32 mcmr; /**< UPMC Mode Register */
854 u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
855 u32 mdr; /**< UPM Data Register */
857 u32 lsdmr; /**< SDRAM Mode Register */
859 u32 lurt; /**< UPM Refresh Timer */
860 u32 lsrt; /**< SDRAM Refresh Timer */
862 u32 ltesr; /**< Transfer Error Status Register */
863 u32 ltedr; /**< Transfer Error Disable Register */
864 u32 lteir; /**< Transfer Error Interrupt Register */
865 u32 lteatr; /**< Transfer Error Attributes Register */
866 u32 ltear; /**< Transfer Error Address Register */
868 u32 lbcr; /**< Configuration Register */
869 #define LBCR_LDIS 0x80000000
870 #define LBCR_LDIS_SHIFT 31
871 #define LBCR_BCTLC 0x00C00000
872 #define LBCR_BCTLC_SHIFT 22
873 #define LBCR_LPBSE 0x00020000
874 #define LBCR_LPBSE_SHIFT 17
875 #define LBCR_EPAR 0x00010000
876 #define LBCR_EPAR_SHIFT 16
877 #define LBCR_BMT 0x0000FF00
878 #define LBCR_BMT_SHIFT 8
879 u32 lcrr; /**< Clock Ratio Register */
880 #define LCRR_DBYP 0x80000000
881 #define LCRR_DBYP_SHIFT 31
882 #define LCRR_BUFCMDC 0x30000000
883 #define LCRR_BUFCMDC_SHIFT 28
884 #define LCRR_ECL 0x03000000
885 #define LCRR_ECL_SHIFT 24
886 #define LCRR_EADC 0x00030000
887 #define LCRR_EADC_SHIFT 16
888 #define LCRR_CLKDIV 0x0000000F
889 #define LCRR_CLKDIV_SHIFT 0
897 * Serial Peripheral Interface
899 typedef struct spi83xx
901 u32 mode; /**< mode register */
902 u32 event; /**< event register */
903 u32 mask; /**< mask register */
904 u32 com; /**< command register */
906 u32 tx; /**< transmit register */
907 u32 rx; /**< receive register */
915 typedef struct dma83xx {
916 u32 res0[0xC]; /* 0x0-0x29 reseverd */
917 u32 omisr; /* 0x30 Outbound message interrupt status register */
918 u32 omimr; /* 0x34 Outbound message interrupt mask register */
919 u32 res1[0x6]; /* 0x38-0x49 reserved */
921 u32 imr0; /* 0x50 Inbound message register 0 */
922 u32 imr1; /* 0x54 Inbound message register 1 */
923 u32 omr0; /* 0x58 Outbound message register 0 */
924 u32 omr1; /* 0x5C Outbound message register 1 */
926 u32 odr; /* 0x60 Outbound doorbell register */
927 u32 res2; /* 0x64-0x67 reserved */
928 u32 idr; /* 0x68 Inbound doorbell register */
929 u32 res3[0x5]; /* 0x6C-0x79 reserved */
931 u32 imisr; /* 0x80 Inbound message interrupt status register */
932 u32 imimr; /* 0x84 Inbound message interrupt mask register */
933 u32 res4[0x1E]; /* 0x88-0x99 reserved */
935 u32 dmamr0; /* 0x100 DMA 0 mode register */
936 u32 dmasr0; /* 0x104 DMA 0 status register */
937 u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */
938 u32 res5; /* 0x10C reserved */
939 u32 dmasar0; /* 0x110 DMA 0 source address register */
940 u32 res6; /* 0x114 reserved */
941 u32 dmadar0; /* 0x118 DMA 0 destination address register */
942 u32 res7; /* 0x11C reserved */
943 u32 dmabcr0; /* 0x120 DMA 0 byte count register */
944 u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */
945 u32 res8[0x16]; /* 0x128-0x179 reserved */
947 u32 dmamr1; /* 0x180 DMA 1 mode register */
948 u32 dmasr1; /* 0x184 DMA 1 status register */
949 u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */
950 u32 res9; /* 0x18C reserved */
951 u32 dmasar1; /* 0x190 DMA 1 source address register */
952 u32 res10; /* 0x194 reserved */
953 u32 dmadar1; /* 0x198 DMA 1 destination address register */
954 u32 res11; /* 0x19C reserved */
955 u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */
956 u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */
957 u32 res12[0x16];/* 0x1A8-0x199 reserved */
959 u32 dmamr2; /* 0x200 DMA 2 mode register */
960 u32 dmasr2; /* 0x204 DMA 2 status register */
961 u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */
962 u32 res13; /* 0x20C reserved */
963 u32 dmasar2; /* 0x210 DMA 2 source address register */
964 u32 res14; /* 0x214 reserved */
965 u32 dmadar2; /* 0x218 DMA 2 destination address register */
966 u32 res15; /* 0x21C reserved */
967 u32 dmabcr2; /* 0x220 DMA 2 byte count register */
968 u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */
969 u32 res16[0x16];/* 0x228-0x279 reserved */
971 u32 dmamr3; /* 0x280 DMA 3 mode register */
972 u32 dmasr3; /* 0x284 DMA 3 status register */
973 u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */
974 u32 res17; /* 0x28C reserved */
975 u32 dmasar3; /* 0x290 DMA 3 source address register */
976 u32 res18; /* 0x294 reserved */
977 u32 dmadar3; /* 0x298 DMA 3 destination address register */
978 u32 res19; /* 0x29C reserved */
979 u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */
980 u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */
982 u32 dmagsr; /* 0x2A8 DMA general status register */
983 u32 res20[0x15];/* 0x2AC-0x2FF reserved */
987 #define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */
988 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */
989 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */
990 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */
991 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */
992 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */
993 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */
994 #define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */
997 #define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */
998 #define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */
1001 * PCI Software Configuration Registers
1003 typedef struct pciconf83xx {
1005 #define PCI_CONFIG_ADDRESS_EN 0x80000000
1006 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16
1007 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
1008 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11
1009 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
1010 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8
1011 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
1012 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0
1013 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
1020 * PCI Outbound Translation Register
1022 typedef struct pci_outbound_window {
1033 typedef struct ios83xx {
1035 #define POTAR_TA_MASK 0x000fffff
1036 #define POBAR_BA_MASK 0x000fffff
1037 #define POCMR_EN 0x80000000
1038 #define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */
1039 #define POCMR_SE 0x20000000 /* streaming enable */
1040 #define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2*/
1041 #define POCMR_CM_MASK 0x000fffff
1042 #define POCMR_CM_4G 0x00000000
1043 #define POCMR_CM_2G 0x00080000
1044 #define POCMR_CM_1G 0x000C0000
1045 #define POCMR_CM_512M 0x000E0000
1046 #define POCMR_CM_256M 0x000F0000
1047 #define POCMR_CM_128M 0x000F8000
1048 #define POCMR_CM_64M 0x000FC000
1049 #define POCMR_CM_32M 0x000FE000
1050 #define POCMR_CM_16M 0x000FF000
1051 #define POCMR_CM_8M 0x000FF800
1052 #define POCMR_CM_4M 0x000FFC00
1053 #define POCMR_CM_2M 0x000FFE00
1054 #define POCMR_CM_1M 0x000FFF00
1055 #define POCMR_CM_512K 0x000FFF80
1056 #define POCMR_CM_256K 0x000FFFC0
1057 #define POCMR_CM_128K 0x000FFFE0
1058 #define POCMR_CM_64K 0x000FFFF0
1059 #define POCMR_CM_32K 0x000FFFF8
1060 #define POCMR_CM_16K 0x000FFFFC
1061 #define POCMR_CM_8K 0x000FFFFE
1062 #define POCMR_CM_4K 0x000FFFFF
1071 * PCI Controller Control and Status Registers
1073 typedef struct pcictrl83xx {
1075 #define ESR_MERR 0x80000000
1076 #define ESR_APAR 0x00000400
1077 #define ESR_PCISERR 0x00000200
1078 #define ESR_MPERR 0x00000100
1079 #define ESR_TPERR 0x00000080
1080 #define ESR_NORSP 0x00000040
1081 #define ESR_TABT 0x00000020
1083 #define ECDR_APAR 0x00000400
1084 #define ECDR_PCISERR 0x00000200
1085 #define ECDR_MPERR 0x00000100
1086 #define ECDR_TPERR 0x00000080
1087 #define ECDR_NORSP 0x00000040
1088 #define ECDR_TABT 0x00000020
1090 #define EER_APAR 0x00000400
1091 #define EER_PCISERR 0x00000200
1092 #define EER_MPERR 0x00000100
1093 #define EER_TPERR 0x00000080
1094 #define EER_NORSP 0x00000040
1095 #define EER_TABT 0x00000020
1097 #define EATCR_ERRTYPR_MASK 0x70000000
1098 #define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */
1099 #define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */
1100 #define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */
1101 #define EATCR_ERRTYPR_MA 0x30000000 /* master abort */
1102 #define EATCR_ERRTYPR_TA 0x40000000 /* target abort */
1103 #define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */
1104 #define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */
1105 #define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */
1106 #define EATCR_BN_MASK 0x0f000000 /* beat number */
1107 #define EATCR_BN_1st 0x00000000
1108 #define EATCR_BN_2ed 0x01000000
1109 #define EATCR_BN_3rd 0x02000000
1110 #define EATCR_BN_4th 0x03000000
1111 #define EATCR_BN_5th 0x0400000
1112 #define EATCR_BN_6th 0x05000000
1113 #define EATCR_BN_7th 0x06000000
1114 #define EATCR_BN_8th 0x07000000
1115 #define EATCR_BN_9th 0x08000000
1116 #define EATCR_TS_MASK 0x00300000 /* transaction size */
1117 #define EATCR_TS_4 0x00000000
1118 #define EATCR_TS_1 0x00100000
1119 #define EATCR_TS_2 0x00200000
1120 #define EATCR_TS_3 0x00300000
1121 #define EATCR_ES_MASK 0x000f0000 /* error source */
1122 #define EATCR_ES_EM 0x00000000 /* external master */
1123 #define EATCR_ES_DMA 0x00050000
1124 #define EATCR_CMD_MASK 0x0000f000
1125 #define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable*/
1126 #define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */
1127 #define EATCR_HPB 0x00000004 /* high parity bit */
1128 #define EATCR_PB 0x00000002 /* parity bit*/
1129 #define EATCR_VI 0x00000001 /* error information valid */
1156 #define PITAR_TA_MASK 0x000fffff
1157 #define PIBAR_MASK 0xffffffff
1158 #define PIEBAR_EBA_MASK 0x000fffff
1159 #define PIWAR_EN 0x80000000
1160 #define PIWAR_PF 0x20000000
1161 #define PIWAR_RTT_MASK 0x000f0000
1162 #define PIWAR_RTT_NO_SNOOP 0x00040000
1163 #define PIWAR_RTT_SNOOP 0x00050000
1164 #define PIWAR_WTT_MASK 0x0000f000
1165 #define PIWAR_WTT_NO_SNOOP 0x00004000
1166 #define PIWAR_WTT_SNOOP 0x00005000
1167 #define PIWAR_IWS_MASK 0x0000003F
1168 #define PIWAR_IWS_4K 0x0000000B
1169 #define PIWAR_IWS_8K 0x0000000C
1170 #define PIWAR_IWS_16K 0x0000000D
1171 #define PIWAR_IWS_32K 0x0000000E
1172 #define PIWAR_IWS_64K 0x0000000F
1173 #define PIWAR_IWS_128K 0x00000010
1174 #define PIWAR_IWS_256K 0x00000011
1175 #define PIWAR_IWS_512K 0x00000012
1176 #define PIWAR_IWS_1M 0x00000013
1177 #define PIWAR_IWS_2M 0x00000014
1178 #define PIWAR_IWS_4M 0x00000015
1179 #define PIWAR_IWS_8M 0x00000016
1180 #define PIWAR_IWS_16M 0x00000017
1181 #define PIWAR_IWS_32M 0x00000018
1182 #define PIWAR_IWS_64M 0x00000019
1183 #define PIWAR_IWS_128M 0x0000001A
1184 #define PIWAR_IWS_256M 0x0000001B
1185 #define PIWAR_IWS_512M 0x0000001C
1186 #define PIWAR_IWS_1G 0x0000001D
1187 #define PIWAR_IWS_2G 0x0000001E
1193 typedef struct usb83xx {
1200 typedef struct tsec83xx {
1207 typedef struct security83xx {
1211 typedef struct immap {
1212 sysconf83xx_t sysconf; /* System configuration */
1213 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
1214 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
1215 rtclk83xx_t pit; /* Periodic Interval Timer */
1216 gtm83xx_t gtm[2]; /* Global Timers Module */
1217 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
1218 arbiter83xx_t arbiter; /* System Arbiter Registers */
1219 reset83xx_t reset; /* Reset Module */
1220 clk83xx_t clk; /* System Clock Module */
1221 pmc83xx_t pmc; /* Power Management Control Module */
1222 gpio83xx_t pgio[2]; /* general purpose I/O module */
1227 ddr83xx_t ddr; /* DDR Memory Controller Memory */
1228 i2c_t i2c[2]; /* I2C1 Controller */
1230 duart83xx_t duart[2];/* DUART */
1232 lbus83xx_t lbus; /* Local Bus Controller Registers */
1234 spi83xx_t spi; /* Serial Peripheral Interface */
1236 dma83xx_t dma; /* DMA */
1237 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
1238 ios83xx_t ios; /* Sequencer */
1239 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
1244 security83xx_t security;
1247 #endif /* __IMMAP_83xx__ */