2 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
4 * MPC83xx Internal Memory Map
7 * Dave Liu <daveliu@freescale.com>
8 * Tanya Jiang <tanya.jiang@freescale.com>
9 * Mandy Lavi <mandy.lavi@freescale.com>
10 * Eran Liberty <liberty@freescale.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #ifndef __IMMAP_83xx__
29 #define __IMMAP_83xx__
31 #include <asm/types.h>
32 #include <asm/fsl_i2c.h>
33 #include <asm/mpc8xxx_spi.h>
38 typedef struct law83xx {
39 u32 bar; /* LBIU local access window base address register */
40 u32 ar; /* LBIU local access window attribute register */
44 * System configuration registers
46 typedef struct sysconf83xx {
47 u32 immrbar; /* Internal memory map base address register */
49 u32 altcbar; /* Alternate configuration base address register */
51 law83xx_t lblaw[4]; /* LBIU local access window */
53 law83xx_t pcilaw[2]; /* PCI local access window */
55 law83xx_t ddrlaw[2]; /* DDR local access window */
57 u32 sgprl; /* System General Purpose Register Low */
58 u32 sgprh; /* System General Purpose Register High */
59 u32 spridr; /* System Part and Revision ID Register */
61 u32 spcr; /* System Priority Configuration Register */
62 u32 sicrl; /* System I/O Configuration Register Low */
63 u32 sicrh; /* System I/O Configuration Register High */
65 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
66 u32 sidcr1; /* System I/O Delay Configuration Register 1 */
67 u32 ddrcdr; /* DDR Control Driver Register */
68 u32 ddrdsr; /* DDR Debug Status Register */
69 u32 obir; /* Output Buffer Impedance Register */
74 * Watch Dog Timer (WDT) Registers
76 typedef struct wdt83xx {
78 u32 swcrr; /* System watchdog control register */
79 u32 swcnr; /* System watchdog count register */
81 u16 swsrr; /* System watchdog service register */
86 * RTC/PIT Module Registers
88 typedef struct rtclk83xx {
89 u32 cnr; /* control register */
90 u32 ldr; /* load register */
91 u32 psr; /* prescale register */
92 u32 ctr; /* counter value field register */
93 u32 evr; /* event register */
94 u32 alr; /* alarm register */
101 typedef struct gtm83xx {
102 u8 cfr1; /* Timer1/2 Configuration */
104 u8 cfr2; /* Timer3/4 Configuration */
106 u16 mdr1; /* Timer1 Mode Register */
107 u16 mdr2; /* Timer2 Mode Register */
108 u16 rfr1; /* Timer1 Reference Register */
109 u16 rfr2; /* Timer2 Reference Register */
110 u16 cpr1; /* Timer1 Capture Register */
111 u16 cpr2; /* Timer2 Capture Register */
112 u16 cnr1; /* Timer1 Counter Register */
113 u16 cnr2; /* Timer2 Counter Register */
114 u16 mdr3; /* Timer3 Mode Register */
115 u16 mdr4; /* Timer4 Mode Register */
116 u16 rfr3; /* Timer3 Reference Register */
117 u16 rfr4; /* Timer4 Reference Register */
118 u16 cpr3; /* Timer3 Capture Register */
119 u16 cpr4; /* Timer4 Capture Register */
120 u16 cnr3; /* Timer3 Counter Register */
121 u16 cnr4; /* Timer4 Counter Register */
122 u16 evr1; /* Timer1 Event Register */
123 u16 evr2; /* Timer2 Event Register */
124 u16 evr3; /* Timer3 Event Register */
125 u16 evr4; /* Timer4 Event Register */
126 u16 psr1; /* Timer1 Prescaler Register */
127 u16 psr2; /* Timer2 Prescaler Register */
128 u16 psr3; /* Timer3 Prescaler Register */
129 u16 psr4; /* Timer4 Prescaler Register */
134 * Integrated Programmable Interrupt Controller
136 typedef struct ipic83xx {
137 u32 sicfr; /* System Global Interrupt Configuration Register */
138 u32 sivcr; /* System Global Interrupt Vector Register */
139 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
140 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
141 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
143 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
144 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
145 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
147 u32 sepnr; /* System External Interrupt Pending Register */
148 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
149 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
150 u32 semsr; /* System External Interrupt Mask Register */
151 u32 secnr; /* System External Interrupt Control Register */
152 u32 sersr; /* System Error Status Register */
153 u32 sermr; /* System Error Mask Register */
154 u32 sercr; /* System Error Control Register */
156 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
157 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
158 u32 sefcr; /* System External Interrupt Force Register */
159 u32 serfr; /* System Error Force Register */
160 u32 scvcr; /* System Critical Interrupt Vector Register */
161 u32 smvcr; /* System Management Interrupt Vector Register */
166 * System Arbiter Registers
168 typedef struct arbiter83xx {
169 u32 acr; /* Arbiter Configuration Register */
170 u32 atr; /* Arbiter Timers Register */
172 u32 aer; /* Arbiter Event Register */
173 u32 aidr; /* Arbiter Interrupt Definition Register */
174 u32 amr; /* Arbiter Mask Register */
175 u32 aeatr; /* Arbiter Event Attributes Register */
176 u32 aeadr; /* Arbiter Event Address Register */
177 u32 aerr; /* Arbiter Event Response Register */
184 typedef struct reset83xx {
185 u32 rcwl; /* Reset Configuration Word Low Register */
186 u32 rcwh; /* Reset Configuration Word High Register */
188 u32 rsr; /* Reset Status Register */
189 u32 rmr; /* Reset Mode Register */
190 u32 rpr; /* Reset protection Register */
191 u32 rcr; /* Reset Control Register */
192 u32 rcer; /* Reset Control Enable Register */
199 typedef struct clk83xx {
200 u32 spmr; /* system PLL mode Register */
201 u32 occr; /* output clock control Register */
202 u32 sccr; /* system clock control Register */
207 * Power Management Control Module
209 typedef struct pmc83xx {
210 u32 pmccr; /* PMC Configuration Register */
211 u32 pmcer; /* PMC Event Register */
212 u32 pmcmr; /* PMC Mask Register */
213 u32 pmccr1; /* PMC Configuration Register 1 */
214 u32 pmccr2; /* PMC Configuration Register 2 */
219 * General purpose I/O module
221 typedef struct gpio83xx {
222 u32 dir; /* direction register */
223 u32 odr; /* open drain register */
224 u32 dat; /* data register */
225 u32 ier; /* interrupt event register */
226 u32 imr; /* interrupt mask register */
227 u32 icr; /* external interrupt control register */
232 * QE Ports Interrupts Registers
234 typedef struct qepi83xx {
236 u32 qepier; /* QE Ports Interrupt Event Register */
237 u32 qepimr; /* QE Ports Interrupt Mask Register */
238 u32 qepicr; /* QE Ports Interrupt Control Register */
243 * QE Parallel I/O Ports
245 typedef struct gpio_n {
246 u32 podr; /* Open Drain Register */
247 u32 pdat; /* Data Register */
248 u32 dir1; /* direction register 1 */
249 u32 dir2; /* direction register 2 */
250 u32 ppar1; /* Pin Assignment Register 1 */
251 u32 ppar2; /* Pin Assignment Register 2 */
254 typedef struct qegpio83xx {
255 gpio_n_t ioport[0x7];
260 * QE Secondary Bus Access Windows
262 typedef struct qesba83xx {
263 u32 lbmcsar; /* Local bus memory controller start address */
264 u32 sdmcsar; /* Secondary DDR memory controller start address */
266 u32 lbmcear; /* Local bus memory controller end address */
267 u32 sdmcear; /* Secondary DDR memory controller end address */
269 u32 lbmcar; /* Local bus memory controller attributes */
270 u32 sdmcar; /* Secondary DDR memory controller attributes */
275 * DDR Memory Controller Memory Map
277 typedef struct ddr_cs_bnds {
282 typedef struct ddr83xx {
283 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
285 u32 cs_config[4]; /* Chip Select x Configuration */
287 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
288 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
289 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
290 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
291 u32 sdram_cfg; /* SDRAM Control Configuration */
292 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
293 u32 sdram_mode; /* SDRAM Mode Configuration */
294 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
295 u32 sdram_md_cntl; /* SDRAM Mode Control */
296 u32 sdram_interval; /* SDRAM Interval Configuration */
297 u32 ddr_data_init; /* SDRAM Data Initialization */
299 u32 sdram_clk_cntl; /* SDRAM Clock Control */
301 u32 ddr_init_addr; /* DDR training initialization address */
302 u32 ddr_init_ext_addr; /* DDR training initialization extended address */
304 u32 ddr_ip_rev1; /* DDR IP block revision 1 */
305 u32 ddr_ip_rev2; /* DDR IP block revision 2 */
307 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
308 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
309 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
311 u32 capture_data_hi; /* Memory Data Path Read Capture High */
312 u32 capture_data_lo; /* Memory Data Path Read Capture Low */
313 u32 capture_ecc; /* Memory Data Path Read Capture ECC */
315 u32 err_detect; /* Memory Error Detect */
316 u32 err_disable; /* Memory Error Disable */
317 u32 err_int_en; /* Memory Error Interrupt Enable */
318 u32 capture_attributes; /* Memory Error Attributes Capture */
319 u32 capture_address; /* Memory Error Address Capture */
320 u32 capture_ext_address;/* Memory Error Extended Address Capture */
321 u32 err_sbe; /* Memory Single-Bit ECC Error Management */
330 typedef struct duart83xx {
331 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
332 u8 uier_udmb; /* combined register for UIER and UDMB */
333 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
334 u8 ulcr; /* line control register */
335 u8 umcr; /* MODEM control register */
336 u8 ulsr; /* line status register */
337 u8 umsr; /* MODEM status register */
338 u8 uscr; /* scratch register */
340 u8 udsr; /* DMA status register */
346 * Local Bus Controller Registers
348 typedef struct lbus_bank {
349 u32 br; /* Base Register */
350 u32 or; /* Option Register */
353 typedef struct lbus83xx {
356 u32 mar; /* UPM Address Register */
358 u32 mamr; /* UPMA Mode Register */
359 u32 mbmr; /* UPMB Mode Register */
360 u32 mcmr; /* UPMC Mode Register */
362 u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
363 u32 mdr; /* UPM Data Register */
365 u32 lsor; /* Special Operation Initiation Register */
366 u32 lsdmr; /* SDRAM Mode Register */
368 u32 lurt; /* UPM Refresh Timer */
369 u32 lsrt; /* SDRAM Refresh Timer */
371 u32 ltesr; /* Transfer Error Status Register */
372 u32 ltedr; /* Transfer Error Disable Register */
373 u32 lteir; /* Transfer Error Interrupt Register */
374 u32 lteatr; /* Transfer Error Attributes Register */
375 u32 ltear; /* Transfer Error Address Register */
377 u32 lbcr; /* Configuration Register */
378 u32 lcrr; /* Clock Ratio Register */
380 u32 fmr; /* Flash Mode Register */
381 u32 fir; /* Flash Instruction Register */
382 u32 fcr; /* Flash Command Register */
383 u32 fbar; /* Flash Block Addr Register */
384 u32 fpar; /* Flash Page Addr Register */
385 u32 fbcr; /* Flash Byte Count Register */
392 typedef struct dma83xx {
393 u32 res0[0xC]; /* 0x0-0x29 reseverd */
394 u32 omisr; /* 0x30 Outbound message interrupt status register */
395 u32 omimr; /* 0x34 Outbound message interrupt mask register */
396 u32 res1[0x6]; /* 0x38-0x49 reserved */
397 u32 imr0; /* 0x50 Inbound message register 0 */
398 u32 imr1; /* 0x54 Inbound message register 1 */
399 u32 omr0; /* 0x58 Outbound message register 0 */
400 u32 omr1; /* 0x5C Outbound message register 1 */
401 u32 odr; /* 0x60 Outbound doorbell register */
402 u32 res2; /* 0x64-0x67 reserved */
403 u32 idr; /* 0x68 Inbound doorbell register */
404 u32 res3[0x5]; /* 0x6C-0x79 reserved */
405 u32 imisr; /* 0x80 Inbound message interrupt status register */
406 u32 imimr; /* 0x84 Inbound message interrupt mask register */
407 u32 res4[0x1E]; /* 0x88-0x99 reserved */
408 u32 dmamr0; /* 0x100 DMA 0 mode register */
409 u32 dmasr0; /* 0x104 DMA 0 status register */
410 u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */
411 u32 res5; /* 0x10C reserved */
412 u32 dmasar0; /* 0x110 DMA 0 source address register */
413 u32 res6; /* 0x114 reserved */
414 u32 dmadar0; /* 0x118 DMA 0 destination address register */
415 u32 res7; /* 0x11C reserved */
416 u32 dmabcr0; /* 0x120 DMA 0 byte count register */
417 u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */
418 u32 res8[0x16]; /* 0x128-0x179 reserved */
419 u32 dmamr1; /* 0x180 DMA 1 mode register */
420 u32 dmasr1; /* 0x184 DMA 1 status register */
421 u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */
422 u32 res9; /* 0x18C reserved */
423 u32 dmasar1; /* 0x190 DMA 1 source address register */
424 u32 res10; /* 0x194 reserved */
425 u32 dmadar1; /* 0x198 DMA 1 destination address register */
426 u32 res11; /* 0x19C reserved */
427 u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */
428 u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */
429 u32 res12[0x16]; /* 0x1A8-0x199 reserved */
430 u32 dmamr2; /* 0x200 DMA 2 mode register */
431 u32 dmasr2; /* 0x204 DMA 2 status register */
432 u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */
433 u32 res13; /* 0x20C reserved */
434 u32 dmasar2; /* 0x210 DMA 2 source address register */
435 u32 res14; /* 0x214 reserved */
436 u32 dmadar2; /* 0x218 DMA 2 destination address register */
437 u32 res15; /* 0x21C reserved */
438 u32 dmabcr2; /* 0x220 DMA 2 byte count register */
439 u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */
440 u32 res16[0x16]; /* 0x228-0x279 reserved */
441 u32 dmamr3; /* 0x280 DMA 3 mode register */
442 u32 dmasr3; /* 0x284 DMA 3 status register */
443 u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */
444 u32 res17; /* 0x28C reserved */
445 u32 dmasar3; /* 0x290 DMA 3 source address register */
446 u32 res18; /* 0x294 reserved */
447 u32 dmadar3; /* 0x298 DMA 3 destination address register */
448 u32 res19; /* 0x29C reserved */
449 u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */
450 u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */
451 u32 dmagsr; /* 0x2A8 DMA general status register */
452 u32 res20[0x15]; /* 0x2AC-0x2FF reserved */
456 * PCI Software Configuration Registers
458 typedef struct pciconf83xx {
466 * PCI Outbound Translation Register
468 typedef struct pci_outbound_window {
480 typedef struct ios83xx {
490 * PCI Controller Control and Status Registers
492 typedef struct pcictrl83xx {
528 typedef struct usb83xx {
535 typedef struct tsec83xx {
542 typedef struct security83xx {
549 typedef struct pex83xx {
556 typedef struct sata83xx {
563 typedef struct sdhc83xx {
570 typedef struct serdes83xx {
577 typedef struct rom83xx {
584 typedef struct tdm83xx {
591 typedef struct tdmdmac83xx {
595 #if defined(CONFIG_MPC834X)
596 typedef struct immap {
597 sysconf83xx_t sysconf; /* System configuration */
598 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
599 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
600 rtclk83xx_t pit; /* Periodic Interval Timer */
601 gtm83xx_t gtm[2]; /* Global Timers Module */
602 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
603 arbiter83xx_t arbiter; /* System Arbiter Registers */
604 reset83xx_t reset; /* Reset Module */
605 clk83xx_t clk; /* System Clock Module */
606 pmc83xx_t pmc; /* Power Management Control Module */
607 gpio83xx_t gpio[2]; /* General purpose I/O module */
612 ddr83xx_t ddr; /* DDR Memory Controller Memory */
613 fsl_i2c_t i2c[2]; /* I2C Controllers */
615 duart83xx_t duart[2]; /* DUART */
617 lbus83xx_t lbus; /* Local Bus Controller Registers */
619 spi8xxx_t spi; /* Serial Peripheral Interface */
620 dma83xx_t dma; /* DMA */
621 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
622 ios83xx_t ios; /* Sequencer */
623 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
628 security83xx_t security;
632 #elif defined(CONFIG_MPC8313)
633 typedef struct immap {
634 sysconf83xx_t sysconf; /* System configuration */
635 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
636 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
637 rtclk83xx_t pit; /* Periodic Interval Timer */
638 gtm83xx_t gtm[2]; /* Global Timers Module */
639 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
640 arbiter83xx_t arbiter; /* System Arbiter Registers */
641 reset83xx_t reset; /* Reset Module */
642 clk83xx_t clk; /* System Clock Module */
643 pmc83xx_t pmc; /* Power Management Control Module */
644 gpio83xx_t gpio[1]; /* General purpose I/O module */
646 ddr83xx_t ddr; /* DDR Memory Controller Memory */
647 fsl_i2c_t i2c[2]; /* I2C Controllers */
649 duart83xx_t duart[2]; /* DUART */
651 lbus83xx_t lbus; /* Local Bus Controller Registers */
653 spi8xxx_t spi; /* Serial Peripheral Interface */
654 dma83xx_t dma; /* DMA */
655 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
657 ios83xx_t ios; /* Sequencer */
658 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
663 security83xx_t security;
667 #elif defined(CONFIG_MPC8315)
668 typedef struct immap {
669 sysconf83xx_t sysconf; /* System configuration */
670 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
671 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
672 rtclk83xx_t pit; /* Periodic Interval Timer */
673 gtm83xx_t gtm[2]; /* Global Timers Module */
674 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
675 arbiter83xx_t arbiter; /* System Arbiter Registers */
676 reset83xx_t reset; /* Reset Module */
677 clk83xx_t clk; /* System Clock Module */
678 pmc83xx_t pmc; /* Power Management Control Module */
679 gpio83xx_t gpio[1]; /* General purpose I/O module */
681 ddr83xx_t ddr; /* DDR Memory Controller Memory */
682 fsl_i2c_t i2c[2]; /* I2C Controllers */
684 duart83xx_t duart[2]; /* DUART */
686 lbus83xx_t lbus; /* Local Bus Controller Registers */
688 spi8xxx_t spi; /* Serial Peripheral Interface */
689 dma83xx_t dma; /* DMA */
690 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
692 ios83xx_t ios; /* Sequencer */
693 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
695 pex83xx_t pciexp[2]; /* PCI Express Controller */
697 tdm83xx_t tdm; /* TDM Controller */
699 sata83xx_t sata[2]; /* SATA Controller */
701 usb83xx_t usb[1]; /* USB DR Controller */
704 tdmdmac83xx_t tdmdmac; /* TDM DMAC */
706 security83xx_t security;
708 serdes83xx_t serdes[1]; /* SerDes Registers */
712 #elif defined(CONFIG_MPC837X)
713 typedef struct immap {
714 sysconf83xx_t sysconf; /* System configuration */
715 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
716 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
717 rtclk83xx_t pit; /* Periodic Interval Timer */
718 gtm83xx_t gtm[2]; /* Global Timers Module */
719 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
720 arbiter83xx_t arbiter; /* System Arbiter Registers */
721 reset83xx_t reset; /* Reset Module */
722 clk83xx_t clk; /* System Clock Module */
723 pmc83xx_t pmc; /* Power Management Control Module */
724 gpio83xx_t gpio[2]; /* General purpose I/O module */
726 ddr83xx_t ddr; /* DDR Memory Controller Memory */
727 fsl_i2c_t i2c[2]; /* I2C Controllers */
729 duart83xx_t duart[2]; /* DUART */
731 lbus83xx_t lbus; /* Local Bus Controller Registers */
733 spi8xxx_t spi; /* Serial Peripheral Interface */
734 dma83xx_t dma; /* DMA */
735 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
737 ios83xx_t ios; /* Sequencer */
738 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
740 pex83xx_t pciexp[2]; /* PCI Express Controller */
742 sata83xx_t sata[4]; /* SATA Controller */
744 usb83xx_t usb[1]; /* USB DR Controller */
747 sdhc83xx_t sdhc; /* SDHC Controller */
749 security83xx_t security;
751 serdes83xx_t serdes[2]; /* SerDes Registers */
753 rom83xx_t rom; /* On Chip ROM */
756 #elif defined(CONFIG_MPC8360)
757 typedef struct immap {
758 sysconf83xx_t sysconf; /* System configuration */
759 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
760 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
761 rtclk83xx_t pit; /* Periodic Interval Timer */
763 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
764 arbiter83xx_t arbiter; /* System Arbiter Registers */
765 reset83xx_t reset; /* Reset Module */
766 clk83xx_t clk; /* System Clock Module */
767 pmc83xx_t pmc; /* Power Management Control Module */
768 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
773 qepio83xx_t qepio; /* QE Parallel I/O ports */
774 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
776 ddr83xx_t ddr; /* DDR Memory Controller Memory */
777 fsl_i2c_t i2c[2]; /* I2C Controllers */
779 duart83xx_t duart[2]; /* DUART */
781 lbus83xx_t lbus; /* Local Bus Controller Registers */
783 dma83xx_t dma; /* DMA */
784 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
786 ios83xx_t ios; /* Sequencer (IOS) */
787 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
789 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
791 security83xx_t security;
793 u8 qe[0x100000]; /* QE block */
796 #elif defined(CONFIG_MPC832X)
797 typedef struct immap {
798 sysconf83xx_t sysconf; /* System configuration */
799 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
800 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
801 rtclk83xx_t pit; /* Periodic Interval Timer */
802 gtm83xx_t gtm[2]; /* Global Timers Module */
803 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
804 arbiter83xx_t arbiter; /* System Arbiter Registers */
805 reset83xx_t reset; /* Reset Module */
806 clk83xx_t clk; /* System Clock Module */
807 pmc83xx_t pmc; /* Power Management Control Module */
808 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
813 qepio83xx_t qepio; /* QE Parallel I/O ports */
815 ddr83xx_t ddr; /* DDR Memory Controller Memory */
816 fsl_i2c_t i2c[2]; /* I2C Controllers */
818 duart83xx_t duart[2]; /* DUART */
820 lbus83xx_t lbus; /* Local Bus Controller Registers */
822 dma83xx_t dma; /* DMA */
823 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
825 ios83xx_t ios; /* Sequencer (IOS) */
826 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
828 security83xx_t security;
830 u8 qe[0x100000]; /* QE block */
834 #endif /* __IMMAP_83xx__ */