2 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
4 * MPC83xx Internal Memory Map
7 * Dave Liu <daveliu@freescale.com>
8 * Tanya Jiang <tanya.jiang@freescale.com>
9 * Mandy Lavi <mandy.lavi@freescale.com>
10 * Eran Liberty <liberty@freescale.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #ifndef __IMMAP_83xx__
29 #define __IMMAP_83xx__
31 #include <asm/types.h>
32 #include <asm/fsl_i2c.h>
33 #include <asm/mpc8xxx_spi.h>
34 #include <asm/fsl_lbc.h>
39 typedef struct law83xx {
40 u32 bar; /* LBIU local access window base address register */
41 u32 ar; /* LBIU local access window attribute register */
45 * System configuration registers
47 typedef struct sysconf83xx {
48 u32 immrbar; /* Internal memory map base address register */
50 u32 altcbar; /* Alternate configuration base address register */
52 law83xx_t lblaw[4]; /* LBIU local access window */
54 law83xx_t pcilaw[2]; /* PCI local access window */
56 law83xx_t ddrlaw[2]; /* DDR local access window */
58 u32 sgprl; /* System General Purpose Register Low */
59 u32 sgprh; /* System General Purpose Register High */
60 u32 spridr; /* System Part and Revision ID Register */
62 u32 spcr; /* System Priority Configuration Register */
63 u32 sicrl; /* System I/O Configuration Register Low */
64 u32 sicrh; /* System I/O Configuration Register High */
66 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
67 u32 sidcr1; /* System I/O Delay Configuration Register 1 */
68 u32 ddrcdr; /* DDR Control Driver Register */
69 u32 ddrdsr; /* DDR Debug Status Register */
70 u32 obir; /* Output Buffer Impedance Register */
75 * Watch Dog Timer (WDT) Registers
77 typedef struct wdt83xx {
79 u32 swcrr; /* System watchdog control register */
80 u32 swcnr; /* System watchdog count register */
82 u16 swsrr; /* System watchdog service register */
87 * RTC/PIT Module Registers
89 typedef struct rtclk83xx {
90 u32 cnr; /* control register */
91 u32 ldr; /* load register */
92 u32 psr; /* prescale register */
93 u32 ctr; /* counter value field register */
94 u32 evr; /* event register */
95 u32 alr; /* alarm register */
100 * Global timer module
102 typedef struct gtm83xx {
103 u8 cfr1; /* Timer1/2 Configuration */
105 u8 cfr2; /* Timer3/4 Configuration */
107 u16 mdr1; /* Timer1 Mode Register */
108 u16 mdr2; /* Timer2 Mode Register */
109 u16 rfr1; /* Timer1 Reference Register */
110 u16 rfr2; /* Timer2 Reference Register */
111 u16 cpr1; /* Timer1 Capture Register */
112 u16 cpr2; /* Timer2 Capture Register */
113 u16 cnr1; /* Timer1 Counter Register */
114 u16 cnr2; /* Timer2 Counter Register */
115 u16 mdr3; /* Timer3 Mode Register */
116 u16 mdr4; /* Timer4 Mode Register */
117 u16 rfr3; /* Timer3 Reference Register */
118 u16 rfr4; /* Timer4 Reference Register */
119 u16 cpr3; /* Timer3 Capture Register */
120 u16 cpr4; /* Timer4 Capture Register */
121 u16 cnr3; /* Timer3 Counter Register */
122 u16 cnr4; /* Timer4 Counter Register */
123 u16 evr1; /* Timer1 Event Register */
124 u16 evr2; /* Timer2 Event Register */
125 u16 evr3; /* Timer3 Event Register */
126 u16 evr4; /* Timer4 Event Register */
127 u16 psr1; /* Timer1 Prescaler Register */
128 u16 psr2; /* Timer2 Prescaler Register */
129 u16 psr3; /* Timer3 Prescaler Register */
130 u16 psr4; /* Timer4 Prescaler Register */
135 * Integrated Programmable Interrupt Controller
137 typedef struct ipic83xx {
138 u32 sicfr; /* System Global Interrupt Configuration Register */
139 u32 sivcr; /* System Global Interrupt Vector Register */
140 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
141 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
142 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
144 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
145 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
146 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
148 u32 sepnr; /* System External Interrupt Pending Register */
149 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
150 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
151 u32 semsr; /* System External Interrupt Mask Register */
152 u32 secnr; /* System External Interrupt Control Register */
153 u32 sersr; /* System Error Status Register */
154 u32 sermr; /* System Error Mask Register */
155 u32 sercr; /* System Error Control Register */
157 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
158 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
159 u32 sefcr; /* System External Interrupt Force Register */
160 u32 serfr; /* System Error Force Register */
161 u32 scvcr; /* System Critical Interrupt Vector Register */
162 u32 smvcr; /* System Management Interrupt Vector Register */
167 * System Arbiter Registers
169 typedef struct arbiter83xx {
170 u32 acr; /* Arbiter Configuration Register */
171 u32 atr; /* Arbiter Timers Register */
173 u32 aer; /* Arbiter Event Register */
174 u32 aidr; /* Arbiter Interrupt Definition Register */
175 u32 amr; /* Arbiter Mask Register */
176 u32 aeatr; /* Arbiter Event Attributes Register */
177 u32 aeadr; /* Arbiter Event Address Register */
178 u32 aerr; /* Arbiter Event Response Register */
185 typedef struct reset83xx {
186 u32 rcwl; /* Reset Configuration Word Low Register */
187 u32 rcwh; /* Reset Configuration Word High Register */
189 u32 rsr; /* Reset Status Register */
190 u32 rmr; /* Reset Mode Register */
191 u32 rpr; /* Reset protection Register */
192 u32 rcr; /* Reset Control Register */
193 u32 rcer; /* Reset Control Enable Register */
200 typedef struct clk83xx {
201 u32 spmr; /* system PLL mode Register */
202 u32 occr; /* output clock control Register */
203 u32 sccr; /* system clock control Register */
208 * Power Management Control Module
210 typedef struct pmc83xx {
211 u32 pmccr; /* PMC Configuration Register */
212 u32 pmcer; /* PMC Event Register */
213 u32 pmcmr; /* PMC Mask Register */
214 u32 pmccr1; /* PMC Configuration Register 1 */
215 u32 pmccr2; /* PMC Configuration Register 2 */
220 * General purpose I/O module
222 typedef struct gpio83xx {
223 u32 dir; /* direction register */
224 u32 odr; /* open drain register */
225 u32 dat; /* data register */
226 u32 ier; /* interrupt event register */
227 u32 imr; /* interrupt mask register */
228 u32 icr; /* external interrupt control register */
233 * QE Ports Interrupts Registers
235 typedef struct qepi83xx {
237 u32 qepier; /* QE Ports Interrupt Event Register */
238 u32 qepimr; /* QE Ports Interrupt Mask Register */
239 u32 qepicr; /* QE Ports Interrupt Control Register */
244 * QE Parallel I/O Ports
246 typedef struct gpio_n {
247 u32 podr; /* Open Drain Register */
248 u32 pdat; /* Data Register */
249 u32 dir1; /* direction register 1 */
250 u32 dir2; /* direction register 2 */
251 u32 ppar1; /* Pin Assignment Register 1 */
252 u32 ppar2; /* Pin Assignment Register 2 */
255 typedef struct qegpio83xx {
256 gpio_n_t ioport[0x7];
261 * QE Secondary Bus Access Windows
263 typedef struct qesba83xx {
264 u32 lbmcsar; /* Local bus memory controller start address */
265 u32 sdmcsar; /* Secondary DDR memory controller start address */
267 u32 lbmcear; /* Local bus memory controller end address */
268 u32 sdmcear; /* Secondary DDR memory controller end address */
270 u32 lbmcar; /* Local bus memory controller attributes */
271 u32 sdmcar; /* Secondary DDR memory controller attributes */
276 * DDR Memory Controller Memory Map
278 typedef struct ddr_cs_bnds {
283 typedef struct ddr83xx {
284 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
286 u32 cs_config[4]; /* Chip Select x Configuration */
288 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
289 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
290 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
291 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
292 u32 sdram_cfg; /* SDRAM Control Configuration */
293 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
294 u32 sdram_mode; /* SDRAM Mode Configuration */
295 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
296 u32 sdram_md_cntl; /* SDRAM Mode Control */
297 u32 sdram_interval; /* SDRAM Interval Configuration */
298 u32 ddr_data_init; /* SDRAM Data Initialization */
300 u32 sdram_clk_cntl; /* SDRAM Clock Control */
302 u32 ddr_init_addr; /* DDR training initialization address */
303 u32 ddr_init_ext_addr; /* DDR training initialization extended address */
305 u32 ddr_ip_rev1; /* DDR IP block revision 1 */
306 u32 ddr_ip_rev2; /* DDR IP block revision 2 */
308 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
309 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
310 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
312 u32 capture_data_hi; /* Memory Data Path Read Capture High */
313 u32 capture_data_lo; /* Memory Data Path Read Capture Low */
314 u32 capture_ecc; /* Memory Data Path Read Capture ECC */
316 u32 err_detect; /* Memory Error Detect */
317 u32 err_disable; /* Memory Error Disable */
318 u32 err_int_en; /* Memory Error Interrupt Enable */
319 u32 capture_attributes; /* Memory Error Attributes Capture */
320 u32 capture_address; /* Memory Error Address Capture */
321 u32 capture_ext_address;/* Memory Error Extended Address Capture */
322 u32 err_sbe; /* Memory Single-Bit ECC Error Management */
331 typedef struct duart83xx {
332 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
333 u8 uier_udmb; /* combined register for UIER and UDMB */
334 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
335 u8 ulcr; /* line control register */
336 u8 umcr; /* MODEM control register */
337 u8 ulsr; /* line status register */
338 u8 umsr; /* MODEM status register */
339 u8 uscr; /* scratch register */
341 u8 udsr; /* DMA status register */
349 typedef struct dma83xx {
350 u32 res0[0xC]; /* 0x0-0x29 reseverd */
351 u32 omisr; /* 0x30 Outbound message interrupt status register */
352 u32 omimr; /* 0x34 Outbound message interrupt mask register */
353 u32 res1[0x6]; /* 0x38-0x49 reserved */
354 u32 imr0; /* 0x50 Inbound message register 0 */
355 u32 imr1; /* 0x54 Inbound message register 1 */
356 u32 omr0; /* 0x58 Outbound message register 0 */
357 u32 omr1; /* 0x5C Outbound message register 1 */
358 u32 odr; /* 0x60 Outbound doorbell register */
359 u32 res2; /* 0x64-0x67 reserved */
360 u32 idr; /* 0x68 Inbound doorbell register */
361 u32 res3[0x5]; /* 0x6C-0x79 reserved */
362 u32 imisr; /* 0x80 Inbound message interrupt status register */
363 u32 imimr; /* 0x84 Inbound message interrupt mask register */
364 u32 res4[0x1E]; /* 0x88-0x99 reserved */
365 u32 dmamr0; /* 0x100 DMA 0 mode register */
366 u32 dmasr0; /* 0x104 DMA 0 status register */
367 u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */
368 u32 res5; /* 0x10C reserved */
369 u32 dmasar0; /* 0x110 DMA 0 source address register */
370 u32 res6; /* 0x114 reserved */
371 u32 dmadar0; /* 0x118 DMA 0 destination address register */
372 u32 res7; /* 0x11C reserved */
373 u32 dmabcr0; /* 0x120 DMA 0 byte count register */
374 u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */
375 u32 res8[0x16]; /* 0x128-0x179 reserved */
376 u32 dmamr1; /* 0x180 DMA 1 mode register */
377 u32 dmasr1; /* 0x184 DMA 1 status register */
378 u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */
379 u32 res9; /* 0x18C reserved */
380 u32 dmasar1; /* 0x190 DMA 1 source address register */
381 u32 res10; /* 0x194 reserved */
382 u32 dmadar1; /* 0x198 DMA 1 destination address register */
383 u32 res11; /* 0x19C reserved */
384 u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */
385 u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */
386 u32 res12[0x16]; /* 0x1A8-0x199 reserved */
387 u32 dmamr2; /* 0x200 DMA 2 mode register */
388 u32 dmasr2; /* 0x204 DMA 2 status register */
389 u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */
390 u32 res13; /* 0x20C reserved */
391 u32 dmasar2; /* 0x210 DMA 2 source address register */
392 u32 res14; /* 0x214 reserved */
393 u32 dmadar2; /* 0x218 DMA 2 destination address register */
394 u32 res15; /* 0x21C reserved */
395 u32 dmabcr2; /* 0x220 DMA 2 byte count register */
396 u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */
397 u32 res16[0x16]; /* 0x228-0x279 reserved */
398 u32 dmamr3; /* 0x280 DMA 3 mode register */
399 u32 dmasr3; /* 0x284 DMA 3 status register */
400 u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */
401 u32 res17; /* 0x28C reserved */
402 u32 dmasar3; /* 0x290 DMA 3 source address register */
403 u32 res18; /* 0x294 reserved */
404 u32 dmadar3; /* 0x298 DMA 3 destination address register */
405 u32 res19; /* 0x29C reserved */
406 u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */
407 u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */
408 u32 dmagsr; /* 0x2A8 DMA general status register */
409 u32 res20[0x15]; /* 0x2AC-0x2FF reserved */
413 * PCI Software Configuration Registers
415 typedef struct pciconf83xx {
423 * PCI Outbound Translation Register
425 typedef struct pci_outbound_window {
437 typedef struct ios83xx {
447 * PCI Controller Control and Status Registers
449 typedef struct pcictrl83xx {
485 typedef struct usb83xx {
492 typedef struct tsec83xx {
499 typedef struct security83xx {
506 typedef struct pex83xx {
513 typedef struct sata83xx {
520 typedef struct sdhc83xx {
527 typedef struct serdes83xx {
534 typedef struct rom83xx {
541 typedef struct tdm83xx {
548 typedef struct tdmdmac83xx {
552 #if defined(CONFIG_MPC834X)
553 typedef struct immap {
554 sysconf83xx_t sysconf; /* System configuration */
555 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
556 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
557 rtclk83xx_t pit; /* Periodic Interval Timer */
558 gtm83xx_t gtm[2]; /* Global Timers Module */
559 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
560 arbiter83xx_t arbiter; /* System Arbiter Registers */
561 reset83xx_t reset; /* Reset Module */
562 clk83xx_t clk; /* System Clock Module */
563 pmc83xx_t pmc; /* Power Management Control Module */
564 gpio83xx_t gpio[2]; /* General purpose I/O module */
569 ddr83xx_t ddr; /* DDR Memory Controller Memory */
570 fsl_i2c_t i2c[2]; /* I2C Controllers */
572 duart83xx_t duart[2]; /* DUART */
574 fsl_lbus_t lbus; /* Local Bus Controller Registers */
576 spi8xxx_t spi; /* Serial Peripheral Interface */
577 dma83xx_t dma; /* DMA */
578 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
579 ios83xx_t ios; /* Sequencer */
580 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
585 security83xx_t security;
589 #elif defined(CONFIG_MPC8313)
590 typedef struct immap {
591 sysconf83xx_t sysconf; /* System configuration */
592 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
593 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
594 rtclk83xx_t pit; /* Periodic Interval Timer */
595 gtm83xx_t gtm[2]; /* Global Timers Module */
596 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
597 arbiter83xx_t arbiter; /* System Arbiter Registers */
598 reset83xx_t reset; /* Reset Module */
599 clk83xx_t clk; /* System Clock Module */
600 pmc83xx_t pmc; /* Power Management Control Module */
601 gpio83xx_t gpio[1]; /* General purpose I/O module */
603 ddr83xx_t ddr; /* DDR Memory Controller Memory */
604 fsl_i2c_t i2c[2]; /* I2C Controllers */
606 duart83xx_t duart[2]; /* DUART */
608 fsl_lbus_t lbus; /* Local Bus Controller Registers */
610 spi8xxx_t spi; /* Serial Peripheral Interface */
611 dma83xx_t dma; /* DMA */
612 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
614 ios83xx_t ios; /* Sequencer */
615 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
620 security83xx_t security;
624 #elif defined(CONFIG_MPC8315)
625 typedef struct immap {
626 sysconf83xx_t sysconf; /* System configuration */
627 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
628 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
629 rtclk83xx_t pit; /* Periodic Interval Timer */
630 gtm83xx_t gtm[2]; /* Global Timers Module */
631 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
632 arbiter83xx_t arbiter; /* System Arbiter Registers */
633 reset83xx_t reset; /* Reset Module */
634 clk83xx_t clk; /* System Clock Module */
635 pmc83xx_t pmc; /* Power Management Control Module */
636 gpio83xx_t gpio[1]; /* General purpose I/O module */
638 ddr83xx_t ddr; /* DDR Memory Controller Memory */
639 fsl_i2c_t i2c[2]; /* I2C Controllers */
641 duart83xx_t duart[2]; /* DUART */
643 fsl_lbus_t lbus; /* Local Bus Controller Registers */
645 spi8xxx_t spi; /* Serial Peripheral Interface */
646 dma83xx_t dma; /* DMA */
647 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
649 ios83xx_t ios; /* Sequencer */
650 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
652 pex83xx_t pciexp[2]; /* PCI Express Controller */
654 tdm83xx_t tdm; /* TDM Controller */
656 sata83xx_t sata[2]; /* SATA Controller */
658 usb83xx_t usb[1]; /* USB DR Controller */
661 tdmdmac83xx_t tdmdmac; /* TDM DMAC */
663 security83xx_t security;
665 serdes83xx_t serdes[1]; /* SerDes Registers */
669 #elif defined(CONFIG_MPC837X)
670 typedef struct immap {
671 sysconf83xx_t sysconf; /* System configuration */
672 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
673 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
674 rtclk83xx_t pit; /* Periodic Interval Timer */
675 gtm83xx_t gtm[2]; /* Global Timers Module */
676 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
677 arbiter83xx_t arbiter; /* System Arbiter Registers */
678 reset83xx_t reset; /* Reset Module */
679 clk83xx_t clk; /* System Clock Module */
680 pmc83xx_t pmc; /* Power Management Control Module */
681 gpio83xx_t gpio[2]; /* General purpose I/O module */
683 ddr83xx_t ddr; /* DDR Memory Controller Memory */
684 fsl_i2c_t i2c[2]; /* I2C Controllers */
686 duart83xx_t duart[2]; /* DUART */
688 fsl_lbus_t lbus; /* Local Bus Controller Registers */
690 spi8xxx_t spi; /* Serial Peripheral Interface */
691 dma83xx_t dma; /* DMA */
692 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
694 ios83xx_t ios; /* Sequencer */
695 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
697 pex83xx_t pciexp[2]; /* PCI Express Controller */
699 sata83xx_t sata[4]; /* SATA Controller */
701 usb83xx_t usb[1]; /* USB DR Controller */
704 sdhc83xx_t sdhc; /* SDHC Controller */
706 security83xx_t security;
708 serdes83xx_t serdes[2]; /* SerDes Registers */
710 rom83xx_t rom; /* On Chip ROM */
713 #elif defined(CONFIG_MPC8360)
714 typedef struct immap {
715 sysconf83xx_t sysconf; /* System configuration */
716 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
717 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
718 rtclk83xx_t pit; /* Periodic Interval Timer */
720 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
721 arbiter83xx_t arbiter; /* System Arbiter Registers */
722 reset83xx_t reset; /* Reset Module */
723 clk83xx_t clk; /* System Clock Module */
724 pmc83xx_t pmc; /* Power Management Control Module */
725 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
730 qepio83xx_t qepio; /* QE Parallel I/O ports */
731 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
733 ddr83xx_t ddr; /* DDR Memory Controller Memory */
734 fsl_i2c_t i2c[2]; /* I2C Controllers */
736 duart83xx_t duart[2]; /* DUART */
738 fsl_lbus_t lbus; /* Local Bus Controller Registers */
740 dma83xx_t dma; /* DMA */
741 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
743 ios83xx_t ios; /* Sequencer (IOS) */
744 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
746 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
748 security83xx_t security;
750 u8 qe[0x100000]; /* QE block */
753 #elif defined(CONFIG_MPC832X)
754 typedef struct immap {
755 sysconf83xx_t sysconf; /* System configuration */
756 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
757 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
758 rtclk83xx_t pit; /* Periodic Interval Timer */
759 gtm83xx_t gtm[2]; /* Global Timers Module */
760 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
761 arbiter83xx_t arbiter; /* System Arbiter Registers */
762 reset83xx_t reset; /* Reset Module */
763 clk83xx_t clk; /* System Clock Module */
764 pmc83xx_t pmc; /* Power Management Control Module */
765 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
770 qepio83xx_t qepio; /* QE Parallel I/O ports */
772 ddr83xx_t ddr; /* DDR Memory Controller Memory */
773 fsl_i2c_t i2c[2]; /* I2C Controllers */
775 duart83xx_t duart[2]; /* DUART */
777 fsl_lbus_t lbus; /* Local Bus Controller Registers */
779 dma83xx_t dma; /* DMA */
780 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
782 ios83xx_t ios; /* Sequencer (IOS) */
783 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
785 security83xx_t security;
787 u8 qe[0x100000]; /* QE block */
791 #endif /* __IMMAP_83xx__ */