2 * (C) Copyright 2004-2009 Freescale Semiconductor, Inc.
4 * MPC83xx Internal Memory Map
7 * Dave Liu <daveliu@freescale.com>
8 * Tanya Jiang <tanya.jiang@freescale.com>
9 * Mandy Lavi <mandy.lavi@freescale.com>
10 * Eran Liberty <liberty@freescale.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #ifndef __IMMAP_83xx__
29 #define __IMMAP_83xx__
31 #include <asm/types.h>
32 #include <asm/fsl_i2c.h>
33 #include <asm/mpc8xxx_spi.h>
34 #include <asm/fsl_lbc.h>
35 #include <asm/fsl_dma.h>
40 typedef struct law83xx {
41 u32 bar; /* LBIU local access window base address register */
42 u32 ar; /* LBIU local access window attribute register */
46 * System configuration registers
48 typedef struct sysconf83xx {
49 u32 immrbar; /* Internal memory map base address register */
51 u32 altcbar; /* Alternate configuration base address register */
53 law83xx_t lblaw[4]; /* LBIU local access window */
55 law83xx_t pcilaw[2]; /* PCI local access window */
57 law83xx_t pcielaw[2]; /* PCI Express local access window */
59 law83xx_t ddrlaw[2]; /* DDR local access window */
61 u32 sgprl; /* System General Purpose Register Low */
62 u32 sgprh; /* System General Purpose Register High */
63 u32 spridr; /* System Part and Revision ID Register */
65 u32 spcr; /* System Priority Configuration Register */
66 u32 sicrl; /* System I/O Configuration Register Low */
67 u32 sicrh; /* System I/O Configuration Register High */
69 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
70 u32 sidcr1; /* System I/O Delay Configuration Register 1 */
71 u32 ddrcdr; /* DDR Control Driver Register */
72 u32 ddrdsr; /* DDR Debug Status Register */
73 u32 obir; /* Output Buffer Impedance Register */
75 u32 pecr1; /* PCI Express control register 1 */
76 u32 pecr2; /* PCI Express control register 2 */
81 * Watch Dog Timer (WDT) Registers
83 typedef struct wdt83xx {
85 u32 swcrr; /* System watchdog control register */
86 u32 swcnr; /* System watchdog count register */
88 u16 swsrr; /* System watchdog service register */
93 * RTC/PIT Module Registers
95 typedef struct rtclk83xx {
96 u32 cnr; /* control register */
97 u32 ldr; /* load register */
98 u32 psr; /* prescale register */
99 u32 ctr; /* counter value field register */
100 u32 evr; /* event register */
101 u32 alr; /* alarm register */
106 * Global timer module
108 typedef struct gtm83xx {
109 u8 cfr1; /* Timer1/2 Configuration */
111 u8 cfr2; /* Timer3/4 Configuration */
113 u16 mdr1; /* Timer1 Mode Register */
114 u16 mdr2; /* Timer2 Mode Register */
115 u16 rfr1; /* Timer1 Reference Register */
116 u16 rfr2; /* Timer2 Reference Register */
117 u16 cpr1; /* Timer1 Capture Register */
118 u16 cpr2; /* Timer2 Capture Register */
119 u16 cnr1; /* Timer1 Counter Register */
120 u16 cnr2; /* Timer2 Counter Register */
121 u16 mdr3; /* Timer3 Mode Register */
122 u16 mdr4; /* Timer4 Mode Register */
123 u16 rfr3; /* Timer3 Reference Register */
124 u16 rfr4; /* Timer4 Reference Register */
125 u16 cpr3; /* Timer3 Capture Register */
126 u16 cpr4; /* Timer4 Capture Register */
127 u16 cnr3; /* Timer3 Counter Register */
128 u16 cnr4; /* Timer4 Counter Register */
129 u16 evr1; /* Timer1 Event Register */
130 u16 evr2; /* Timer2 Event Register */
131 u16 evr3; /* Timer3 Event Register */
132 u16 evr4; /* Timer4 Event Register */
133 u16 psr1; /* Timer1 Prescaler Register */
134 u16 psr2; /* Timer2 Prescaler Register */
135 u16 psr3; /* Timer3 Prescaler Register */
136 u16 psr4; /* Timer4 Prescaler Register */
141 * Integrated Programmable Interrupt Controller
143 typedef struct ipic83xx {
144 u32 sicfr; /* System Global Interrupt Configuration Register */
145 u32 sivcr; /* System Global Interrupt Vector Register */
146 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
147 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
148 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
150 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
151 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
152 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
154 u32 sepnr; /* System External Interrupt Pending Register */
155 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
156 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
157 u32 semsr; /* System External Interrupt Mask Register */
158 u32 secnr; /* System External Interrupt Control Register */
159 u32 sersr; /* System Error Status Register */
160 u32 sermr; /* System Error Mask Register */
161 u32 sercr; /* System Error Control Register */
163 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
164 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
165 u32 sefcr; /* System External Interrupt Force Register */
166 u32 serfr; /* System Error Force Register */
167 u32 scvcr; /* System Critical Interrupt Vector Register */
168 u32 smvcr; /* System Management Interrupt Vector Register */
173 * System Arbiter Registers
175 typedef struct arbiter83xx {
176 u32 acr; /* Arbiter Configuration Register */
177 u32 atr; /* Arbiter Timers Register */
179 u32 aer; /* Arbiter Event Register */
180 u32 aidr; /* Arbiter Interrupt Definition Register */
181 u32 amr; /* Arbiter Mask Register */
182 u32 aeatr; /* Arbiter Event Attributes Register */
183 u32 aeadr; /* Arbiter Event Address Register */
184 u32 aerr; /* Arbiter Event Response Register */
191 typedef struct reset83xx {
192 u32 rcwl; /* Reset Configuration Word Low Register */
193 u32 rcwh; /* Reset Configuration Word High Register */
195 u32 rsr; /* Reset Status Register */
196 u32 rmr; /* Reset Mode Register */
197 u32 rpr; /* Reset protection Register */
198 u32 rcr; /* Reset Control Register */
199 u32 rcer; /* Reset Control Enable Register */
206 typedef struct clk83xx {
207 u32 spmr; /* system PLL mode Register */
208 u32 occr; /* output clock control Register */
209 u32 sccr; /* system clock control Register */
214 * Power Management Control Module
216 typedef struct pmc83xx {
217 u32 pmccr; /* PMC Configuration Register */
218 u32 pmcer; /* PMC Event Register */
219 u32 pmcmr; /* PMC Mask Register */
220 u32 pmccr1; /* PMC Configuration Register 1 */
221 u32 pmccr2; /* PMC Configuration Register 2 */
226 * General purpose I/O module
228 typedef struct gpio83xx {
229 u32 dir; /* direction register */
230 u32 odr; /* open drain register */
231 u32 dat; /* data register */
232 u32 ier; /* interrupt event register */
233 u32 imr; /* interrupt mask register */
234 u32 icr; /* external interrupt control register */
239 * QE Ports Interrupts Registers
241 typedef struct qepi83xx {
243 u32 qepier; /* QE Ports Interrupt Event Register */
244 u32 qepimr; /* QE Ports Interrupt Mask Register */
245 u32 qepicr; /* QE Ports Interrupt Control Register */
250 * QE Parallel I/O Ports
252 typedef struct gpio_n {
253 u32 podr; /* Open Drain Register */
254 u32 pdat; /* Data Register */
255 u32 dir1; /* direction register 1 */
256 u32 dir2; /* direction register 2 */
257 u32 ppar1; /* Pin Assignment Register 1 */
258 u32 ppar2; /* Pin Assignment Register 2 */
261 typedef struct qegpio83xx {
262 gpio_n_t ioport[0x7];
267 * QE Secondary Bus Access Windows
269 typedef struct qesba83xx {
270 u32 lbmcsar; /* Local bus memory controller start address */
271 u32 sdmcsar; /* Secondary DDR memory controller start address */
273 u32 lbmcear; /* Local bus memory controller end address */
274 u32 sdmcear; /* Secondary DDR memory controller end address */
276 u32 lbmcar; /* Local bus memory controller attributes */
277 u32 sdmcar; /* Secondary DDR memory controller attributes */
282 * DDR Memory Controller Memory Map
284 typedef struct ddr_cs_bnds {
289 typedef struct ddr83xx {
290 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
292 u32 cs_config[4]; /* Chip Select x Configuration */
294 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
295 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
296 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
297 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
298 u32 sdram_cfg; /* SDRAM Control Configuration */
299 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
300 u32 sdram_mode; /* SDRAM Mode Configuration */
301 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
302 u32 sdram_md_cntl; /* SDRAM Mode Control */
303 u32 sdram_interval; /* SDRAM Interval Configuration */
304 u32 ddr_data_init; /* SDRAM Data Initialization */
306 u32 sdram_clk_cntl; /* SDRAM Clock Control */
308 u32 ddr_init_addr; /* DDR training initialization address */
309 u32 ddr_init_ext_addr; /* DDR training initialization extended address */
311 u32 ddr_ip_rev1; /* DDR IP block revision 1 */
312 u32 ddr_ip_rev2; /* DDR IP block revision 2 */
314 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
315 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
316 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
318 u32 capture_data_hi; /* Memory Data Path Read Capture High */
319 u32 capture_data_lo; /* Memory Data Path Read Capture Low */
320 u32 capture_ecc; /* Memory Data Path Read Capture ECC */
322 u32 err_detect; /* Memory Error Detect */
323 u32 err_disable; /* Memory Error Disable */
324 u32 err_int_en; /* Memory Error Interrupt Enable */
325 u32 capture_attributes; /* Memory Error Attributes Capture */
326 u32 capture_address; /* Memory Error Address Capture */
327 u32 capture_ext_address;/* Memory Error Extended Address Capture */
328 u32 err_sbe; /* Memory Single-Bit ECC Error Management */
337 typedef struct duart83xx {
338 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
339 u8 uier_udmb; /* combined register for UIER and UDMB */
340 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
341 u8 ulcr; /* line control register */
342 u8 umcr; /* MODEM control register */
343 u8 ulsr; /* line status register */
344 u8 umsr; /* MODEM status register */
345 u8 uscr; /* scratch register */
347 u8 udsr; /* DMA status register */
355 typedef struct dma83xx {
356 u32 res0[0xC]; /* 0x0-0x29 reseverd */
357 u32 omisr; /* 0x30 Outbound message interrupt status register */
358 u32 omimr; /* 0x34 Outbound message interrupt mask register */
359 u32 res1[0x6]; /* 0x38-0x49 reserved */
360 u32 imr0; /* 0x50 Inbound message register 0 */
361 u32 imr1; /* 0x54 Inbound message register 1 */
362 u32 omr0; /* 0x58 Outbound message register 0 */
363 u32 omr1; /* 0x5C Outbound message register 1 */
364 u32 odr; /* 0x60 Outbound doorbell register */
365 u32 res2; /* 0x64-0x67 reserved */
366 u32 idr; /* 0x68 Inbound doorbell register */
367 u32 res3[0x5]; /* 0x6C-0x79 reserved */
368 u32 imisr; /* 0x80 Inbound message interrupt status register */
369 u32 imimr; /* 0x84 Inbound message interrupt mask register */
370 u32 res4[0x1E]; /* 0x88-0x99 reserved */
371 struct fsl_dma dma[4];
375 * PCI Software Configuration Registers
377 typedef struct pciconf83xx {
385 * PCI Outbound Translation Register
387 typedef struct pci_outbound_window {
399 typedef struct ios83xx {
409 * PCI Controller Control and Status Registers
411 typedef struct pcictrl83xx {
447 typedef struct usb83xx {
454 typedef struct tsec83xx {
461 typedef struct security83xx {
468 struct pex_inbound_window {
475 struct pex_outbound_window {
482 struct pex_csb_bridge {
513 u32 pex_int_apio_vec1;
514 u32 pex_int_apio_vec2;
516 u32 pex_int_ppio_vec1;
517 u32 pex_int_ppio_vec2;
518 u32 pex_int_wdma_vec1;
519 u32 pex_int_wdma_vec2;
520 u32 pex_int_rdma_vec1;
521 u32 pex_int_rdma_vec2;
522 u32 pex_int_misc_vec;
524 u32 pex_int_axi_pio_enb;
525 u32 pex_int_axi_wdma_enb;
526 u32 pex_int_axi_rdma_enb;
527 u32 pex_int_axi_misc_enb;
528 u32 pex_int_axi_pio_stat;
529 u32 pex_int_axi_wdma_stat;
530 u32 pex_int_axi_rdma_stat;
531 u32 pex_int_axi_misc_stat;
533 struct pex_outbound_window pex_outbound_win[4];
540 struct pex_inbound_window pex_inbound_win[4];
543 typedef struct pex83xx {
544 u8 pex_cfg_header[0x404];
547 u32 pex_ack_replay_timeout;
554 u32 pex_aspm_req_timer;
556 u32 pex_ssvid_update;
566 u32 pex_pme_to_ack_tor;
568 u32 pex_ss_intr_mask;
570 struct pex_csb_bridge bridge;
577 typedef struct sata83xx {
584 typedef struct sdhc83xx {
591 typedef struct serdes83xx {
598 typedef struct rom83xx {
605 typedef struct tdm83xx {
612 typedef struct tdmdmac83xx {
616 #if defined(CONFIG_MPC834x)
617 typedef struct immap {
618 sysconf83xx_t sysconf; /* System configuration */
619 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
620 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
621 rtclk83xx_t pit; /* Periodic Interval Timer */
622 gtm83xx_t gtm[2]; /* Global Timers Module */
623 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
624 arbiter83xx_t arbiter; /* System Arbiter Registers */
625 reset83xx_t reset; /* Reset Module */
626 clk83xx_t clk; /* System Clock Module */
627 pmc83xx_t pmc; /* Power Management Control Module */
628 gpio83xx_t gpio[2]; /* General purpose I/O module */
633 ddr83xx_t ddr; /* DDR Memory Controller Memory */
634 fsl_i2c_t i2c[2]; /* I2C Controllers */
636 duart83xx_t duart[2]; /* DUART */
638 fsl_lbus_t lbus; /* Local Bus Controller Registers */
640 spi8xxx_t spi; /* Serial Peripheral Interface */
641 dma83xx_t dma; /* DMA */
642 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
643 ios83xx_t ios; /* Sequencer */
644 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
649 security83xx_t security;
653 #elif defined(CONFIG_MPC8313)
654 typedef struct immap {
655 sysconf83xx_t sysconf; /* System configuration */
656 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
657 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
658 rtclk83xx_t pit; /* Periodic Interval Timer */
659 gtm83xx_t gtm[2]; /* Global Timers Module */
660 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
661 arbiter83xx_t arbiter; /* System Arbiter Registers */
662 reset83xx_t reset; /* Reset Module */
663 clk83xx_t clk; /* System Clock Module */
664 pmc83xx_t pmc; /* Power Management Control Module */
665 gpio83xx_t gpio[1]; /* General purpose I/O module */
667 ddr83xx_t ddr; /* DDR Memory Controller Memory */
668 fsl_i2c_t i2c[2]; /* I2C Controllers */
670 duart83xx_t duart[2]; /* DUART */
672 fsl_lbus_t lbus; /* Local Bus Controller Registers */
674 spi8xxx_t spi; /* Serial Peripheral Interface */
675 dma83xx_t dma; /* DMA */
676 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
678 ios83xx_t ios; /* Sequencer */
679 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
684 security83xx_t security;
688 #elif defined(CONFIG_MPC8315)
689 typedef struct immap {
690 sysconf83xx_t sysconf; /* System configuration */
691 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
692 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
693 rtclk83xx_t pit; /* Periodic Interval Timer */
694 gtm83xx_t gtm[2]; /* Global Timers Module */
695 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
696 arbiter83xx_t arbiter; /* System Arbiter Registers */
697 reset83xx_t reset; /* Reset Module */
698 clk83xx_t clk; /* System Clock Module */
699 pmc83xx_t pmc; /* Power Management Control Module */
700 gpio83xx_t gpio[1]; /* General purpose I/O module */
702 ddr83xx_t ddr; /* DDR Memory Controller Memory */
703 fsl_i2c_t i2c[2]; /* I2C Controllers */
705 duart83xx_t duart[2]; /* DUART */
707 fsl_lbus_t lbus; /* Local Bus Controller Registers */
709 spi8xxx_t spi; /* Serial Peripheral Interface */
710 dma83xx_t dma; /* DMA */
711 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
713 ios83xx_t ios; /* Sequencer */
714 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
716 pex83xx_t pciexp[2]; /* PCI Express Controller */
718 tdm83xx_t tdm; /* TDM Controller */
720 sata83xx_t sata[2]; /* SATA Controller */
722 usb83xx_t usb[1]; /* USB DR Controller */
725 tdmdmac83xx_t tdmdmac; /* TDM DMAC */
727 security83xx_t security;
729 serdes83xx_t serdes[1]; /* SerDes Registers */
733 #elif defined(CONFIG_MPC837x)
734 typedef struct immap {
735 sysconf83xx_t sysconf; /* System configuration */
736 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
737 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
738 rtclk83xx_t pit; /* Periodic Interval Timer */
739 gtm83xx_t gtm[2]; /* Global Timers Module */
740 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
741 arbiter83xx_t arbiter; /* System Arbiter Registers */
742 reset83xx_t reset; /* Reset Module */
743 clk83xx_t clk; /* System Clock Module */
744 pmc83xx_t pmc; /* Power Management Control Module */
745 gpio83xx_t gpio[2]; /* General purpose I/O module */
747 ddr83xx_t ddr; /* DDR Memory Controller Memory */
748 fsl_i2c_t i2c[2]; /* I2C Controllers */
750 duart83xx_t duart[2]; /* DUART */
752 fsl_lbus_t lbus; /* Local Bus Controller Registers */
754 spi8xxx_t spi; /* Serial Peripheral Interface */
755 dma83xx_t dma; /* DMA */
756 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
758 ios83xx_t ios; /* Sequencer */
759 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
761 pex83xx_t pciexp[2]; /* PCI Express Controller */
763 sata83xx_t sata[4]; /* SATA Controller */
765 usb83xx_t usb[1]; /* USB DR Controller */
768 sdhc83xx_t sdhc; /* SDHC Controller */
770 security83xx_t security;
772 serdes83xx_t serdes[2]; /* SerDes Registers */
774 rom83xx_t rom; /* On Chip ROM */
777 #elif defined(CONFIG_MPC8360)
778 typedef struct immap {
779 sysconf83xx_t sysconf; /* System configuration */
780 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
781 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
782 rtclk83xx_t pit; /* Periodic Interval Timer */
784 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
785 arbiter83xx_t arbiter; /* System Arbiter Registers */
786 reset83xx_t reset; /* Reset Module */
787 clk83xx_t clk; /* System Clock Module */
788 pmc83xx_t pmc; /* Power Management Control Module */
789 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
794 qepio83xx_t qepio; /* QE Parallel I/O ports */
795 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
797 ddr83xx_t ddr; /* DDR Memory Controller Memory */
798 fsl_i2c_t i2c[2]; /* I2C Controllers */
800 duart83xx_t duart[2]; /* DUART */
802 fsl_lbus_t lbus; /* Local Bus Controller Registers */
804 dma83xx_t dma; /* DMA */
805 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
807 ios83xx_t ios; /* Sequencer (IOS) */
808 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
810 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
812 security83xx_t security;
814 u8 qe[0x100000]; /* QE block */
817 #elif defined(CONFIG_MPC832x)
818 typedef struct immap {
819 sysconf83xx_t sysconf; /* System configuration */
820 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
821 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
822 rtclk83xx_t pit; /* Periodic Interval Timer */
823 gtm83xx_t gtm[2]; /* Global Timers Module */
824 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
825 arbiter83xx_t arbiter; /* System Arbiter Registers */
826 reset83xx_t reset; /* Reset Module */
827 clk83xx_t clk; /* System Clock Module */
828 pmc83xx_t pmc; /* Power Management Control Module */
829 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
834 qepio83xx_t qepio; /* QE Parallel I/O ports */
836 ddr83xx_t ddr; /* DDR Memory Controller Memory */
837 fsl_i2c_t i2c[2]; /* I2C Controllers */
839 duart83xx_t duart[2]; /* DUART */
841 fsl_lbus_t lbus; /* Local Bus Controller Registers */
843 dma83xx_t dma; /* DMA */
844 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
846 ios83xx_t ios; /* Sequencer (IOS) */
847 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
849 security83xx_t security;
851 u8 qe[0x100000]; /* QE block */
855 #define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
856 #define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
857 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
858 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
859 #define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
860 #define CONFIG_SYS_MPC83xx_USB_ADDR \
861 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
862 #endif /* __IMMAP_83xx__ */