2 * timer.h -- ColdFire internal TIMER support defines.
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /****************************************************************************/
29 /****************************************************************************/
31 /****************************************************************************/
33 /****************************************************************************/
34 /* DMA Timer module registers */
35 typedef struct dtimer_ctrl {
36 u16 tmr; /* 0x00 Mode register */
37 u8 txmr; /* 0x02 Extended Mode register */
38 u8 ter; /* 0x03 Event register */
39 u32 trr; /* 0x04 Reference register */
40 u32 tcr; /* 0x08 Capture register */
41 u32 tcn; /* 0x0C Counter register */
44 /*Programmable Interrupt Timer */
45 typedef struct pit_ctrl {
46 u16 pcsr; /* 0x00 Control and Status Register */
47 u16 pmr; /* 0x02 Modulus Register */
48 u16 pcntr; /* 0x04 Count Register */
51 /*********************************************************************
53 *********************************************************************/
54 /* Bit definitions and macros for DTMR */
55 #define DTIM_DTMR_RST (0x0001) /* Reset */
56 #define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
57 #define DTIM_DTMR_FRR (0x0008) /* Free run/restart */
58 #define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
59 #define DTIM_DTMR_OM (0x0020) /* Output Mode */
60 #define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
61 #define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
62 #define DTIM_DTMR_RST_EN (0x0001)
63 #define DTIM_DTMR_RST_RST (0x0000)
64 #define DTIM_DTMR_CE_ANY (0x00C0)
65 #define DTIM_DTMR_CE_FALL (0x0080)
66 #define DTIM_DTMR_CE_RISE (0x0040)
67 #define DTIM_DTMR_CE_NONE (0x0000)
68 #define DTIM_DTMR_CLK_DTIN (0x0006)
69 #define DTIM_DTMR_CLK_DIV16 (0x0004)
70 #define DTIM_DTMR_CLK_DIV1 (0x0002)
71 #define DTIM_DTMR_CLK_STOP (0x0000)
73 /* Bit definitions and macros for DTXMR */
74 #define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
75 #define DTIM_DTXMR_DMAEN (0x80) /* DMA request */
77 /* Bit definitions and macros for DTER */
78 #define DTIM_DTER_CAP (0x01) /* Capture event */
79 #define DTIM_DTER_REF (0x02) /* Output reference event */
81 /*********************************************************************
83 * Programmable Interrupt Timer Modules (PIT)
85 *********************************************************************/
87 /* Bit definitions and macros for PCSR */
88 #define PIT_PCSR_EN (0x0001)
89 #define PIT_PCSR_RLD (0x0002)
90 #define PIT_PCSR_PIF (0x0004)
91 #define PIT_PCSR_PIE (0x0008)
92 #define PIT_PCSR_OVW (0x0010)
93 #define PIT_PCSR_HALTED (0x0020)
94 #define PIT_PCSR_DOZE (0x0040)
95 #define PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
97 /* Bit definitions and macros for PMR */
98 #define PIT_PMR_PM(x) (x)
100 /* Bit definitions and macros for PCNTR */
101 #define PIT_PCNTR_PC(x) (x)
103 /****************************************************************************/