2 * mcf5271.h -- Definitions for Motorola Coldfire 5271
4 * (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com>
5 * Based on mcf5272sim.h of uCLinux distribution:
6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
33 #define mbar_readShort(x) *((volatile unsigned short *) (CFG_MBAR + x))
34 #define mbar_readByte(x) *((volatile unsigned char *) (CFG_MBAR + x))
35 #define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
36 #define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
37 #define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
39 #define MCF_FMPLL_SYNCR 0x120000
40 #define MCF_FMPLL_SYNSR 0x120004
41 #define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24)
42 #define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19)
43 #define MCF_FMPLL_SYNSR_LOCK 0x8
45 #define MCF_WTM_WCR 0x140000
46 #define MCF_WTM_WCNTR 0x140004
47 #define MCF_WTM_WSR 0x140006
48 #define MCF_WTM_WCR_EN 0x0001
50 #define MCF_RCM_RCR 0x110000
51 #define MCF_RCM_RCR_FRCRSTOUT 0x40
52 #define MCF_RCM_RCR_SOFTRST 0x80
54 #define MCF_GPIO_PAR_AD 0x100040
55 #define MCF_GPIO_PAR_CS 0x100045
56 #define MCF_GPIO_PAR_SDRAM 0x100046
57 #define MCF_GPIO_PAR_FECI2C 0x100047
58 #define MCF_GPIO_PAR_UART 0x100048
60 #define MCF_CCM_CIR 0x11000A
61 #define MCF_CCM_CIR_PRN_MASK 0x3F
62 #define MCF_CCM_CIR_PIN_LEN 6
63 #define MCF_CCM_CIR_PIN_MCF5270 0x2e
64 #define MCF_CCM_CIR_PIN_MCF5271 0x80
66 #define MCF_GPIO_AD_ADDR23 0x80
67 #define MCF_GPIO_AD_ADDR22 0x40
68 #define MCF_GPIO_AD_ADDR21 0x20
69 #define MCF_GPIO_AD_DATAL 0x01
70 #define MCF_GPIO_AD_MASK 0xe1
72 #define MCF_GPIO_PAR_CS_PAR_CS2 0x04
74 #define MCF_GPIO_SDRAM_CSSDCS_00 0x00 /* CS[3:2] pins: CS3, CS2 */
75 #define MCF_GPIO_SDRAM_CSSDCS_01 0x40 /* CS[3:2] pins: CS3, SD_CS0 */
76 #define MCF_GPIO_SDRAM_CSSDCS_10 0x80 /* CS[3:2] pins: SD_CS1, SC2 */
77 #define MCF_GPIO_SDRAM_CSSDCS_11 0xc0 /* CS[3:2] pins: SD_CS1, SD_CS0 */
78 #define MCF_GPIO_SDRAM_SDWE 0x20 /* WE pin */
79 #define MCF_GPIO_SDRAM_SCAS 0x10 /* CAS pin */
80 #define MCF_GPIO_SDRAM_SRAS 0x08 /* RAS pin */
81 #define MCF_GPIO_SDRAM_SCKE 0x04 /* CKE pin */
82 #define MCF_GPIO_SDRAM_SDCS_00 0x00 /* SD_CS[0:1] pins: GPIO, GPIO */
83 #define MCF_GPIO_SDRAM_SDCS_01 0x01 /* SD_CS[0:1] pins: GPIO, SD_CS0 */
84 #define MCF_GPIO_SDRAM_SDCS_10 0x02 /* SD_CS[0:1] pins: SD_CS1, GPIO */
85 #define MCF_GPIO_SDRAM_SDCS_11 0x03 /* SD_CS[0:1] pins: SD_CS1, SD_CS0 */
87 #define MCF_GPIO_PAR_UART_U0RTS 0x0001
88 #define MCF_GPIO_PAR_UART_U0CTS 0x0002
89 #define MCF_GPIO_PAR_UART_U0TXD 0x0004
90 #define MCF_GPIO_PAR_UART_U0RXD 0x0008
91 #define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
92 #define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
94 #define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
96 #define MCF_SDRAMC_DCR 0x000040
97 #define MCF_SDRAMC_DACR0 0x000048
98 #define MCF_SDRAMC_DMR0 0x00004C
100 #define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
101 #define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
102 #define MCF_SDRAMC_DCR_IS 0x0800
103 #define MCF_SDRAMC_DCR_COC 0x1000
104 #define MCF_SDRAMC_DCR_NAM 0x2000
106 #define MCF_SDRAMC_DACRn_IP 0x00000008
107 #define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4)
108 #define MCF_SDRAMC_DACRn_MRS 0x00000040
109 #define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8)
110 #define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12)
111 #define MCF_SDRAMC_DACRn_RE 0x00008000
112 #define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18)
114 #define MCF_SDRAMC_DMRn_BAM_8M 0x007C0000
115 #define MCF_SDRAMC_DMRn_BAM_16M 0x00FC0000
116 #define MCF_SDRAMC_DMRn_V 0x00000001
118 #define MCFSIM_ICR1 0x000C41
120 #endif /* _MCF5271_H_ */