2 * mcf5329.h -- Definitions for Freescale Coldfire 5329
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /****************************************************************************/
30 /*********************************************************************
31 * System Control Module (SCM)
32 *********************************************************************/
34 /* Bit definition and macros for SCM_IPSBAR */
35 #define SCM_IPSBAR_BA(x) (((x)&0x03)<<30)
36 #define SCM_IPSBAR_V (0x00000001)
38 /* Bit definition and macros for SCM_RAMBAR */
39 #define SCM_RAMBAR_BA(x) (((x)&0xFFFF)<<16)
40 #define SCM_RAMBAR_BDE (0x00000200)
42 /* Bit definition and macros for SCM_CRSR */
43 #define SCM_CRSR_EXT (0x80)
45 /* Bit definitions and macros for SCM_CWCR */
46 #define SCM_CWCR_CWE (0x80)
47 #define SCM_CWCR_CWRI (0x40)
48 #define SCM_CWCR_CWT(x) (((x)&0x07)<<3)
49 #define SCM_CWCR_CWTA (0x04)
50 #define SCM_CWCR_CWTAVAL (0x02)
51 #define SCM_CWCR_CWTIC (0x01)
53 /* Bit definitions and macros for SCM_LPICR */
54 #define SCM_LPICR_ENBSTOP (0x80)
55 #define SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4)
56 #define SCM_LPICR_XLPM_IPL_ANY (0x00)
57 #define SCM_LPICR_XLPM_IPL_L2_7 (0x10)
58 #define SCM_LPICR_XLPM_IPL_L3_7 (0x20)
59 #define SCM_LPICR_XLPM_IPL_L4_7 (0x30)
60 #define SCM_LPICR_XLPM_IPL_L5_7 (0x40)
61 #define SCM_LPICR_XLPM_IPL_L6_7 (0x50)
62 #define SCM_LPICR_XLPM_IPL_L7 (0x70)
64 /* Bit definitions and macros for SCM_DMAREQC */
65 #define SCM_DMAREQC_EXT(x) (((x)&0x0F)<<16)
66 #define SCM_DMAREQC_EXT_ETPU (0x00080000)
67 #define SCM_DMAREQC_EXT_EXTDREQ2 (0x00040000)
68 #define SCM_DMAREQC_EXT_EXTDREQ1 (0x00020000)
69 #define SCM_DMAREQC_EXT_EXTDREQ0 (0x00010000)
70 #define SCM_DMAREQC_DMAC3(x) (((x)&0x0F)<<12)
71 #define SCM_DMAREQC_DMAC2(x) (((x)&0x0F)<<8)
72 #define SCM_DMAREQC_DMAC1(x) (((x)&0x0F)<<4)
73 #define SCM_DMAREQC_DMAC0(x) (((x)&0x0F))
74 #define SCM_DMAREQC_DMACn_DTMR0 (0x04)
75 #define SCM_DMAREQC_DMACn_DTMR1 (0x05)
76 #define SCM_DMAREQC_DMACn_DTMR2 (0x06)
77 #define SCM_DMAREQC_DMACn_DTMR3 (0x07)
78 #define SCM_DMAREQC_DMACn_UART0RX (0x08)
79 #define SCM_DMAREQC_DMACn_UART1RX (0x09)
80 #define SCM_DMAREQC_DMACn_UART2RX (0x0A)
81 #define SCM_DMAREQC_DMACn_UART0TX (0x0C)
82 #define SCM_DMAREQC_DMACn_UART1TX (0x0D)
83 #define SCM_DMAREQC_DMACn_UART3TX (0x0E)
85 /* Bit definitions and macros for SCM_MPARK */
86 #define SCM_MPARK_M2_P_EN (0x02000000)
87 #define SCM_MPARK_M3_PRTY_MSK (0x00C00000)
88 #define SCM_MPARK_M3_PRTY_4TH (0x00000000)
89 #define SCM_MPARK_M3_PRTY_3RD (0x00400000)
90 #define SCM_MPARK_M3_PRTY_2ND (0x00800000)
91 #define SCM_MPARK_M3_PRTY_1ST (0x00C00000)
92 #define SCM_MPARK_M2_PRTY_MSK (0x00300000)
93 #define SCM_MPARK_M2_PRTY_4TH (0x00000000)
94 #define SCM_MPARK_M2_PRTY_3RD (0x00100000)
95 #define SCM_MPARK_M2_PRTY_2ND (0x00200000)
96 #define SCM_MPARK_M2_PRTY_1ST (0x00300000)
97 #define SCM_MPARK_M0_PRTY_MSK (0x000C0000)
98 #define SCM_MPARK_M0_PRTY_4TH (0x00000000)
99 #define SCM_MPARK_M0_PRTY_3RD (0x00040000)
100 #define SCM_MPARK_M0_PRTY_2ND (0x00080000)
101 #define SCM_MPARK_M0_PRTY_1ST (0x000C0000)
102 #define SCM_MPARK_FIXED (0x00004000)
103 #define SCM_MPARK_TIMEOUT (0x00002000)
104 #define SCM_MPARK_PRKLAST (0x00001000)
105 #define SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0F)<<8)
107 /* Bit definitions and macros for SCM_MPR */
108 #define SCM_MPR_MPR3 (0x08)
109 #define SCM_MPR_MPR2 (0x04)
110 #define SCM_MPR_MPR1 (0x02)
111 #define SCM_MPR_MPR0 (0x01)
113 /* Bit definitions and macros for SCM_PACRn */
114 #define SCM_PACRn_LOCK1 (0x80)
115 #define SCM_PACRn_ACCESSCTRL1(x) (((x)&0x07)<<4)
116 #define SCM_PACRn_LOCK0 (0x08)
117 #define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
119 /* Bit definitions and macros for SCM_GPACR */
120 #define SCM_PACRn_LOCK (0x80)
121 #define SCM_PACRn_ACCESSCTRL0(x) (((x)&0x07))
123 /*********************************************************************
124 * SDRAM Controller (SDRAMC)
125 *********************************************************************/
126 /* Bit definitions and macros for SDRAMC_DCR */
127 #define SDRAMC_DCR_NAM (0x2000)
128 #define SDRAMC_DCR_COC (0x1000)
129 #define SDRAMC_DCR_IS (0x0800)
130 #define SDRAMC_DCR_RTIM_MASK (0x0C00)
131 #define SDRAMC_DCR_RTIM_3CLKS (0x0000)
132 #define SDRAMC_DCR_RTIM_6CLKS (0x0200)
133 #define SDRAMC_DCR_RTIM_9CLKS (0x0400)
134 #define SDRAMC_DCR_RC(x) (((x)&0xFF)<<8)
136 /* Bit definitions and macros for SDRAMC_DARCn */
137 #define SDRAMC_DARCn_BA(x) (((x)&0xFFFC)<<18)
138 #define SDRAMC_DARCn_RE (0x00008000)
139 #define SDRAMC_DARCn_CASL_MASK (0x00003000)
140 #define SDRAMC_DARCn_CASL_C0 (0x00000000)
141 #define SDRAMC_DARCn_CASL_C1 (0x00001000)
142 #define SDRAMC_DARCn_CASL_C2 (0x00002000)
143 #define SDRAMC_DARCn_CASL_C3 (0x00003000)
144 #define SDRAMC_DARCn_CBM_MASK (0x00000700)
145 #define SDRAMC_DARCn_CBM_CMD17 (0x00000000)
146 #define SDRAMC_DARCn_CBM_CMD18 (0x00000100)
147 #define SDRAMC_DARCn_CBM_CMD19 (0x00000200)
148 #define SDRAMC_DARCn_CBM_CMD20 (0x00000300)
149 #define SDRAMC_DARCn_CBM_CMD21 (0x00000400)
150 #define SDRAMC_DARCn_CBM_CMD22 (0x00000500)
151 #define SDRAMC_DARCn_CBM_CMD23 (0x00000600)
152 #define SDRAMC_DARCn_CBM_CMD24 (0x00000700)
153 #define SDRAMC_DARCn_IMRS (0x00000040)
154 #define SDRAMC_DARCn_PS_MASK (0x00000030)
155 #define SDRAMC_DARCn_PS_32 (0x00000000)
156 #define SDRAMC_DARCn_PS_16 (0x00000010)
157 #define SDRAMC_DARCn_PS_8 (0x00000020)
158 #define SDRAMC_DARCn_IP (0x00000008)
160 /* Bit definitions and macros for SDRAMC_DMRn */
161 #define SDRAMC_DMRn_BAM(x) (((x)&0x3FFF)<<18)
162 #define SDRAMC_DMRn_WP (0x00000100)
163 #define SDRAMC_DMRn_V (0x00000001)
165 /*********************************************************************
166 * FlexBus Chip Selects (FBCS)
167 *********************************************************************/
168 /* Bit definitions and macros for FBCS_CSMR */
169 #define FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<16)
170 #define FBCS_CSMR_BAM_4G (0xFFFF0000)
171 #define FBCS_CSMR_BAM_2G (0x7FFF0000)
172 #define FBCS_CSMR_BAM_1G (0x3FFF0000)
173 #define FBCS_CSMR_BAM_1024M (0x3FFF0000)
174 #define FBCS_CSMR_BAM_512M (0x1FFF0000)
175 #define FBCS_CSMR_BAM_256M (0x0FFF0000)
176 #define FBCS_CSMR_BAM_128M (0x07FF0000)
177 #define FBCS_CSMR_BAM_64M (0x03FF0000)
178 #define FBCS_CSMR_BAM_32M (0x01FF0000)
179 #define FBCS_CSMR_BAM_16M (0x00FF0000)
180 #define FBCS_CSMR_BAM_8M (0x007F0000)
181 #define FBCS_CSMR_BAM_4M (0x003F0000)
182 #define FBCS_CSMR_BAM_2M (0x001F0000)
183 #define FBCS_CSMR_BAM_1M (0x000F0000)
184 #define FBCS_CSMR_BAM_1024K (0x000F0000)
185 #define FBCS_CSMR_BAM_512K (0x00070000)
186 #define FBCS_CSMR_BAM_256K (0x00030000)
187 #define FBCS_CSMR_BAM_128K (0x00010000)
188 #define FBCS_CSMR_BAM_64K (0x00000000)
189 #define FBCS_CSMR_WP (0x00000100)
190 #define FBCS_CSMR_V (0x00000001)
192 /* Bit definitions and macros for FBCS_CSCR */
193 #define FBCS_CSCR_SRWS(x) (((x)&0x03)<<14)
194 #define FBCS_CSCR_IWS(x) (((x)&0x0F)<<10)
195 #define FBCS_CSCR_AA (0x0100)
196 #define FBCS_CSCR_PS_MASK (0x00C0)
197 #define FBCS_CSCR_PS_32 (0x0000)
198 #define FBCS_CSCR_PS_16 (0x0080)
199 #define FBCS_CSCR_PS_8 (0x0040)
200 #define FBCS_CSCR_BEM (0x0020)
201 #define FBCS_CSCR_BSTR (0x0010)
202 #define FBCS_CSCR_BSTW (0x0008)
203 #define FBCS_CSCR_SWWS(x) ((x)&0x07)
205 /*********************************************************************
206 * Queued Serial Peripheral Interface (QSPI)
207 *********************************************************************/
208 /* Bit definitions and macros for QSPI_QMR */
209 #define QSPI_QMR_MSTR (0x8000)
210 #define QSPI_QMR_DOHIE (0x4000)
211 #define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
212 #define QSPI_QMR_CPOL (0x0200)
213 #define QSPI_QMR_CPHA (0x0100)
214 #define QSPI_QMR_BAUD(x) ((x)&0x00FF)
216 /* Bit definitions and macros for QSPI_QDLYR */
217 #define QSPI_QDLYR_SPE (0x8000)
218 #define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
219 #define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
221 /* Bit definitions and macros for QSPI_QWR */
222 #define QSPI_QWR_HALT (0x8000)
223 #define QSPI_QWR_WREN (0x4000)
224 #define QSPI_QWR_WRTO (0x2000)
225 #define QSPI_QWR_CSIV (0x1000)
226 #define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
227 #define QSPI_QWR_NEWQP(x) ((x)&0x000F)
229 /* Bit definitions and macros for QSPI_QIR */
230 #define QSPI_QIR_WCEFB (0x8000)
231 #define QSPI_QIR_ABRTB (0x4000)
232 #define QSPI_QIR_ABRTL (0x1000)
233 #define QSPI_QIR_WCEFE (0x0800)
234 #define QSPI_QIR_ABRTE (0x0400)
235 #define QSPI_QIR_SPIFE (0x0100)
236 #define QSPI_QIR_WCEF (0x0008)
237 #define QSPI_QIR_ABRT (0x0004)
238 #define QSPI_QIR_SPIF (0x0001)
240 /* Bit definitions and macros for QSPI_QAR */
241 #define QSPI_QAR_ADDR(x) ((x)&0x003F)
243 /* Bit definitions and macros for QSPI_QDR */
244 #define QSPI_QDR_CONT (0x8000)
245 #define QSPI_QDR_BITSE (0x4000)
246 #define QSPI_QDR_DT (0x2000)
247 #define QSPI_QDR_DSCK (0x1000)
248 #define QSPI_QDR_QSPI_CS3 (0x0800)
249 #define QSPI_QDR_QSPI_CS2 (0x0400)
250 #define QSPI_QDR_QSPI_CS1 (0x0200)
251 #define QSPI_QDR_QSPI_CS0 (0x0100)
253 /*********************************************************************
254 * Interrupt Controller (INTC)
255 *********************************************************************/
256 #define INT0_LO_RSVD0 (0)
257 #define INT0_LO_EPORT1 (1)
258 #define INT0_LO_EPORT2 (2)
259 #define INT0_LO_EPORT3 (3)
260 #define INT0_LO_EPORT4 (4)
261 #define INT0_LO_EPORT5 (5)
262 #define INT0_LO_EPORT6 (6)
263 #define INT0_LO_EPORT7 (7)
264 #define INT0_LO_SCM (8)
265 #define INT0_LO_DMA0 (9)
266 #define INT0_LO_DMA1 (10)
267 #define INT0_LO_DMA2 (11)
268 #define INT0_LO_DMA3 (12)
269 #define INT0_LO_UART0 (13)
270 #define INT0_LO_UART1 (14)
271 #define INT0_LO_UART2 (15)
272 #define INT0_LO_RSVD1 (16)
273 #define INT0_LO_I2C (17)
274 #define INT0_LO_QSPI (18)
275 #define INT0_LO_DTMR0 (19)
276 #define INT0_LO_DTMR1 (20)
277 #define INT0_LO_DTMR2 (21)
278 #define INT0_LO_DTMR3 (22)
279 #define INT0_LO_FEC_TXF (23)
280 #define INT0_LO_FEC_TXB (24)
281 #define INT0_LO_FEC_UN (25)
282 #define INT0_LO_FEC_RL (26)
283 #define INT0_LO_FEC_RXF (27)
284 #define INT0_LO_FEC_RXB (28)
285 #define INT0_LO_FEC_MII (29)
286 #define INT0_LO_FEC_LC (30)
287 #define INT0_LO_FEC_HBERR (31)
288 #define INT0_HI_FEC_GRA (32)
289 #define INT0_HI_FEC_EBERR (33)
290 #define INT0_HI_FEC_BABT (34)
291 #define INT0_HI_FEC_BABR (35)
292 #define INT0_HI_PIT0 (36)
293 #define INT0_HI_PIT1 (37)
294 #define INT0_HI_PIT2 (38)
295 #define INT0_HI_PIT3 (39)
296 #define INT0_HI_RNG (40)
297 #define INT0_HI_SKHA (41)
298 #define INT0_HI_MDHA (42)
299 #define INT0_HI_CAN1_BUF0I (43)
300 #define INT0_HI_CAN1_BUF1I (44)
301 #define INT0_HI_CAN1_BUF2I (45)
302 #define INT0_HI_CAN1_BUF3I (46)
303 #define INT0_HI_CAN1_BUF4I (47)
304 #define INT0_HI_CAN1_BUF5I (48)
305 #define INT0_HI_CAN1_BUF6I (49)
306 #define INT0_HI_CAN1_BUF7I (50)
307 #define INT0_HI_CAN1_BUF8I (51)
308 #define INT0_HI_CAN1_BUF9I (52)
309 #define INT0_HI_CAN1_BUF10I (53)
310 #define INT0_HI_CAN1_BUF11I (54)
311 #define INT0_HI_CAN1_BUF12I (55)
312 #define INT0_HI_CAN1_BUF13I (56)
313 #define INT0_HI_CAN1_BUF14I (57)
314 #define INT0_HI_CAN1_BUF15I (58)
315 #define INT0_HI_CAN1_ERRINT (59)
316 #define INT0_HI_CAN1_BOFFINT (60)
320 #define INT1_LO_CAN1_BUF0I (8)
321 #define INT1_LO_CAN1_BUF1I (9)
322 #define INT1_LO_CAN1_BUF2I (10)
323 #define INT1_LO_CAN1_BUF3I (11)
324 #define INT1_LO_CAN1_BUF4I (12)
325 #define INT1_LO_CAN1_BUF5I (13)
326 #define INT1_LO_CAN1_BUF6I (14)
327 #define INT1_LO_CAN1_BUF7I (15)
328 #define INT1_LO_CAN1_BUF8I (16)
329 #define INT1_LO_CAN1_BUF9I (17)
330 #define INT1_LO_CAN1_BUF10I (18)
331 #define INT1_LO_CAN1_BUF11I (19)
332 #define INT1_LO_CAN1_BUF12I (20)
333 #define INT1_LO_CAN1_BUF13I (21)
334 #define INT1_LO_CAN1_BUF14I (22)
335 #define INT1_LO_CAN1_BUF15I (23)
336 #define INT1_LO_CAN1_ERRINT (24)
337 #define INT1_LO_CAN1_BOFFINT (25)
339 #define INT1_LO_ETPU_TC0F (27)
340 #define INT1_LO_ETPU_TC1F (28)
341 #define INT1_LO_ETPU_TC2F (29)
342 #define INT1_LO_ETPU_TC3F (30)
343 #define INT1_LO_ETPU_TC4F (31)
344 #define INT1_HI_ETPU_TC5F (32)
345 #define INT1_HI_ETPU_TC6F (33)
346 #define INT1_HI_ETPU_TC7F (34)
347 #define INT1_HI_ETPU_TC8F (35)
348 #define INT1_HI_ETPU_TC9F (36)
349 #define INT1_HI_ETPU_TC10F (37)
350 #define INT1_HI_ETPU_TC11F (38)
351 #define INT1_HI_ETPU_TC12F (39)
352 #define INT1_HI_ETPU_TC13F (40)
353 #define INT1_HI_ETPU_TC14F (41)
354 #define INT1_HI_ETPU_TC15F (42)
355 #define INT1_HI_ETPU_TC16F (43)
356 #define INT1_HI_ETPU_TC17F (44)
357 #define INT1_HI_ETPU_TC18F (45)
358 #define INT1_HI_ETPU_TC19F (46)
359 #define INT1_HI_ETPU_TC20F (47)
360 #define INT1_HI_ETPU_TC21F (48)
361 #define INT1_HI_ETPU_TC22F (49)
362 #define INT1_HI_ETPU_TC23F (50)
363 #define INT1_HI_ETPU_TC24F (51)
364 #define INT1_HI_ETPU_TC25F (52)
365 #define INT1_HI_ETPU_TC26F (53)
366 #define INT1_HI_ETPU_TC27F (54)
367 #define INT1_HI_ETPU_TC28F (55)
368 #define INT1_HI_ETPU_TC29F (56)
369 #define INT1_HI_ETPU_TC30F (57)
370 #define INT1_HI_ETPU_TC31F (58)
371 #define INT1_HI_ETPU_TGIF (59)
373 /* Bit definitions and macros for INTC_IPRH */
374 #define INTC_IPRH_INT63 (0x80000000)
375 #define INTC_IPRH_INT62 (0x40000000)
376 #define INTC_IPRH_INT61 (0x20000000)
377 #define INTC_IPRH_INT60 (0x10000000)
378 #define INTC_IPRH_INT59 (0x08000000)
379 #define INTC_IPRH_INT58 (0x04000000)
380 #define INTC_IPRH_INT57 (0x02000000)
381 #define INTC_IPRH_INT56 (0x01000000)
382 #define INTC_IPRH_INT55 (0x00800000)
383 #define INTC_IPRH_INT54 (0x00400000)
384 #define INTC_IPRH_INT53 (0x00200000)
385 #define INTC_IPRH_INT52 (0x00100000)
386 #define INTC_IPRH_INT51 (0x00080000)
387 #define INTC_IPRH_INT50 (0x00040000)
388 #define INTC_IPRH_INT49 (0x00020000)
389 #define INTC_IPRH_INT48 (0x00010000)
390 #define INTC_IPRH_INT47 (0x00008000)
391 #define INTC_IPRH_INT46 (0x00004000)
392 #define INTC_IPRH_INT45 (0x00002000)
393 #define INTC_IPRH_INT44 (0x00001000)
394 #define INTC_IPRH_INT43 (0x00000800)
395 #define INTC_IPRH_INT42 (0x00000400)
396 #define INTC_IPRH_INT41 (0x00000200)
397 #define INTC_IPRH_INT40 (0x00000100)
398 #define INTC_IPRH_INT39 (0x00000080)
399 #define INTC_IPRH_INT38 (0x00000040)
400 #define INTC_IPRH_INT37 (0x00000020)
401 #define INTC_IPRH_INT36 (0x00000010)
402 #define INTC_IPRH_INT35 (0x00000008)
403 #define INTC_IPRH_INT34 (0x00000004)
404 #define INTC_IPRH_INT33 (0x00000002)
405 #define INTC_IPRH_INT32 (0x00000001)
407 /* Bit definitions and macros for INTC_IPRL */
408 #define INTC_IPRL_INT31 (0x80000000)
409 #define INTC_IPRL_INT30 (0x40000000)
410 #define INTC_IPRL_INT29 (0x20000000)
411 #define INTC_IPRL_INT28 (0x10000000)
412 #define INTC_IPRL_INT27 (0x08000000)
413 #define INTC_IPRL_INT26 (0x04000000)
414 #define INTC_IPRL_INT25 (0x02000000)
415 #define INTC_IPRL_INT24 (0x01000000)
416 #define INTC_IPRL_INT23 (0x00800000)
417 #define INTC_IPRL_INT22 (0x00400000)
418 #define INTC_IPRL_INT21 (0x00200000)
419 #define INTC_IPRL_INT20 (0x00100000)
420 #define INTC_IPRL_INT19 (0x00080000)
421 #define INTC_IPRL_INT18 (0x00040000)
422 #define INTC_IPRL_INT17 (0x00020000)
423 #define INTC_IPRL_INT16 (0x00010000)
424 #define INTC_IPRL_INT15 (0x00008000)
425 #define INTC_IPRL_INT14 (0x00004000)
426 #define INTC_IPRL_INT13 (0x00002000)
427 #define INTC_IPRL_INT12 (0x00001000)
428 #define INTC_IPRL_INT11 (0x00000800)
429 #define INTC_IPRL_INT10 (0x00000400)
430 #define INTC_IPRL_INT9 (0x00000200)
431 #define INTC_IPRL_INT8 (0x00000100)
432 #define INTC_IPRL_INT7 (0x00000080)
433 #define INTC_IPRL_INT6 (0x00000040)
434 #define INTC_IPRL_INT5 (0x00000020)
435 #define INTC_IPRL_INT4 (0x00000010)
436 #define INTC_IPRL_INT3 (0x00000008)
437 #define INTC_IPRL_INT2 (0x00000004)
438 #define INTC_IPRL_INT1 (0x00000002)
439 #define INTC_IPRL_INT0 (0x00000001)
441 /* Bit definitions and macros for INTC_IRLR */
442 #define INTC_IRLRn(x) (((x)&0x7F)<<1)
444 /* Bit definitions and macros for INTC_IACKLPRn */
445 #define INTC_IACKLPRn_LEVEL(x) (((x)&0x07)<<4)
446 #define INTC_IACKLPRn_PRI(x) ((x)&0x0F)
448 /* Bit definitions and macros for INTC_ICRnx */
449 #define INTC_ICRnx_IL(x) (((x)&0x07)<<3)
450 #define INTC_ICRnx_IP(x) ((x)&0x07)
452 /*********************************************************************
453 * General Purpose I/O (GPIO)
454 *********************************************************************/
455 /* Bit definitions and macros for GPIO_PODR */
456 #define GPIO_PODR_ADDR(x) (((x)&0x07)<<5)
457 #define GPIO_PODR_ADDR_MASK (0xE0)
458 #define GPIO_PODR_BS(x) ((x)&0x0F)
459 #define GPIO_PODR_BS_MASK (0x0F)
460 #define GPIO_PODR_CS(x) (((x)&0x7F)<<1)
461 #define GPIO_PODR_CS_MASK (0xFE)
462 #define GPIO_PODR_SDRAM(X) ((x)&0x3F)
463 #define GPIO_PODR_SDRAM_MASK (0x3F)
464 #define GPIO_PODR_FECI2C(x) GPIO_PODR_BS(x)
465 #define GPIO_PODR_FECI2C_MASK GPIO_PODR_BS_MASK
466 #define GPIO_PODR_UARTH(x) ((x)&0x03)
467 #define GPIO_PODR_UARTH_MASK (0x03)
468 #define GPIO_PODR_QSPI(x) ((x)&0x1F)
469 #define GPIO_PODR_QSPI_MASK (0x1F)
470 #define GPIO_PODR_ETPU(x) ((x)&0x07)
471 #define GPIO_PODR_ETPU_MASK (0x07)
473 /* Bit definitions and macros for GPIO_PDDR */
474 #define GPIO_PDDR_ADDR(x) GPIO_PODR_ADDR(x)
475 #define GPIO_PDDR_ADDR_MASK GPIO_PODR_ADDR_MASK
476 #define GPIO_PDDR_BS(x) GPIO_PODR_BS(x)
477 #define GPIO_PDDR_BS_MASK GPIO_PODR_BS_MASK
478 #define GPIO_PDDR_CS(x) GPIO_PODR_CS(x)
479 #define GPIO_PDDR_CS_MASK GPIO_PODR_CS_MASK
480 #define GPIO_PDDR_SDRAM(X) GPIO_PODR_SDRAM(X)
481 #define GPIO_PDDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
482 #define GPIO_PDDR_FECI2C(x) GPIO_PDDR_BS(x)
483 #define GPIO_PDDR_FECI2C_MASK GPIO_PDDR_BS_MASK
484 #define GPIO_PDDR_UARTH(x) GPIO_PODR_UARTH(x)
485 #define GPIO_PDDR_UARTH_MASK GPIO_PODR_UARTH_MASK
486 #define GPIO_PDDR_QSPI(x) GPIO_PODR_QSPI(x)
487 #define GPIO_PDDR_QSPI_MASK GPIO_PODR_QSPI_MASK
488 #define GPIO_PDDR_ETPU(x) GPIO_PODR_ETPU(x)
489 #define GPIO_PDDR_ETPU_MASK GPIO_PODR_ETPU_MASK
491 /* Bit definitions and macros for GPIO_PPDSDR */
492 #define GPIO_PPDSDR_ADDR(x) GPIO_PODR_ADDR(x)
493 #define GPIO_PPDSDR_ADDR_MASK GPIO_PODR_ADDR_MASK
494 #define GPIO_PPDSDR_BS(x) GPIO_PODR_BS(x)
495 #define GPIO_PPDSDR_BS_MASK GPIO_PODR_BS_MASK
496 #define GPIO_PPDSDR_CS(x) GPIO_PODR_CS(x)
497 #define GPIO_PPDSDR_CS_MASK GPIO_PODR_CS_MASK
498 #define GPIO_PPDSDR_SDRAM(X) GPIO_PODR_SDRAM(X)
499 #define GPIO_PPDSDR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
500 #define GPIO_PPDSDR_FECI2C(x) GPIO_PPDSDR_BS(x)
501 #define GPIO_PPDSDR_FECI2C_MASK GPIO_PPDSDR_BS_MASK
502 #define GPIO_PPDSDR_UARTH(x) GPIO_PODR_UARTH(x)
503 #define GPIO_PPDSDR_UARTH_MASK GPIO_PODR_UARTH_MASK
504 #define GPIO_PPDSDR_QSPI(x) GPIO_PODR_QSPI(x)
505 #define GPIO_PPDSDR_QSPI_MASK GPIO_PODR_QSPI_MASK
506 #define GPIO_PPDSDR_ETPU(x) GPIO_PODR_ETPU(x)
507 #define GPIO_PPDSDR_ETPU_MASK GPIO_PODR_ETPU_MASK
509 /* Bit definitions and macros for GPIO_PCLRR */
510 #define GPIO_PCLRR_ADDR(x) GPIO_PODR_ADDR(x)
511 #define GPIO_PCLRR_ADDR_MASK GPIO_PODR_ADDR_MASK
512 #define GPIO_PCLRR_BS(x) GPIO_PODR_BS(x)
513 #define GPIO_PCLRR_BS_MASK GPIO_PODR_BS_MASK
514 #define GPIO_PCLRR_CS(x) GPIO_PODR_CS(x)
515 #define GPIO_PCLRR_CS_MASK GPIO_PODR_CS_MASK
516 #define GPIO_PCLRR_SDRAM(X) GPIO_PODR_SDRAM(X)
517 #define GPIO_PCLRR_SDRAM_MASK GPIO_PODR_SDRAM_MASK
518 #define GPIO_PCLRR_FECI2C(x) GPIO_PCLRR_BS(x)
519 #define GPIO_PCLRR_FECI2C_MASK GPIO_PCLRR_BS_MASK
520 #define GPIO_PCLRR_UARTH(x) GPIO_PODR_UARTH(x)
521 #define GPIO_PCLRR_UARTH_MASK GPIO_PODR_UARTH_MASK
522 #define GPIO_PCLRR_QSPI(x) GPIO_PODR_QSPI(x)
523 #define GPIO_PCLRR_QSPI_MASK GPIO_PODR_QSPI_MASK
524 #define GPIO_PCLRR_ETPU(x) GPIO_PODR_ETPU(x)
525 #define GPIO_PCLRR_ETPU_MASK GPIO_PODR_ETPU_MASK
527 /* Bit definitions and macros for GPIO_PAR */
528 #define GPIO_PAR_AD_ADDR23 (0x80)
529 #define GPIO_PAR_AD_ADDR22 (0x40)
530 #define GPIO_PAR_AD_ADDR21 (0x20)
531 #define GPIO_PAR_AD_DATAL (0x01)
532 #define GPIO_PAR_BUSCTL_OE (0x4000)
533 #define GPIO_PAR_BUSCTL_TA (0x1000)
534 #define GPIO_PAR_BUSCTL_TEA(x) (((x)&0x03)<<10)
535 #define GPIO_PAR_BUSCTL_TEA_MASK (0x0C00)
536 #define GPIO_PAR_BUSCTL_TEA_GPIO (0x0400)
537 #define GPIO_PAR_BUSCTL_TEA_DREQ1 (0x0800)
538 #define GPIO_PAR_BUSCTL_TEA_EXTBUS (0x0C00)
539 #define GPIO_PAR_BUSCTL_RWB (0x0100)
540 #define GPIO_PAR_BUSCTL_TSIZ1 (0x0040)
541 #define GPIO_PAR_BUSCTL_TSIZ0 (0x0010)
542 #define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<2)
543 #define GPIO_PAR_BUSCTL_TS_MASK (0x0C)
544 #define GPIO_PAR_BUSCTL_TS_GPIO (0x04)
545 #define GPIO_PAR_BUSCTL_TS_DACK2 (0x08)
546 #define GPIO_PAR_BUSCTL_TS_EXTBUS (0x0C)
547 #define GPIO_PAR_BUSCTL_TIP(x) ((x)&0x03)
548 #define GPIO_PAR_BUSCTL_TIP_MASK (0x03)
549 #define GPIO_PAR_BUSCTL_TIP_GPIO (0x01)
550 #define GPIO_PAR_BUSCTL_TIP_DREQ0 (0x02)
551 #define GPIO_PAR_BUSCTL_TIP_EXTBUS (0x03)
552 #define GPIO_PAR_BS(x) ((x)&0x0F)
553 #define GPIO_PAR_BS_MASK (0x0F)
554 #define GPIO_PAR_CS(x) (((x)&0x7F)<<1)
555 #define GPIO_PAR_CS_MASK (0xFE)
556 #define GPIO_PAR_CS_CS7 (0x80)
557 #define GPIO_PAR_CS_CS6 (0x40)
558 #define GPIO_PAR_CS_CS5 (0x20)
559 #define GPIO_PAR_CS_CS4 (0x10)
560 #define GPIO_PAR_CS_CS3 (0x08)
561 #define GPIO_PAR_CS_CS2 (0x04)
562 #define GPIO_PAR_CS_CS1 (0x02)
563 #define GPIO_PAR_CS_SD3 GPIO_PAR_CS_CS3
564 #define GPIO_PAR_CS_SD2 GPIO_PAR_CS_CS2
565 #define GPIO_PAR_SDRAM_CSSDCS(x) (((x)&0x03)<<6)
566 #define GPIO_PAR_SDRAM_CSSDCS_MASK (0xC0)
567 #define GPIO_PAR_SDRAM_SDWE (0x20)
568 #define GPIO_PAR_SDRAM_SCAS (0x10)
569 #define GPIO_PAR_SDRAM_SRAS (0x08)
570 #define GPIO_PAR_SDRAM_SCKE (0x04)
571 #define GPIO_PAR_SDRAM_SDCS(x) ((x)&0x03)
572 #define GPIO_PAR_SDRAM_SDCS_MASK (0x03)
573 #define GPIO_PAR_FECI2C_EMDC(x) (((x)&0x03)<<6)
574 #define GPIO_PAR_FECI2C_EMDC_MASK (0xC0)
575 #define GPIO_PAR_FECI2C_EMDC_U2TXD (0x40)
576 #define GPIO_PAR_FECI2C_EMDC_I2CSCL (0x80)
577 #define GPIO_PAR_FECI2C_EMDC_FECEMDC (0xC0)
578 #define GPIO_PAR_FECI2C_EMDIO(x) (((x)&0x03)<<4)
579 #define GPIO_PAR_FECI2C_EMDIO_MASK (0x30)
580 #define GPIO_PAR_FECI2C_EMDIO_U2RXD (0x10)
581 #define GPIO_PAR_FECI2C_EMDIO_I2CSDA (0x20)
582 #define GPIO_PAR_FECI2C_EMDIO_FECEMDIO (0x30)
583 #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
584 #define GPIO_PAR_FECI2C_SCL_MASK (0x0C)
585 #define GPIO_PAR_FECI2C_SCL_CAN0RX (0x08)
586 #define GPIO_PAR_FECI2C_SCL_I2CSCL (0x0C)
587 #define GPIO_PAR_FECI2C_SDA(x) ((x)&0x03)
588 #define GPIO_PAR_FECI2C_SDA_MASK (0x03)
589 #define GPIO_PAR_FECI2C_SDA_CAN0TX (0x02)
590 #define GPIO_PAR_FECI2C_SDA_I2CSDA (0x03)
591 #define GPIO_PAR_UART_DREQ2 (0x8000)
592 #define GPIO_PAR_UART_CAN1EN (0x4000)
593 #define GPIO_PAR_UART_U2RXD (0x2000)
594 #define GPIO_PAR_UART_U2TXD (0x1000)
595 #define GPIO_PAR_UART_U1RXD(x) (((x)&0x03)<<10)
596 #define GPIO_PAR_UART_U1RXD_MASK (0x0C00)
597 #define GPIO_PAR_UART_U1RXD_CAN0RX (0x0800)
598 #define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
599 #define GPIO_PAR_UART_U1TXD(x) (((x)&0x03)<<8)
600 #define GPIO_PAR_UART_U1TXD_MASK (0x0300)
601 #define GPIO_PAR_UART_U1TXD_CAN0TX (0x0200)
602 #define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
603 #define GPIO_PAR_UART_U1CTS(x) (((x)&0x03)<<6)
604 #define GPIO_PAR_UART_U1CTS_MASK (0x00C0)
605 #define GPIO_PAR_UART_U1CTS_U2CTS (0x0080)
606 #define GPIO_PAR_UART_U1CTS_U1CTS (0x00C0)
607 #define GPIO_PAR_UART_U1RTS(x) (((x)&0x03)<<4)
608 #define GPIO_PAR_UART_U1RTS_MASK (0x0030)
609 #define GPIO_PAR_UART_U1RTS_U2RTS (0x0020)
610 #define GPIO_PAR_UART_U1RTS_U1RTS (0x0030)
611 #define GPIO_PAR_UART_U0RXD (0x0008)
612 #define GPIO_PAR_UART_U0TXD (0x0004)
613 #define GPIO_PAR_UART_U0CTS (0x0002)
614 #define GPIO_PAR_UART_U0RTS (0x0001)
615 #define GPIO_PAR_QSPI_CS1(x) (((x)&0x03)<<6)
616 #define GPIO_PAR_QSPI_CS1_MASK (0xC0)
617 #define GPIO_PAR_QSPI_CS1_SDRAMSCKE (0x80)
618 #define GPIO_PAR_QSPI_CS1_QSPICS1 (0xC0)
619 #define GPIO_PAR_QSPI_CS0 (0x20)
620 #define GPIO_PAR_QSPI_DIN(x) (((x)&0x03)<<3)
621 #define GPIO_PAR_QSPI_DIN_MASK (0x18)
622 #define GPIO_PAR_QSPI_DIN_I2CSDA (0x10)
623 #define GPIO_PAR_QSPI_DIN_QSPIDIN (0x18)
624 #define GPIO_PAR_QSPI_DOUT (0x04)
625 #define GPIO_PAR_QSPI_SCK(x) ((x)&0x03)
626 #define GPIO_PAR_QSPI_SCK_MASK (0x03)
627 #define GPIO_PAR_QSPI_SCK_I2CSCL (0x02)
628 #define GPIO_PAR_QSPI_SCK_QSPISCK (0x03)
629 #define GPIO_PAR_DT3IN(x) (((x)&0x03)<<14)
630 #define GPIO_PAR_DT3IN_MASK (0xC000)
631 #define GPIO_PAR_DT3IN_QSPICS2 (0x4000)
632 #define GPIO_PAR_DT3IN_U2CTS (0x8000)
633 #define GPIO_PAR_DT3IN_DT3IN (0xC000)
634 #define GPIO_PAR_DT2IN(x) (((x)&0x03)<<12)
635 #define GPIO_PAR_DT2IN_MASK (0x3000)
636 #define GPIO_PAR_DT2IN_DT2OUT (0x1000)
637 #define GPIO_PAR_DT2IN_DREQ2 (0x2000)
638 #define GPIO_PAR_DT2IN_DT2IN (0x3000)
639 #define GPIO_PAR_DT1IN(x) (((x)&0x03)<<10)
640 #define GPIO_PAR_DT1IN_MASK (0x0C00)
641 #define GPIO_PAR_DT1IN_DT1OUT (0x0400)
642 #define GPIO_PAR_DT1IN_DREQ1 (0x0800)
643 #define GPIO_PAR_DT1IN_DT1IN (0x0C00)
644 #define GPIO_PAR_DT0IN(x) (((x)&0x03)<<8)
645 #define GPIO_PAR_DT0IN_MASK (0x0300)
646 #define GPIO_PAR_DT0IN_DREQ0 (0x0200)
647 #define GPIO_PAR_DT0IN_DT0IN (0x0300)
648 #define GPIO_PAR_DT3OUT(x) (((x)&0x03)<<6)
649 #define GPIO_PAR_DT3OUT_MASK (0x00C0)
650 #define GPIO_PAR_DT3OUT_QSPICS3 (0x0040)
651 #define GPIO_PAR_DT3OUT_U2RTS (0x0080)
652 #define GPIO_PAR_DT3OUT_DT3OUT (0x00C0)
653 #define GPIO_PAR_DT2OUT(x) (((x)&0x03)<<4)
654 #define GPIO_PAR_DT2OUT_MASK (0x0030)
655 #define GPIO_PAR_DT2OUT_DACK2 (0x0020)
656 #define GPIO_PAR_DT2OUT_DT2OUT (0x0030)
657 #define GPIO_PAR_DT1OUT(x) (((x)&0x03)<<2)
658 #define GPIO_PAR_DT1OUT_MASK (0x000C)
659 #define GPIO_PAR_DT1OUT_DACK1 (0x0008)
660 #define GPIO_PAR_DT1OUT_DT1OUT (0x000C)
661 #define GPIO_PAR_DT0OUT(x) ((x)&0x03)
662 #define GPIO_PAR_DT0OUT_MASK (0x0003)
663 #define GPIO_PAR_DT0OUT_DACK0 (0x0002)
664 #define GPIO_PAR_DT0OUT_DT0OUT (0x0003)
665 #define GPIO_PAR_ETPU_TCRCLK (0x04)
666 #define GPIO_PAR_ETPU_UTPU_ODIS (0x02)
667 #define GPIO_PAR_ETPU_LTPU_ODIS (0x01)
669 /* Bit definitions and macros for GPIO_DSCR */
670 #define GPIO_DSCR_EIM_EIM1 (0x10)
671 #define GPIO_DSCR_EIM_EIM0 (0x01)
672 #define GPIO_DSCR_ETPU_ETPU31_24 (0x40)
673 #define GPIO_DSCR_ETPU_ETPU23_16 (0x10)
674 #define GPIO_DSCR_ETPU_ETPU15_8 (0x04)
675 #define GPIO_DSCR_ETPU_ETPU7_0 (0x01)
676 #define GPIO_DSCR_FECI2C_FEC (0x10)
677 #define GPIO_DSCR_FECI2C_I2C (0x01)
678 #define GPIO_DSCR_UART_IRQ (0x40)
679 #define GPIO_DSCR_UART_UART2 (0x10)
680 #define GPIO_DSCR_UART_UART1 (0x04)
681 #define GPIO_DSCR_UART_UART0 (0x01)
682 #define GPIO_DSCR_QSPI_QSPI (0x01)
683 #define GPIO_DSCR_TIMER (0x01)
685 /*********************************************************************
686 * Chip Configuration Module (CCM)
687 *********************************************************************/
688 /* Bit definitions and macros for CCM_RCR */
689 #define CCM_RCR_SOFTRST (0x80)
690 #define CCM_RCR_FRCRSTOUT (0x40)
692 /* Bit definitions and macros for CCM_RSR */
693 #define CCM_RSR_SOFT (0x20)
694 #define CCM_RSR_WDR (0x10)
695 #define CCM_RSR_POR (0x08)
696 #define CCM_RSR_EXT (0x04)
697 #define CCM_RSR_LOC (0x02)
698 #define CCM_RSR_LOL (0x01)
700 /* Bit definitions and macros for CCM_CCR */
701 #define CCM_CCR_LOAD (0x8000)
702 #define CCM_CCR_SZEN (0x0040)
703 #define CCM_CCR_PSTEN (0x0020)
704 #define CCM_CCR_BME (0x0008)
705 #define CCM_CCR_BMT(x) ((x)&0x07)
706 #define CCM_CCR_BMT_MASK (0x0007)
707 #define CCM_CCR_BMT_64K (0x0000)
708 #define CCM_CCR_BMT_32K (0x0001)
709 #define CCM_CCR_BMT_16K (0x0002)
710 #define CCM_CCR_BMT_8K (0x0003)
711 #define CCM_CCR_BMT_4K (0x0004)
712 #define CCM_CCR_BMT_2K (0x0005)
713 #define CCM_CCR_BMT_1K (0x0006)
714 #define CCM_CCR_BMT_512 (0x0007)
716 /* Bit definitions and macros for CCM_RCON */
717 #define CCM_RCON_RCSC(x) (((x)&0x0003)<<8)
718 #define CCM_RCON_RLOAD (0x0020)
719 #define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3)
720 #define CCM_RCON_BOOTPS_MASK (0x0018)
721 #define CCM_RCON_BOOTPS_32 (0x0018)
722 #define CCM_RCON_BOOTPS_16 (0x0008)
723 #define CCM_RCON_BOOTPS_8 (0x0010)
724 #define CCM_RCON_MODE (0x0001)
726 /* Bit definitions and macros for CCM_CIR */
727 #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
728 #define CCM_CIR_PRN(x) ((x)&0x003F)
730 /*********************************************************************
732 *********************************************************************/
733 /* Bit definitions and macros for PLL_SYNCR */
734 #define PLL_SYNCR_MFD(x) (((x)&0x07)<<24)
735 #define PLL_SYNCR_MFD_MASK (0x07000000)
736 #define PLL_SYNCR_RFC(x) (((x)&0x07)<<19)
737 #define PLL_SYNCR_RFC_MASK (0x00380000)
738 #define PLL_SYNCR_LOCEN (0x00040000)
739 #define PLL_SYNCR_LOLRE (0x00020000)
740 #define PLL_SYNCR_LOCRE (0x00010000)
741 #define PLL_SYNCR_DISCLK (0x00008000)
742 #define PLL_SYNCR_LOLIRQ (0x00004000)
743 #define PLL_SYNCR_LOCIRQ (0x00002000)
744 #define PLL_SYNCR_RATE (0x00001000)
745 #define PLL_SYNCR_DEPTH(x) (((x)&0x03)<<10)
746 #define PLL_SYNCR_EXP(x) ((x)&0x03FF)
748 /* Bit definitions and macros for PLL_SYNSR */
749 #define PLL_SYNSR_LOLF (0x00000200)
750 #define PLL_SYNSR_LOC (0x00000100)
751 #define PLL_SYNSR_MODE (0x00000080)
752 #define PLL_SYNSR_PLLSEL (0x00000040)
753 #define PLL_SYNSR_PLLREF (0x00000020)
754 #define PLL_SYNSR_LOCKS (0x00000010)
755 #define PLL_SYNSR_LOCK (0x00000008)
756 #define PLL_SYNSR_LOCF (0x00000004)
757 #define PLL_SYNSR_CALDONE (0x00000002)
758 #define PLL_SYNSR_CALPASS (0x00000001)
760 /*********************************************************************
762 *********************************************************************/
763 #define EPORT_EPPAR_EPPA7(x) (((x)&0x03)<<14)
764 #define EPORT_EPPAR_EPPA6(x) (((x)&0x03)<<12)
765 #define EPORT_EPPAR_EPPA5(x) (((x)&0x03)<<10)
766 #define EPORT_EPPAR_EPPA4(x) (((x)&0x03)<<8)
767 #define EPORT_EPPAR_EPPA3(x) (((x)&0x03)<<6)
768 #define EPORT_EPPAR_EPPA2(x) (((x)&0x03)<<4)
769 #define EPORT_EPPAR_EPPA1(x) (((x)&0x03)<<2)
771 #define EPORT_EPDDR_EPDD7(x) EPORT_EPPAR_EPPA7(x)
772 #define EPORT_EPDDR_EPDD6(x) EPORT_EPPAR_EPPA6(x)
773 #define EPORT_EPDDR_EPDD5(x) EPORT_EPPAR_EPPA5(x)
774 #define EPORT_EPDDR_EPDD4(x) EPORT_EPPAR_EPPA4(x)
775 #define EPORT_EPDDR_EPDD3(x) EPORT_EPPAR_EPPA3(x)
776 #define EPORT_EPDDR_EPDD2(x) EPORT_EPPAR_EPPA2(x)
777 #define EPORT_EPDDR_EPDD1(x) EPORT_EPPAR_EPPA1(x)
779 #define EPORT_EPIER_EPIE7 (0x80)
780 #define EPORT_EPIER_EPIE6 (0x40)
781 #define EPORT_EPIER_EPIE5 (0x20)
782 #define EPORT_EPIER_EPIE4 (0x10)
783 #define EPORT_EPIER_EPIE3 (0x08)
784 #define EPORT_EPIER_EPIE2 (0x04)
785 #define EPORT_EPIER_EPIE1 (0x02)
787 #define EPORT_EPDR_EPDR7 EPORT_EPIER_EPIE7
788 #define EPORT_EPDR_EPDR6 EPORT_EPIER_EPIE6
789 #define EPORT_EPDR_EPDR5 EPORT_EPIER_EPIE5
790 #define EPORT_EPDR_EPDR4 EPORT_EPIER_EPIE4
791 #define EPORT_EPDR_EPDR3 EPORT_EPIER_EPIE3
792 #define EPORT_EPDR_EPDR2 EPORT_EPIER_EPIE2
793 #define EPORT_EPDR_EPDR1 EPORT_EPIER_EPIE1
795 #define EPORT_EPPDR_EPPDR7 EPORT_EPIER_EPIE7
796 #define EPORT_EPPDR_EPPDR6 EPORT_EPIER_EPIE6
797 #define EPORT_EPPDR_EPPDR5 EPORT_EPIER_EPIE5
798 #define EPORT_EPPDR_EPPDR4 EPORT_EPIER_EPIE4
799 #define EPORT_EPPDR_EPPDR3 EPORT_EPIER_EPIE3
800 #define EPORT_EPPDR_EPPDR2 EPORT_EPIER_EPIE2
801 #define EPORT_EPPDR_EPPDR1 EPORT_EPIER_EPIE1
803 /*********************************************************************
804 * Watchdog Timer Modules (WTM)
805 *********************************************************************/
806 /* Bit definitions and macros for WTM_WCR */
807 #define WTM_WCR_WAIT (0x0008)
808 #define WTM_WCR_DOZE (0x0004)
809 #define WTM_WCR_HALTED (0x0002)
810 #define WTM_WCR_EN (0x0001)
812 /*********************************************************************
813 * FlexCAN Module (CAN)
814 *********************************************************************/
815 /* Bit definitions and macros for CAN_CANMCR */
816 #define CANMCR_MDIS (0x80000000)
817 #define CANMCR_FRZ (0x40000000)
818 #define CANMCR_HALT (0x10000000)
819 #define CANMCR_NORDY (0x08000000)
820 #define CANMCR_SOFTRST (0x02000000)
821 #define CANMCR_FRZACK (0x01000000)
822 #define CANMCR_SUPV (0x00800000)
823 #define CANMCR_LPMACK (0x00100000)
824 #define CANMCR_MAXMB(x) (((x)&0x0F))
826 /* Bit definitions and macros for CAN_CANCTRL */
827 #define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
828 #define CANCTRL_RJW(x) (((x)&0x03)<<22)
829 #define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
830 #define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
831 #define CANCTRL_BOFFMSK (0x00008000)
832 #define CANCTRL_ERRMSK (0x00004000)
833 #define CANCTRL_CLKSRC (0x00002000)
834 #define CANCTRL_LPB (0x00001000)
835 #define CANCTRL_SMP (0x00000080)
836 #define CANCTRL_BOFFREC (0x00000040)
837 #define CANCTRL_TSYNC (0x00000020)
838 #define CANCTRL_LBUF (0x00000010)
839 #define CANCTRL_LOM (0x00000008)
840 #define CANCTRL_PROPSEG(x) (((x)&0x07))
842 /* Bit definitions and macros for CAN_TIMER */
843 #define TIMER_TIMER(x) ((x)&0xFFFF)
845 /* Bit definitions and macros for CAN_RXGMASK */
846 #define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
848 /* Bit definitions and macros for CAN_ERRCNT */
849 #define ERRCNT_TXECTR(x) (((x)&0xFF))
850 #define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
852 /* Bit definitions and macros for CAN_ERRSTAT */
853 #define ERRSTAT_BITERR1 (0x00008000)
854 #define ERRSTAT_BITERR0 (0x00004000)
855 #define ERRSTAT_ACKERR (0x00002000)
856 #define ERRSTAT_CRCERR (0x00001000)
857 #define ERRSTAT_FRMERR (0x00000800)
858 #define ERRSTAT_STFERR (0x00000400)
859 #define ERRSTAT_TXWRN (0x00000200)
860 #define ERRSTAT_RXWRN (0x00000100)
861 #define ERRSTAT_IDLE (0x00000080)
862 #define ERRSTAT_TXRX (0x00000040)
863 #define ERRSTAT_FLT_BUSOFF (0x00000020)
864 #define ERRSTAT_FLT_PASSIVE (0x00000010)
865 #define ERRSTAT_FLT_ACTIVE (0x00000000)
866 #define ERRSTAT_BOFFINT (0x00000004)
867 #define ERRSTAT_ERRINT (0x00000002)
869 /* Bit definitions and macros for CAN_IMASK */
870 #define IMASK_BUF15M (0x00008000)
871 #define IMASK_BUF14M (0x00004000)
872 #define IMASK_BUF13M (0x00002000)
873 #define IMASK_BUF12M (0x00001000)
874 #define IMASK_BUF11M (0x00000800)
875 #define IMASK_BUF10M (0x00000400)
876 #define IMASK_BUF9M (0x00000200)
877 #define IMASK_BUF8M (0x00000100)
878 #define IMASK_BUF7M (0x00000080)
879 #define IMASK_BUF6M (0x00000040)
880 #define IMASK_BUF5M (0x00000020)
881 #define IMASK_BUF4M (0x00000010)
882 #define IMASK_BUF3M (0x00000008)
883 #define IMASK_BUF2M (0x00000004)
884 #define IMASK_BUF1M (0x00000002)
885 #define IMASK_BUF0M (0x00000001)
887 /* Bit definitions and macros for CAN_IFLAG */
888 #define IFLAG_BUF15I (0x00008000)
889 #define IFLAG_BUF14I (0x00004000)
890 #define IFLAG_BUF13I (0x00002000)
891 #define IFLAG_BUF12I (0x00001000)
892 #define IFLAG_BUF11I (0x00000800)
893 #define IFLAG_BUF10I (0x00000400)
894 #define IFLAG_BUF9I (0x00000200)
895 #define IFLAG_BUF8I (0x00000100)
896 #define IFLAG_BUF7I (0x00000080)
897 #define IFLAG_BUF6I (0x00000040)
898 #define IFLAG_BUF5I (0x00000020)
899 #define IFLAG_BUF4I (0x00000010)
900 #define IFLAG_BUF3I (0x00000008)
901 #define IFLAG_BUF2I (0x00000004)
902 #define IFLAG_BUF1I (0x00000002)
903 #define IFLAG_BUF0I (0x00000001)
905 #endif /* mcf5235_h */
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